112G PAM4 PCB Guide: Loss, Vias and Release Checks

November 4th, 2026

A 112G PAM4 PCB is not qualified by choosing a low-loss laminate and routing a nominal differential impedance. The complete electrical channel—package, traces, vias, connector launches and receiving circuitry—must meet the requirements of the selected interface. Start by identifying the exact lane rate, channel class and measurement reference planes. Then agree the stackup, models and manufacturing controls before releasing fabrication data.

This guide separates rate calculations from compliance limits and explains what engineers and PCB buyers should exchange. It does not prescribe a universal trace width, reach or backdrill depth: those depend on the actual construction and channel.

Photorealistic illustration of a network switch circuit board and connector cages — AI-generated physical-scene illustration; not a customer board or evidence of tested link performance.

What Does 112G PAM4 Mean?

PAM4 uses four amplitude levels to encode two bits per symbol. Consequently, an illustrative gross rate of 112.0 Gb/s corresponds to 56 GBd. However, “112G” is also used as a technology-family label. A specific interface may use another exact rate; payload throughput additionally depends on coding and forward error correction.

Do not infer the electrical specification from a switch port’s aggregate data rate. A port can contain several lanes, and its optical and host electrical interfaces need not have identical lane arrangements. Record the governing specification and revision, SerDes mode, lane count and gross bit rate first.

Detailed Rate Parameters and Their Practical Meaning

For ideal PAM4 encoding, symbol rate equals gross bit rate divided by two. Symbol interval is the reciprocal of symbol rate; the Nyquist frequency is half the symbol rate. These calculations describe the signaling rate, not the required analog bandwidth of every device or instrument.

Rate examples calculated from the stated gross bit rates—not universal interface requirements
Parameter	112.0 Gb/s PAM4 example	106.25 Gb/s PAM4 example	Design meaning
Bits per symbol	2	2	Four encoded amplitude levels
Symbol rate	56 GBd	53.125 GBd	Use the selected mode, not a rounded family name
Symbol interval	17.857 ps	18.824 ps	State whether timing budgets use symbol or bit intervals
Nyquist frequency	28 GHz	26.5625 GHz	A useful channel evaluation frequency, not a brick-wall bandwidth

A reference clock frequency is a separate parameter. It must match the SerDes clock architecture, with the specified jitter integration band and operating conditions. It must not be substituted for the serial baud rate.

PAM4 vs NRZ: Lower Baud Rate, Tighter Vertical Separation

At the same gross bit rate, PAM4 halves the symbol rate relative to binary NRZ. That reduces the fundamental frequency burden, but introduces three eyes and smaller adjacent-level spacing. With the same ideal outer-level voltage span and equally spaced levels, adjacent PAM4 levels are separated by one-third of that span. Real receiver tolerance also depends on noise, linearity, jitter and equalization.

Signaling comparison at an illustrative 112.0 Gb/s gross lane rate
Item	NRZ	PAM4	Trade-off
Levels / bits per symbol	2 / 1	4 / 2	PAM4 carries more information per symbol
Symbol rate	112 GBd	56 GBd	PAM4 reduces the rate-related channel bandwidth burden
Nyquist frequency	56 GHz	28 GHz	Neither value alone specifies an instrument bandwidth
Eye structure	One eye	Three eyes	PAM4 requires level and eye-specific evaluation
Selection risk	Assuming bandwidth is sufficient	Assuming equalization fixes all impairments	Evaluate the complete specified link

Define the Whole Channel Before Allocating Loss

Build a block list from transmitter reference plane to receiver reference plane. Include package models when required, every routed segment, layer transition, connector and applicable test fixture. Assign ownership of each model. A missing launch can make a simulation optimistic; including it in both a connector model and a PCB model can count its loss twice.

Insertion loss at one frequency is not a complete channel specification. Return loss, crosstalk, mode conversion and frequency-dependent behavior matter too. OIF defines multiple channel classes rather than one universal “112G reach.” Use the selected agreement and device requirements, not an unrelated backplane example, to establish the actual limits.

Select the Laminate Construction, Not Just a Material Name

Request the proposed laminate family, glass styles, resin content, cured dielectric thickness and associated electrical property data. Dk and Df depend on test method and conditions; values from different methods are not automatically interchangeable. The stackup used for simulation should match the construction that will actually be built.

Compare candidate constructions on modeled channel performance, fabrication availability and reliability requirements. A lower quoted Df is not by itself proof of a better finished channel. A thicker dielectric may permit wider conductors, but can change via geometry, board thickness and connector integration. Have the fabricator return the final impedance geometry for approval.

Include Copper Roughness and Finished Geometry

Conductor roughness contributes to high-frequency loss and can affect propagation. Specify the foil/interface information needed by the field solver and verify whether the model represents the relevant treated surfaces. Avoid mixing roughness parameters or models without understanding their definitions.

Finished trace width, thickness and cross-sectional shape are more useful than nominal artwork alone. Ask which geometry the impedance solver assumes and how process tolerances are evaluated. Do not claim a channel is robust simply because a single nominal stackup meets an impedance target.

Treat Connector Launches as Electromagnetic Structures

A connector’s headline data-rate label does not qualify its PCB footprint in a different stackup. Pads, antipads, reference-plane transitions, nearby ground structures and the connector itself form a coupled structure. Use a vendor-supported footprint and model for the relevant configuration, then reconcile the model boundary with the PCB extraction.

Before modifying a recommended footprint for routing convenience, identify whether it changes the modeled launch. A smaller pad may reduce one discontinuity while compromising assembly margin. Evaluate the electrical and manufacturing consequences together.

Photorealistic illustration of a high-frequency evaluation board with coaxial edge launches — AI-generated physical-scene illustration of launch hardware; geometry is illustrative, not a validated 112G layout.

Control Via Stubs, Return Paths and Backdrill Boundaries

A layer transition must preserve a suitable signal and return-current path. Analyze the via barrel, unused stub, pads, antipads and surrounding return structures together. A generic instruction to “add ground vias” is not a substitute for a configuration-specific model.

If backdrilling is required, provide drill side, target layer, keep-out requirements and an agreed residual-stub tolerance. Check the tolerance against board thickness, layer position and the fabricator’s process. Do not specify an impractical zero stub, or assume that every via needs backdrilling regardless of its electrical role.

Manage Pair Skew Without Creating a Different Problem

Match the relevant electrical path, including breakout and transitions, rather than only CAD centerline lengths. Local asymmetry, different reference environments and material effects can change delay. Tight meanders used to remove a displayed mismatch can introduce coupling and impedance disturbances.

For scale only, 0.5 ps is about 2.8% of a 17.857 ps symbol interval. This calculation is not an allowable-skew specification. Obtain the actual budget from the interface and device requirements, and distinguish intra-pair skew from lane-to-lane timing.

Keep Power Integrity and Reference Clock Requirements in Scope

A passive channel can be acceptable while the assembled system fails because of supply noise or clocking behavior. Follow the SerDes vendor’s power, decoupling and reference clock recommendations. Specify how clock jitter is measured; a single unexplained femtosecond number is not a transferable qualification.

Power integrity review and channel review should share physical constraints. Changing a reference plane, clearance or power distribution feature to solve one issue can affect the return path of another. Review such changes before the final extraction rather than after manufacturing release.

Correlate Models and Measurements at Matching Reference Planes

Record S-parameter port ordering, reference impedance, frequency range and de-embedding assumptions. Check that cascaded blocks use compatible definitions. The measurement fixture and launch must be included or removed consistently; otherwise measured and simulated results can disagree for reasons unrelated to the production trace.

For an active link, document transmitter settings, receiver equalization, operating conditions, test pattern and the relevant error/compliance method. A clear-looking eye screenshot alone does not establish compliance. A coupon also cannot prove that every populated connector and package transition behaves identically.

Photorealistic illustration of coaxial cables and a passive PCB coupon on a measurement bench — AI-generated physical-scene illustration; no measured loss, eye opening or compliance result is represented.

Manufacturing Release Checklist: Files, Owners and Acceptance

Release a controlled package rather than an email saying “112G capable.” Identify the stackup revision, final routing revision, approved launch geometry and models. Define who may approve material substitutions, copper changes, backdrill changes and CAM edits affecting the channel.

Practical engineering-to-fabrication handoff
Deliverable	What to specify	What it does not prove
Stackup and impedance drawing	Construction, finished geometry, target and tolerance, reference layers	Complete channel compliance
Via and backdrill definition	Layer transitions, drill side, residual-stub requirement, approval boundary	Acceptable connector launch without modeling
Channel model package	Ports, reference planes, versions, extraction assumptions	Correlation with hardware unless measured
Coupon and inspection plan	Structure represented, measurement method, acceptance criteria	Performance of every assembled system path
Change-control record	Substitution restrictions and named engineering approval route	That an unreviewed “equivalent” material is interchangeable

Before approval, confirm: exact rate and channel class; complete block ownership; nominal and tolerance-aware extraction; no duplicated launch; agreed fabrication limits; documented test conditions; and a plan to resolve failed correlation. Electrical testing for shorts and opens remains necessary, but is not a high-frequency channel measurement.

FAQ

Is 112G PAM4 always 56 GBd?

Exactly 112.0 Gb/s gross PAM4 corresponds to 56 GBd. However, a product described as 112G-class can use a different exact rate in a selected protocol mode. Read the interface specification and device configuration before calculating Nyquist frequency or choosing a model and test setup.

Does a 400G port mean each PCB lane runs at 400 Gb/s?

No. Aggregate port throughput can be distributed across multiple electrical or optical lanes. Establish which side of the interface is being discussed and obtain its lane count, modulation and exact gross rate. The aggregate label alone does not define the PCB channel or a suitable SerDes component.

Can ordinary FR-4 be used for a short 112G channel?

Do not decide from the broad FR-4 label alone. Evaluate the actual construction, length, transitions and material properties against the applicable channel requirements. A short route is not automatically acceptable, and a low-loss material is not automatically necessary or sufficient for every design. Confirm the proposed stackup through analysis and validation.

Is a nominal differential impedance enough to approve the board?

No. Impedance is one part of the channel. Frequency-dependent insertion and return loss, crosstalk, mode conversion, transitions and active-device requirements also matter. An impedance coupon can verify the represented transmission-line structure but does not replace evaluation of the complete routed and assembled link.

Should every high-speed via be backdrilled?

Not automatically. The unused stub and full transition must be evaluated for the actual stackup and channel. Backdrilling adds manufacturing constraints and needs defined tolerances. Some transitions may meet requirements without it; others may need a different layer strategy or via structure. Use modeled behavior rather than a universal rule.

Can equalization compensate for any PCB loss?

No. Equalization operates within the transmitter and receiver’s supported capabilities and the applicable test assumptions. It does not make arbitrary reflections, crosstalk, noise or mode conversion harmless. State the equalization configuration when comparing simulation and measurements, and evaluate the specified channel rather than relying on an optimistic eye plot.

Does a 56G component label mean it supports a 112G PAM4 lane?

No. Gbit/s and GBd are not interchangeable. A component marketed for a particular data-rate family must be checked against its supported baud rates, modulation modes and exact operating conditions. Do not infer 112 Gb/s compatibility merely because a datasheet or marketing page includes the number 56.

What should be sent for a manufacturing feasibility review?

Send the stackup, target impedance and tolerances, relevant routing geometry, via and backdrill definitions, required material construction and controlled fabrication data. Include any substitution restrictions and validation requirements. Keep SerDes and complete-channel qualification responsibilities explicit; a fabrication review alone does not certify an assembled link.

References and Technical Scope

Samtec: a case study in a 112Gbps-PAM4 silicon and connector test platform.
OIF: implementation agreements and applicable channel definitions; select the required agreement and revision rather than assuming one universal reach.
Texas Instruments: 112G and 224G PAM4 SerDes clocking.
Rogers: transmission-line materials and copper roughness considerations.

Rate and timing examples are mathematical illustrations, not guaranteed performance or fabrication capability. Design limits must come from the applicable interface, device documentation and approved construction.

Request a PCB Manufacturing Review

For a PCB fabrication review, send your controlled stackup and fabrication package to sales@bestpcbs.com. Best Technology can review the requested construction and confirm applicable manufacturing details before quotation. Start from the Best Technology website; do not treat a quotation as a substitute for complete-channel electrical validation.

Glass PCB Guide: Glass-Core Substrates, TGVs and Limits

November 4th, 2026

A glass PCB substrate uses a solid glass material as part of its interconnect structure; it is not the same as FR-4, which contains glass reinforcement in a resin composite. In advanced packaging, a glass core can support build-up wiring and through-glass vias, or TGVs. Its usefulness depends on the completed metallized structure, not transparency alone.

This guide focuses on glass-core packaging and interconnect selection—not decorative clear circuit boards. It separates raw-panel data, formed holes, metallized vias and qualified assemblies so engineers can evaluate a proposed construction without mistaking a material sample for a production-ready substrate.

Copper-patterned glass substrate coupon beside a clear glass panel — AI-generated physical-scene illustration of glass electronic substrates; not a Best Technology production sample, factory photograph or qualification result.

What Does Glass PCB Mean in Advanced Packaging?

In this context, glass is a core or interposer material carrying an engineered conductor system. It may sit inside a package structure that also includes copper and polymer build-up layers; it does not mean that every layer is glass.

SCHOTT’s advanced IC packaging overview distinguishes glass-core substrate applications from other glass roles. Ask where the glass sits in the stack and what electrical connections cross it. A temporary carrier wafer, an optical window and a permanent interconnect core have different functions, even if their starting material looks similar.

Glass Core vs FR-4 and Silicon Interposers

Compare the intended interconnect level and qualified process, not a general claim that one substrate is “better.” A motherboard, package substrate and fine-pitch interposer can belong to different manufacturing and acceptance systems.

Option	What to evaluate	Selection boundary
Glass-reinforced organic PCB	Established board construction, routing and assembly needs	Glass fibers do not make FR-4 a solid-glass core
Organic package substrate	Package-scale build-up routing and qualified interconnect	Not interchangeable with an ordinary board stackup
Glass core or interposer	Selected glass, TGVs, metallization and build-up integration	Raw-glass properties do not qualify the complete substrate
Silicon interposer	Interconnect density and the specific integration platform	Process, electrical behavior and cost must be compared at the same function

A fair comparison holds die count, I/O requirements, routing, package size, electrical budget and reliability target constant. Otherwise a material comparison can quietly become a comparison of different products.

Green glass-reinforced PCB coupon beside a separate clear glass substrate — AI-generated physical-scene illustration. A glass-reinforced polymer board and a solid-glass panel are different constructions.

Detailed Glass Panel Parameters and Their Boundaries

Read each value against a named glass product and condition. SCHOTT publishes the following examples for its glass-panel offering; availability and limits depend on glass type and thickness.

Panel property	Published example	Boundary
CTE, 20–300°C	3.2, 3.3, 5.0 or 7.2 ppm/K	Different material choices, not one universal glass value
Panel format	510 × 515 mm	Raw-panel format, not usable finished routing area
Initial thickness	0.5–1.1 mm	Other thicknesses require supplier confirmation
Thickness tolerance range	±10–20 µm	Depends on glass type and thickness
Total thickness variation	≤10–20 µm	Not the same metric as thickness tolerance
Warp range	≤100–200 µm	Panel condition, not final-package warpage

Source: SCHOTT Glass Panels technical details. These are third-party panel examples, not Best Technology manufacturing capabilities or a promise that every listed property is simultaneously available in any requested construction.

A Through-Glass Hole Is Not Yet a Working Via

A TGV needs a defined conductive connection through the glass, not merely a hole with an impressive diameter. Hole formation, profile, metallization and connections to surface wiring must work as one process.

AGC’s TGV product page lists EN-A1 non-alkali glass among its materials, 0.1–1.0 mm sheet thickness examples, and 20–150 µm hole diameters. It also distinguishes straight, tapered and hourglass profiles. These are supplier offering ranges, not evidence that every diameter can be combined with every thickness or that each hole is a qualified copper-filled via.

Ask for the actual layer span, entry and minimum diameter, taper, metallization structure, continuity evidence and connection to the redistribution layers. Do not calculate one aspect ratio from unrelated endpoints in a product-range table.

CTE Matching Helps Only When the Whole Stack Is Considered

Thermal-expansion mismatch depends on the selected glass and its partner materials, geometry and temperature history. “Low CTE” alone does not prove low stress or a reliable joint.

Illustrative calculation: assume two unconstrained materials have constant CTEs of 3.3 and 7.2 ppm/K over a 100 K change. Across 50 mm, their free expansion difference is (7.2 − 3.3) × 10⁻⁶ × 100 × 50 = 0.0195 mm, or 19.5 µm. This is a simplified geometric estimate, not the warpage or stress of a bonded package.

Bonding, copper distribution, polymer layers, stiffness and temperature-dependent behavior change the real response. Use appropriate material data and a validated package model where alignment or joint reliability has little margin.

Metallization and Adhesion Can Become the Governing Interface

Successful glass selection requires a conductor process that adheres and remains electrically continuous through the intended assembly and use conditions. A smooth raw surface does not, by itself, establish copper adhesion.

Define surface preparation, seed and conductor layers, via-wall coverage, patterning and interfaces to build-up materials with the process provider. Request evidence from the proposed stack rather than a bare-glass coupon. SCHOTT’s structured-glass announcement describes the need to adapt the supply chain when moving from conventional packaging structures. It is not proof that an ordinary PCB line can accept a glass core without qualification.

Electrical Performance Requires Grade- and Frequency-Specific Data

Evaluate dielectric properties at the relevant frequency and with a method suitable for the design model. A generic “glass is low loss” claim is not enough to calculate an interconnect channel.

Specify Dk and loss data, conductor dimensions and roughness, return structure and transitions. Include TGV pads and connections in the channel model when their discontinuities matter. Test or simulate the complete interconnect, not just the raw dielectric. Do not claim a data-rate improvement from a lower material-loss number without holding route length, conductor construction and the remaining channel constant.

Mechanical Handling and Edge Quality Need Explicit Controls

Glass-core processing needs a handling and inspection plan that preserves the approved panel condition. Chips, scratches, residual stress and processing damage can matter even when a panel remains intact.

Define support, transport, panel orientation, edge condition and rejection criteria with the processor. Inspect before a later coating or assembly hides the surface. Do not use visible transparency as evidence that an internal conductor is complete or a microscopic crack is absent. The correct inspection method must detect the specified defect at the relevant location and resolution.

Glass substrate panel on supports beneath an optical inspection instrument — AI-generated physical-scene illustration of glass-panel inspection; no crack-detection resolution or measured yield is implied.

Integration With Build-Up Layers and Assembly Must Be Qualified

Qualify glass, vias, surface wiring, polymers and assembly as one construction. A raw material’s temperature property is not an approved reflow profile for the finished stack.

List the intended lamination, cure, soldering and rework exposures. Review dimensional movement, adhesion and joint behavior after the relevant sequence. Keep prototype deviations visible: a sample assembled with different build-up materials or a different metallization route cannot validate every production assumption. Define what must be rechecked when a process or material changes.

Which Tests Distinguish Feasibility From Qualification?

Use evidence that progresses from the raw panel to the completed interconnect and assembled package. One attractive micrograph or a passing continuity test cannot cover every failure mode.

Stage	Question	Evidence to agree
Raw panel	Does the supplied glass meet the controlled geometry?	Material identity, dimensions, variation and surface records
Formed features	Are hole profile and damage within limits?	Defined dimensional and defect inspection
Metallized substrate	Are connections continuous and isolated as intended?	Electrical tests and representative interface analysis
Assembled structure	Does the interconnect survive the required exposures?	Agreed thermal, mechanical and electrical qualification

Specify test conditions, sampling, failure criteria and traceability. Temperature cycling, adhesion or high-frequency measurements answer different questions; select the combination that represents the product rather than using one test name as a reliability label.

Cost and Supply Risk Follow the Complete Process Route

Compare cost per accepted interconnect structure, not raw glass price alone. Patterning, hole formation, metallization, handling, inspection and downstream assembly all contribute to the result.

Separate development tooling and qualification from recurring production costs. Confirm which supplier owns each interface, what data transfer is required and which steps are outsourced. Public announcements do not establish today’s capacity, yield, lead time or availability for your geometry. Obtain a project-specific proposal and identify alternate routes before treating a laboratory sample as a stable supply chain.

Selection and Inquiry Checklist for a Glass-Core Project

Start with the bottleneck that glass is intended to solve, then compare the complete candidate constructions. If an existing organic or ceramic route already meets the requirement, a glass core needs a defensible benefit beyond novelty.

Identify the interconnect level: board, package substrate, interposer or temporary carrier.
Freeze the die, I/O, footprint, routing and thermal requirements.
Select a glass grade and the required dimensional and dielectric data.
Define TGV profiles, metallization and surface-layer interfaces.
Agree assembly exposure and qualification criteria.
Compare accepted-part cost, supplier responsibilities and change control.

For the separate optical-appearance intent, see the existing transparent PCB guide. This article instead addresses permanent glass cores and their interconnect qualification.

FAQ

Does FR-4 already count as a glass-core substrate?

Not in the solid-glass-core meaning used here. FR-4 is a glass-reinforced resin composite, while a glass core is a selected solid glass material integrated into an interconnect stack. Their manufacturing routes and properties differ. Specify the actual cross-section and materials so a request for “glass PCB” is not interpreted as an ordinary fiberglass board.

Will a glass-core package be transparent after manufacturing?

Not necessarily. Copper routing, planes, polymer layers, components and package materials can obscure the glass. Optical transparency of a starting panel is not a guarantee of a clear finished assembly. If appearance or optical transmission is a requirement, specify it separately from electrical routing and review the final stack rather than the raw material alone.

Is a glass core the same as a glass carrier wafer?

No. A permanent core remains in the functional interconnect structure; a carrier supports processing and may later be removed. Surface treatment, release behavior and acceptance requirements follow the role. A glass material suitable for temporary handling is not automatically qualified as the permanent substrate carrying vias and conductor layers in the final product.

Does low expansion mean glass cannot crack?

No. Expansion mismatch is only one contributor to mechanical behavior. Geometry, defects, handling, residual stress and local interfaces also matter. A smaller free-expansion difference does not establish fracture resistance in a bonded assembly. Evaluate the actual construction and required exposures, with inspection methods and acceptance limits defined before the qualification run.

Can a normal PCB supplier make any TGV design?

Do not assume so. Hole formation, glass handling, metallization and packaging integration require a compatible process and evidence for the proposed geometry. Ask for project-specific confirmation and representative qualification records. A supplier’s conventional plated-through-hole capability or a raw-glass sample does not establish production capability for a completed glass-core interconnect.

Does a small TGV automatically provide high-density routing?

No. Surface pads, registration, keepouts, build-up wiring and connection requirements can set the usable pitch. A hole-diameter figure does not define the full routing cell. Review the complete stack and escape geometry, and confirm that the proposed feature combination is qualified rather than combining unrelated minimum numbers from different configurations.

Can glass replace a ceramic substrate for heat removal?

Not from the material name alone. Compare the selected grades, thicknesses, metallization, heat-source geometry and cooling interfaces against the same thermal requirement. Electrical loss, dimensional stability and thermal conduction are different properties. A glass-core packaging advantage does not establish an equivalent heat path to a qualified ceramic power substrate.

Do public glass-substrate announcements prove mass-production readiness?

No. An announcement may describe development, a pilot platform or a particular product configuration. Verify the relevant supplier’s current process, accepted geometry, test evidence and commercial terms for your design. Keep development feasibility, qualified production and committed supply separate; none can be inferred reliably from a headline or a single demonstration sample.

To discuss the appropriate PCB or special-substrate route, send Best Technology your stack concept, interconnect requirements, drawings and qualification expectations at sales@bestpcbs.com. This guide does not claim in-house glass-core or TGV production; the feasible manufacturing and sourcing scope must be confirmed for the project.

Solder Flux Selection: Datasheet and Residue Checks

November 4th, 2026

Solder flux removes surface oxides during heating so molten solder can wet a joint. Choosing it requires more than picking a liquid, gel or “no-clean” label: the chemistry must fit the soldering process, the assembly must tolerate any required cleaning, and the remaining residue must be acceptable for its use environment. Select the material and its processing route together, then validate them on a representative assembly before changing production.

Illustrative solder flux gel, flux pen and PCB on an electronics workbench — AI-generated illustration of electronics soldering materials, not a factory record or product endorsement.

Start Solder Flux Selection With the Job, Not the Container

Identify the soldering operation and the final assembly requirements before choosing a flux form. Wave soldering needs controlled liquid delivery; local rework may need a material that stays near the joint. A liquid flux, tacky flux and flux-bearing solder paste are not interchangeable just because they all assist wetting.

Record the alloy, finish, component restrictions, heating method, cleaning access and downstream coating or testing. For a basic explanation of oxide removal, see what solder flux does. The decision here is whether a specific material/process combination can be released, not whether flux is useful.

Separate Chemistry, Activity, Form and Cleaning Labels

Flux labels describe different properties, so “rosin,” “gel” and “no-clean” are not three mutually exclusive chemistries. Read each dimension separately.

Label dimension	Examples	Decision it supports
Composition family	RO, RE, OR, IN	Rosin, resin, organic or inorganic classification; confirm electronics suitability
Activity classification	L, M or H within a J-STD-004 code	Screen activity, then review actual product/process data
Delivery form	Liquid, tacky gel, flux core	Match dispensing and access to the operation
Residue/cleaning route	No-clean or water-soluble	Decide whether the proposed processing and residue state are acceptable

The final 0 or 1 in a classification concerns halide classification under the referenced standard; it is not a universal statement about every halogen-containing substance or absolute analytical zero. Use the product’s declared test basis. Coilcraft’s flux-selection note explains why composition and activity must be considered with the component and cleaning process.

Detailed Product Parameters: Three Liquid Flux Examples

Compare named products with their stated units and conditions, not generic “low” and “high” scores. These published Kester bulletin values are examples for interpreting datasheets, not approved incoming specifications or a recommendation to substitute one product for another.

Published property	Kester 951	Kester 959T	Kester 2331-ZX
Intended route	Low-solids, no-clean liquid	Low-solids, no-clean liquid	Organic water-soluble liquid
Declared classification	ORL0, J-STD-004	ORL0, J-STD-004B	ORH1, J-STD-004B
Solids	2.0%, theoretical	2.9%, typical	33%, theoretical
Specific gravity at 25°C	0.814	0.794 ± 0.005	0.899 ± 0.005
Acid number	14.3 mg KOH/g flux, typical	21.0 ± 1.0 mg KOH/g flux	Not supplied in the cited parameter summary

Sources: 951 bulletin, 13 May 2021; 959T bulletin, 17 February 2021; 2331-ZX manufacturer bulletin. Specific gravity is dimensionless. Typical and theoretical values are not automatically guaranteed limits. Obtain the current controlled TDS and SDS before procurement or process release.

No-Clean vs Water-Soluble: Choose the Complete Route

Choose a no-clean route when the specific residue and processing conditions are qualified; choose a water-soluble route only when the required washing, rinsing and drying can be completed on the assembly. Neither label alone establishes reliability.

The examples expose two traps. First, 951 and 959T share ORL0 but differ in solids and other properties, so their dispensing settings cannot be assumed identical. Second, 2331-ZX’s neutral-pH description does not make it a no-clean material. Chemistry descriptions, cleaning instructions and application approval answer different questions.

More activity is not automatically better. A material that wets an oxidized test coupon may be unsuitable for a component that traps chemistry or cannot tolerate washing. Compare the whole route, including reject risk and cleaning access, rather than the bottle price alone.

Control Delivered Solids, Not Just Wet Flux Volume

Equal wet delivery does not mean equal flux-solids delivery. For a mass-based estimate, deposited solids = wet flux mass × solids mass fraction. Volume-based dispensing additionally requires an appropriate density conversion and calibration.

In a hypothetical comparison, 0.100 g of a 2.0% solids material contains 2.0 mg of solids, while the same wet mass at 33% contains 33 mg. The 16.5-fold difference explains why copying a dispenser setting can be misleading. This is arithmetic using the two cited concentrations, not a recommended dose or measured board result.

Input solids are not the same as final post-heating residue. Indium’s residue discussion identifies thermal conditions and measurement basis as reasons residue quantities differ. Keep incoming concentration, applied mass and final residue separate in the process record.

Macro illustration of thin amber solder flux residue around soldered connector pins on a green PCB — AI-generated physical-scene illustration of flux residue, not a measured production result. Input solids and post-heating residue are different quantities.

Match the Flux to the Real Thermal and Dispensing Process

Use the selected product’s process guidance and verify it on the actual equipment and assembly. A wave-soldering liquid is not automatically a suitable substitute for a rework gel, and a hot-tool setpoint is not the measured temperature history of every fluxed area.

Check coverage, repeatability, preheat or reflow exposure, and whether material spreads beyond the region receiving the intended heating. Do not compensate for contaminated surfaces or poor heat transfer by flooding the board. Keep alloy and component thermal restrictions in the same review. Kester’s 951 bulletin identifies acid-number measurement as a concentration-control method for that low-solids system; it does not authorize adding arbitrary solvent to any flux.

Check Cleaning Access Before Selecting Aggressive Chemistry

A cleaning requirement is practical only if the process can remove residue from the places it enters. Review low-standoff components, connectors, coils and enclosed structures before choosing a wash-required flux.

Coilcraft warns that chemistry can enter fine-wire components and become trapped; cleaning can also move residue farther into a winding. This is a component/process compatibility issue, not proof that every water-soluble product is unusable. Check the exact component guidance and qualify the full sequence. If a required wash conflicts with a component restriction, change the material, process sequence or component choice before release.

Decide Whether No-Clean Residue Is Acceptable Electrically

Accept retained residue against the assembly’s electrical and environmental requirements, not its appearance alone. Consider sensitive nodes, conductor spacing, humidity exposure and the actual process history when choosing representative verification.

A supplier’s surface-insulation-resistance result applies to its documented test conditions. It is useful material evidence, but not a complete qualification of every board geometry or mixed-chemistry rework sequence. Where leakage or corrosion risk matters, define suitable test structures, exposure conditions and acceptance criteria with the responsible engineering and quality team. Do not claim that a visually clean board or a quick continuity check proves long-term insulation performance.

Include Rework Chemistry in the Qualification Boundary

Qualify the complete sequence of materials a finished board receives, including touch-up flux and flux-core wire. Approving the main production flux does not automatically approve an added pen or gel.

List the main flux or solder paste, wire-core chemistry, separate rework flux, cleaner and any coating. Evaluate the combined residue state and processing sequence. A locally reheated joint may leave nearby applied material outside the intended thermal exposure. If compatibility data are missing, do not assume two products can be mixed because both say “no-clean.” Obtain supplier guidance or run a controlled qualification instead of treating a successful first joint as release evidence.

Verify Coating, Potting and Test-Probe Compatibility

Check downstream operations explicitly because a residue acceptable on an uncoated board may still interfere with another process. Review coating adhesion and coverage, potting compatibility, and electrical test contact behavior.

Coilcraft calls for flux/coating compatibility testing rather than a blanket material-family approval. Indium explains that no-clean residue removal, when required, needs a chemically compatible cleaning agent. A poorly matched wipe can redistribute material rather than establish cleanliness. Use representative assemblies and the actual downstream materials; a clean-looking open coupon does not reproduce every hidden surface.

Troubleshoot the Symptom Before Changing Flux

Identify which process variable failed before increasing activity or temperature. The following are candidate causes and discriminating checks, not diagnoses from appearance alone.

Symptom	Possible contributors	Check before changing chemistry
Solder beads or incomplete wetting	Oxides, contamination, heat transfer, flux delivery	Surface condition, joint temperature history and coverage
Sticky or excessive residue	Over-application, formulation, inadequate processing	Applied amount and actual product/thermal instructions
White film after cleaning	Partial dissolution, redeposition or material interaction	Cleaner compatibility, removal/rinse sequence and remaining contamination
Unstable test contact or leakage	Residue location, probe contamination or electrical/environmental sensitivity	Probe condition and an appropriate contamination/insulation investigation
Coating dewetting or poor adhesion	Surface contamination or material incompatibility	Qualified cleaning and coating compatibility on the actual assembly

Stop unqualified chemical or thermal changes when component compatibility is unknown. Follow the relevant SDS for handling, ventilation, ignition control and disposal; a flux family name is not a safety instruction.

Release a Flux Change With a Reusable Evidence Checklist

Release the change only when material identity, processing conditions and acceptance evidence agree. Use a short change record rather than a verbal statement that the new flux “works better.”

Identify the exact product, lot, TDS revision, SDS and approved application.
Record alloy, finish, relevant components, board revision and application equipment.
Define controlled delivery and the verified thermal sequence, including rework.
Record the cleaning decision, access limitations and downstream coating or testing.
Evaluate wetting, defects, residue and the electrical/environmental checks required by the product.
Approve limits and change authority; retain results and define what future changes trigger requalification.

Flux change decision path connecting material identity, process fit and acceptance evidence — Material, process and evidence must describe the same qualified combination.

FAQ

Does solder flux expire even when it still looks usable?

Use the manufacturer’s shelf life and storage conditions rather than appearance alone. For example, the cited 951 bulletin specifies one year from manufacture when properly handled at 10–25°C. Other products differ. Quarantine material with unknown age or storage history until its disposition is approved.

Does water-soluble mean the liquid contains only water?

No. The term describes a cleaning property of the formulation or residue, not a guarantee about the carrier or flammability. Check the exact TDS and SDS. Do not add water to a flux tank or substitute a storage method based only on that label.

Why can alcohol leave a white film instead of removing residue?

The cleaner may dissolve only part of the residue, move it to a new area or interact with another material. White appearance alone does not identify the cause. Check the flux manufacturer’s cleaner recommendation and verify removal, rather than repeatedly spreading dissolved material with the same wipe.

Is paste flux the same material as solder paste?

No. Paste or tacky flux supplies flux chemistry but not the solder-alloy powder needed to form a joint. Solder paste combines metal powder with a flux system. Confirm the actual product description before selecting it for printing, dispensing, rework or a purchasing substitution.

Can a flux be approved without a manufacturer datasheet?

Not responsibly for a controlled production change. Without traceable identity, processing instructions and residue information, the engineer cannot define a reproducible route. An attractive label or a successful repair is not equivalent evidence. Request the documents or select a traceable candidate before qualification.

Does a neutral pH prove the residue is harmless?

No. pH and acid number are different measurements, and neither alone establishes residue reliability after soldering. The cited 2331-ZX product is described as neutral-pH but remains a water-soluble flux with its own processing requirements. Read the cleaning and test information instead of approving it from one descriptor.

Can one no-clean flux replace another with the same code?

The shared classification is a starting point, not a drop-in compatibility statement. Compare delivery, solids, thermal guidance, residue behavior and downstream materials. The 951 and 959T examples show different physical properties despite ORL0 labels. Validate the proposed substitution under the actual assembly process before approval.

Can plumbing flux be used if the board will be washed?

Do not substitute plumbing flux for an electronics-qualified material merely because cleaning is planned. Its intended metals and chemistry may be unsuitable for the assembly, and washing does not automatically establish compatibility. Choose a documented electronics product and verify its process against the board and component requirements.

Sources and Application Limits

The product values above come from manufacturer bulletins, not Best Technology production measurements. Additional references include Chemtronics’ electronics-flux guide, the linked Coilcraft component guidance and Indium’s flux/residue explanations. Classification references retain the revisions declared by those documents; this article does not claim they are the latest standard editions.

For an assembly project review, send the board revision, BOM, solder alloy, proposed flux TDS, cleaning restrictions and required acceptance evidence to sales@bestpcbs.com. Material substitution and test scope need project-specific approval.

PCB Busbar Joint Resistance: Kelvin Test and Acceptance

November 4th, 2026

PCB busbar joint resistance is meaningful only when the measurement boundary is defined. A four-wire meter can remove most lead-voltage error, but it cannot decide which copper, solder, fastener or parallel path belongs in the result. Before accepting a joint, specify the sense locations, test current, temperature and circuit isolation. Then compare like-for-like results rather than applying a universal micro-ohm limit.

Illustrative unpowered PCB busbar joint mounted above a PCB without test probes — AI-generated illustration, not a production measurement or proof of a test capability.

What Does a PCB Busbar Joint Resistance Test Measure?

The reading includes everything between the voltage-sense points that carries the measured current. It may include bulk conductor, a contact interface, solder and current-spreading regions. It is not automatically the interface resistance alone. A low result also does not prove adequate mechanical retention, insulation or long-term thermal performance.

This guide covers an isolated, unpowered assembly using a controlled DC resistance test. Live equipment and stored-energy systems require a separate approved safety procedure and appropriately rated instruments.

Why Can a Two-Wire Reading Be Misleading?

A two-wire instrument measures voltage across the device plus its test leads and contacts. Those additional resistances can overwhelm a low-resistance joint. Four-wire, or Kelvin, measurement drives current through one pair of connections and senses voltage through another high-impedance pair. Sense current is very small, reducing the effect of voltage drop along the sensing leads.

Four-wire sensing improves the electrical measurement; it does not remove errors from incorrect probe placement, an unstable contact or unintended current routes.

Detailed Test Parameters to Define Before Measurement

Parameter	Record	Why it matters
Measurement boundary	Drawing coordinates or marked sense points	Defines the conductor length and interfaces included
Test current	Magnitude, direction and dwell	Controls signal level and possible self-heating
Temperature	Joint or assembly temperature and stabilization condition	Conductor resistance changes with temperature
Instrument	Range, resolution, uncertainty and calibration status	Display digits alone do not establish accuracy
Offset handling	Current reversal or approved compensation method	Thermoelectric voltage can bias small voltage readings
Circuit state	Isolated paths, connectors and stored-energy checks	Parallel conductors can reduce the apparent resistance

Where Should Current and Sense Probes Be Placed?

Put the current connections outside the intended sensing boundary. Locate the voltage probes on the controlled conductor surfaces on opposite sides of the joint. Use a drawing or fixture to reproduce those positions. Moving a sense probe farther along a copper bar adds conductor resistance; placing both probes on the same side of the interface may exclude the joint entirely.

Probe pressure, surface condition and current distribution near a connection can affect repeatability. Avoid claiming a single placement is correct for every busbar geometry: validate it for the actual assembly.

Four-wire measurement boundary checklist showing current, sense and isolation requirements — Define what the voltage probes include before interpreting the number.

How Can Parallel PCB Copper Hide a Poor Joint?

A PCB plane, second busbar, cable, connected module or another joint can create a bypass around the test boundary. The meter then reports an equivalent network resistance rather than the intended joint. Disconnecting external power does not necessarily remove those paths.

Review the schematic and physical assembly together. Where isolation is impossible, document the network and use an approved model or another verification method. Never label a network reading as a standalone contact resistance without that qualification.

How Do Thermoelectric Offsets Affect Microvolt Signals?

Dissimilar-metal contacts at different temperatures can generate a small voltage independent of the test current. At low resistance, that voltage may be significant compared with the wanted signal. Keithley describes current reversal as one way to separate a stable offset from the resistive component.

For equal positive and negative current magnitudes, R = (V₊ − V₋)/(2I), provided the offset and resistance remain sufficiently stable between readings. Rapid temperature changes, settling errors or self-heating can invalidate that assumption. Use the instrument’s specified procedure rather than reversing an arbitrary power source manually.

How Should Test Current and Dwell Be Selected?

Choose current high enough for a resolvable voltage but compatible with the joint, PCB tracks, connectors and instrument compliance. Excess current or long dwell can heat the assembly and change the resistance being measured. A room-temperature resistance check is not the same as an operating-current temperature-rise test.

For illustration only, 10 A through 100 µΩ produces 1 mV and 0.01 W. These numbers explain signal scale; they are not recommended test settings or an acceptance threshold. Validate settings against the actual assembly and uncertainty target.

Kelvin DC Test vs Two-Wire Meter vs Thermal Test

Method	Useful for	Limitation
Two-wire resistance	Continuity and higher-resistance checks	Lead/contact voltage drop can dominate a low-resistance joint
Four-wire DC resistance	Controlled low-resistance comparison	Requires defined boundaries, isolation and offset control
Operating-current thermal test	Temperature rise under defined cooling and loading	Depends on environment; does not isolate contact resistance by itself
AC impedance tester	Frequency-specific impedance measurements	Not interchangeable with DC joint resistance without validation

What Acceptance Limit Is Defensible?

Derive limits from the electrical loss budget, allowable temperature rise, mechanical design and validation evidence. The simple relation P = I²R connects resistance to local loss, but it does not predict temperature without a thermal model or test. Consider current distribution and surrounding heat paths.

Record a qualified reference population under the same method, evaluate measurement uncertainty and define decision rules for readings near the limit. A limit from a power-distribution busway manual belongs to that manufacturer’s construction and procedure; it must not be copied directly onto a PCB-mounted joint.

Common Failure Patterns and Their Root Causes

Observation	Check first	Do not assume
Unexpectedly low resistance	Parallel paths; both sense points on one side	That the joint is exceptionally good
Reading changes when probes move	Included conductor length and surface contact	That all variation comes from the joint
Drift during repeated readings	Thermal stabilization, offset and self-heating	That instrument resolution proves stability
High but repeatable result	Boundary, interface condition and assembly process	That tightening alone is an approved repair

For bolted designs, use the drawing’s approved hardware and assembly process. For soldered or welded designs, investigate the applicable process evidence. Do not prescribe a universal torque, reflow profile or rework method across different constructions.

What Should the Repeatability Checklist Include?

Confirm de-energization and discharge; identify current and sense points; check bypass isolation; verify instrument range and calibration; stabilize temperature; apply the validated current and settling time; repeat the measurement with controlled probe placement; record both the result and abnormal behavior. If reversal is used, retain enough information to detect an unstable offset.

Measurement record workflow from boundary definition through repeatability and acceptance — A traceable result needs a controlled setup as well as a resistance value.

What Should an Engineering or Supplier Review Receive?

Provide the busbar/PCB drawing, joint construction, intended current duty, thermal constraints, measurement boundary and acceptance method. Include the complete fixture and instrument conditions when comparing suppliers or production lots. A naked micro-ohm number is not a transferable specification.

For a special PCB manufacturing review, send the controlled design and test requirements to sales@bestpcbs.com. Test availability and production limits require project-specific confirmation.

FAQ

Can a normal multimeter measure a busbar joint accurately?

It may check continuity, but a two-wire reading can include more lead and probe resistance than the joint itself. Confirm range and uncertainty. For low-resistance acceptance, use a validated four-wire method with defined sense points and circuit isolation. Record the instrument model and selected range.

Are Kelvin clips sufficient to guarantee a correct result?

No. They provide separate current and voltage contacts, but placement, surface condition and circuit topology still matter. Confirm which contact is the voltage sense and which conductor sections lie between the two sense locations. Keep placement photographs or fixture references with the measurement record.

Can a battery tester replace a DC micro-ohmmeter?

Not automatically. Some testers measure AC impedance at a specified frequency rather than DC resistance. Different excitation and processing can produce different values. Use the instrument type required by the approved procedure or demonstrate equivalence for that assembly. Check the specified excitation frequency before comparing readings.

Why does the result drift after connecting the probes?

Possible causes include thermal EMF, unsettled contacts, changing temperature and test-current heating. Check the instrument’s settling requirements and repeat at controlled conditions. Drift is not enough by itself to identify a defective joint. Compare stabilized readings using the same current and sensing boundary.

Must PCB parallel paths be disconnected?

They must be removed, shown to be irrelevant or included explicitly in a validated measurement model. Otherwise, the result may describe a parallel network instead of the joint. An unpowered PCB can still contain conductive bypass paths. Document the isolation configuration with the measured value.

Is there a universal acceptable micro-ohm value?

No single number applies to every material, geometry and current duty. Establish a limit from the qualified design and thermal/electrical requirements, then account for the measurement method and uncertainty. Keep the probe boundary identical when comparing results. Avoid transferring limits between different joint constructions.

Can the busbar itself be used as a current shunt?

Only with suitable characterization and an approved design. Sense spacing, temperature coefficient, current distribution and calibration affect accuracy. A busbar selected for low loss is not automatically a precision shunt, even if its voltage drop can be measured. Separate current-monitoring accuracy requirements from joint-acceptance requirements.

Does passing resistance testing prove the joint is reliable?

No. It verifies one characteristic under one condition. Mechanical retention, insulation, thermal cycling, corrosion and operating temperature may need separate qualification. The required tests depend on the actual product and application, not the resistance reading alone. Keep qualification evidence separate from routine production measurements.

References

Technical guidance is for engineering planning. Use qualified personnel, approved procedures and the actual instrument manual for testing.

Microstrip PCB: Structure, Impedance and Design Checks

November 2nd, 2026

A microstrip is a planar transmission line with a conductor on an outer PCB surface and a reference plane separated by dielectric material. Keysight defines it as a thin conductive trace printed or etched on the top of an insulating substrate with a parallel ground plane on the other side. Because some electromagnetic field exists in air and some in the substrate, impedance and effective permittivity depend on both geometry and material.

Microstrip transmission line on an RF printed circuit board — A microstrip trace is referenced to a plane through the dielectric below it.

How Does a Microstrip PCB Trace Work?

The signal and its return current form a transmission structure. At high edge rates or RF frequencies, the trace cannot be treated as an ideal wire. Its width, copper thickness, distance to the reference plane, dielectric properties and surrounding structures determine characteristic impedance, delay, loss and radiation.

Detailed Microstrip Design Parameters

Parameter	Model input	Practical effect
Trace width	Finished top/bottom width or etch profile	Changes impedance and conductor loss
Copper thickness	Finished copper including plating where applicable	Changes cross-section and impedance
Dielectric height	Pressed distance to the reference plane	Strongly affects field spread and impedance
Material Dk/loss	Grade-specific design model at frequency	Controls delay, geometry and dielectric loss
Copper roughness	Model appropriate to foil/treatment	Can increase high-frequency attenuation
Solder mask	Thickness and dielectric behavior	Changes effective impedance for covered lines
Reference plane	Continuous geometry and openings	Controls return path and discontinuities

Microstrip vs Stripline vs Coplanar Waveguide

Structure	Field location	Strength	Trade-off
Microstrip	Outer layer, air and substrate	Easy probing and components	More exposed to radiation and environment
Stripline	Internal trace between planes	Better field containment	More vias and less direct access
Grounded coplanar waveguide	Outer trace with adjacent ground and lower plane	Useful field control and grounding	Gap, via fence and launch geometry become critical

How Is Microstrip Impedance Calculated?

Use a field solver with the proposed production stackup rather than a single generic formula for sign-off. Closed-form equations are useful for early estimates, but real boards include copper thickness, trapezoidal etch, solder mask, roughness and anisotropic materials. For differential microstrip, pair spacing and symmetry also matter.

Stage	Input quality	Output use
Early estimate	Nominal Dk and geometry	Choose layer and approximate width
Fabricator calculation	Actual laminate, pressed thickness and finished copper	Set production artwork and coupon
EM extraction	Launches, bends, vias and local structures	Analyze discontinuities and RF behavior
Coupon measurement	Controlled test structure	Verify the manufactured process

Reference-Plane and Return-Path Rules

Keep a continuous reference plane beneath critical microstrip routes. Plane gaps, slots and poorly placed transitions force return current to detour, increasing loop area and potentially creating reflection, crosstalk and EMI. When a signal changes layers or reference planes, provide an appropriate nearby return connection based on the interface and stackup.

Nearby copper features also change the field. Ground pours, component pads, shields and board edges can alter local impedance when they sit inside the line’s field region. Define keep-outs or model the real copper instead of assuming an isolated textbook microstrip. The same review applies to differential pairs whose spacing changes near pads and connectors.

RF Launches, Bends and Via Transitions

A nominally correct straight line can still fail at connectors, pads, neck-downs, bends and vias. Model the launch as part of the channel. Miters or curved bends may reduce excess capacitance in some geometries, but the correct shape comes from the actual frequency and stackup. Ground-via placement and anti-pad geometry should be evaluated together with the signal transition.

Production Checklist

Microstrip PCB engineering release checklist — Release the line only after stackup, geometry and acceptance evidence agree.

Freeze material grade, dielectric thickness and copper construction.
Use finished trace geometry and agreed etch tolerance.
Document impedance target, tolerance, net class and test method.
Keep the reference plane continuous below the line.
Review solder-mask coverage and connector launches.
Specify coupon design, location and report requirements.
Recalculate after any material or stackup substitution.

Common Microstrip Failures

Using a generic Dk rather than the laminate’s design value.
Ignoring solder mask on a tightly controlled line.
Routing across a reference-plane opening.
Optimizing the trace while leaving the connector launch unmodeled.
Measuring a coupon that does not represent the routed layer or geometry.

FAQ

Is every outer-layer trace a microstrip?

Only when it behaves as a transmission line referenced to an appropriate plane. Low-speed traces may not need transmission-line treatment, but the physical structure can still be microstrip-like.

Is microstrip always 50 ohms?

No. Fifty ohms is common in RF systems, but the target comes from the interface and system design.

Does a wider trace increase or decrease impedance?

With other inputs fixed, a wider microstrip generally lowers characteristic impedance. Recalculate the complete geometry rather than changing width alone.

When is stripline better?

Stripline is useful when field containment and reduced exposure are priorities and internal-layer routing is acceptable.

Sources

For a microstrip PCB stackup and manufacturability review, send fabrication data, material, frequency and impedance requirements to sales@bestpcbs.com. EBest Circuit can review manufacturing inputs; final RF performance remains subject to the customer’s design and validation.

PCB Crosstalk Simulation: Inputs, Metrics and Validation

November 2nd, 2026

PCB crosstalk simulation estimates unwanted coupling from an aggressor interconnect into a victim interconnect. Useful results require more than drawing two parallel traces: the model must represent the production stackup, conductor geometry, coupled length, return path, vias, source behavior, receiver loading and the frequency or edge-rate range of interest. The simulation should answer a defined design question, such as whether induced noise violates a receiver threshold or reduces an eye-diagram margin.

High-speed PCB crosstalk simulation with coupled traces and waveforms — Crosstalk depends on the physical channel and the electrical behavior of the connected I/O.

What Is PCB Crosstalk?

Crosstalk is unintended electromagnetic coupling between nearby conductors. Changing voltage and current on the aggressor create electric and magnetic fields that induce a signal on the victim. Siemens identifies coupled length, spacing, stackup position, driver behavior and termination among the factors that control the result. Ansys similarly explains that dense routing can place traces close enough for unwanted coupling and recommends board-level analysis when routing rules alone do not establish adequate margin.

Near-end crosstalk (NEXT) is observed at the victim end near the aggressor source. Far-end crosstalk (FEXT) is observed at the opposite end. Their polarity and magnitude depend on the geometry, propagation behavior, termination and observation definition. Always label the ports and probing points in the report.

Detailed Simulation Parameters

Input	What the model needs	Risk if simplified incorrectly
Stackup	Layer order, dielectric thickness, Dk/loss model and reference planes	Incorrect impedance, delay and field distribution
Copper geometry	Finished width, thickness, spacing and etch profile	Coupling and impedance do not represent production
Coupled length	Actual parallel run and changing separation	A short local coupling region becomes overstated or missed
Vias and transitions	Barrels, pads, anti-pads, stubs and return vias	Via-to-via and cavity coupling are omitted
I/O models	IBIS/SPICE/AMI or defined source and load behavior	Noise amplitude and timing use unrealistic edge strength
Termination	Source, parallel, differential or device termination	Reflections alter the observed crosstalk waveform
Analysis range	Time step, rise/fall time or frequency sweep	Relevant spectral content is not captured
Acceptance metric	Voltage, S-parameter, eye, jitter or receiver threshold	Plots are produced without a pass/fail decision

Pre-Layout vs Post-Layout Crosstalk Simulation

Approach	Best use	Model detail	Limitation
Pre-layout what-if model	Set spacing, layer and topology constraints	Representative stackup and parameter sweeps	Cannot include every final route and discontinuity
Post-layout extraction	Check actual aggressor/victim geometry	Routed traces, layers, vias and nearby structures	Quality depends on imported material and I/O data
3D EM extraction	Dense vias, connectors, launches or nonuniform structures	Full electromagnetic geometry in a bounded region	Higher setup and computation cost
Bench measurement	Correlate prototypes and production channels	Physical coupons or completed boards	Measurement fixtures and calibration affect the result

Altium’s documentation notes that its crosstalk analysis is post-layout because routed nets are required. Pre-layout simulation still has value for developing constraints, but final sign-off should incorporate the released geometry and applicable models.

Which Crosstalk Metrics Should Be Checked?

No single metric fits every interface. Time-domain NEXT and FEXT show induced voltage relative to switching events. Frequency-domain S-parameters quantify coupling versus frequency; mixed-mode terms are useful for differential pairs and mode conversion. Eye diagrams can show the combined effect of coupling, loss, reflections and timing, while jitter or receiver-mask measurements connect the channel result to protocol margin.

Metric	Answers	Important condition
Peak NEXT/FEXT voltage	How large is the induced transient?	State driver pattern, edge rate, load and probe point
Coupling S-parameter	How does coupling change with frequency?	State port mapping, reference impedance and mode
Eye height/width	Does the combined channel preserve receiver margin?	Use correct data rate, pattern and receiver assumptions
Timing or jitter	Does aggressor activity move victim crossings?	Separate deterministic coupling from other jitter sources

Crosstalk Simulation Workflow

PCB crosstalk simulation input and metrics workflow — Geometry, models and acceptance criteria must be controlled together.

Define the victim and aggressors. Include clocks, data, strobes, power-related switching and I/O routes that share a meaningful coupling region.
Set the acceptance criterion. Use the interface’s receiver or system requirement rather than a universal spacing slogan.
Import the production stackup. Confirm finished copper, dielectric thickness and relevant material models with the fabricator.
Extract the actual geometry. Preserve spacing changes, reference-plane discontinuities, transitions and return vias.
Assign electrical models. Use appropriate driver, receiver and termination behavior.
Run useful cases. Sweep plausible process and geometry variation, not only a single nominal case.
Identify the dominant mechanism. Separate trace-to-trace, via-to-via, cavity and common-mode contributions where possible.
Change one design variable at a time. Compare spacing, layer, coupled length, reference placement, termination or via structure.
Correlate high-risk channels. Use coupons, TDR, VNA or oscilloscope measurements with documented fixtures and calibration.

How Geometry Changes Crosstalk

Increasing separation generally reduces coupling, while longer parallel runs generally increase it. Moving a trace closer to a solid reference plane can contain more of its field, but the final effect depends on the complete geometry. Routing critical signals across plane gaps or close to I/O nets can create additional return-path and EMI problems. Differential symmetry also matters because imbalance can convert differential energy into common-mode noise.

A fixed “three-width rule” or similar spacing heuristic can be a conservative starting constraint, but it is not a universal pass condition. The acceptable spacing for a slow control line and a fast low-voltage memory interface may differ even on the same board. Simulation should use the actual edge spectrum and receiver margin.

Simulation vs Measurement: What Each Can Prove

Simulation isolates design variables and enables early sweeps before hardware exists. Measurement checks the physical realization, including fabrication variation and effects omitted from the model. Neither automatically validates the other. Correlation requires matching geometry, port locations, stackup, fixtures, terminations, stimulus and bandwidth. Siemens’ via-to-via crosstalk work demonstrates the value of comparing simulation with S-parameter and time-domain measurements on controlled test boards.

When results disagree, first audit input data and reference planes, then fixture removal, calibration, model bandwidth and material values. Do not tune an arbitrary parameter solely to force agreement without a physical explanation.

Common Modeling Mistakes

Using nominal line width instead of the finished production geometry.
Ignoring plane splits, voids, connector launches or via fields.
Simulating frequency alone while the real risk is a fast edge with broad spectral content.
Using ideal voltage sources when device output impedance and edge rate determine aggressor strength.
Reporting NEXT or FEXT without port definitions and observation locations.
Judging a color plot without a numerical acceptance criterion.
Assuming a nominal pass covers dielectric, etch and registration variation.

FAQ

Do all PCB nets need crosstalk simulation?

No. Prioritize fast edges, low-noise analog victims, clocks, strobes, dense buses and routes with long close coupling or difficult transitions.

Is trace spacing enough to control crosstalk?

Spacing is important, but coupled length, reference structure, layer, edge rate, termination and vias also matter. Use spacing rules as constraints and simulation for risk-specific confirmation.

Should simulation use clock frequency or rise time?

Both context and edge behavior matter. A low repetition-rate signal can still contain high-frequency energy when its transitions are fast.

What fabrication data should be confirmed?

Confirm material model, pressed dielectric thickness, finished copper, trace/space tolerance, etch profile, via geometry and the final stackup used for impedance control.

Sources

For PCB manufacturability and stackup review, send the released fabrication data, target stackup, controlled-impedance requirements, quantities and acceptance needs to sales@bestpcbs.com. EBest Circuit can review manufacturing inputs; system-level signal-integrity acceptance remains the customer’s design responsibility.

EMI Shielding Film for FPC: Stack-Up, Grounding and Design Checks

November 2nd, 2026

EMI shielding film is a thin multilayer material laminated onto a flexible printed circuit to reduce electromagnetic coupling while preserving a low-profile, bendable construction. It is not simply decorative metal foil. Its protective layer, shielding layer and conductive adhesive must form a controlled electrical and mechanical interface with the FPC.

Selection should start with the required frequency range, shielding target, total thickness, grounding method, bend condition and lamination process. A film that performs well on a flat test coupon can still fail after poor grounding, creasing, over-pressing or repeated dynamic bending.

Flexible printed circuit laminated with a thin dark EMI shielding film on a laboratory inspection bench — EMI shielding film adds a thin conductive layer to an FPC, but its ground interface and press process determine whether the shield works in the finished assembly.

What Is EMI Shielding Film?

Shielding film for FPC commonly combines a protective surface, a conductive shielding layer and a conductive or anisotropic conductive adhesive. TATSUTA describes product families with thermosetting adhesive for FPC processing, pressure-sensitive versions for selected devices and supplementary grounding films. The exact construction varies by series, so design values must come from the selected supplier data sheet.

Layer or feature	Primary job	Design risk
Protective layer	Handling and surface protection	Cracking, abrasion or excess stiffness
Shielding layer	Conductive path for field attenuation	Discontinuity, crease damage or inadequate frequency performance
Conductive adhesive	Bonding and electrical connection to ground features	High contact resistance or incomplete penetration
Release/transfer film	Processing support before lamination	Wrong removal sequence or contamination

Detailed Film Parameters and Practical Meaning

As one product-specific example, TATSUTA’s SF-PC3900R1-C and R2-C sheet reports total pressed thicknesses of 12 µm and 13 µm, with shielding-layer thicknesses of 1 µm and 2 µm respectively. These are not universal values and must not be copied to another series.

Parameter	What to verify	Why it matters
Total thickness after press	Finished laminate, adhesive flow and tolerance	Changes connector fit, bend stiffness and enclosure clearance
Shield effectiveness	Frequency, fixture, grounding and test method	A dB value without test conditions is not transferable
Contact resistance	Ground-pad geometry, pressure and aging	High impedance weakens the RF return path
Peel strength	Initial and aged adhesion to the actual coverlay	Delamination creates mechanical and electrical discontinuities
Press conditions	Temperature, pressure, time and release sequence	Controls adhesive flow, bonding and dimensional stability
Flex performance	Static bend or dynamic cycles, radius and direction	Film selection for a folding hinge differs from a fixed cable

Layer diagram showing protective, shielding, adhesive, coverlay, copper and polyimide layers — Use the selected supplier’s real layer construction; thickness, adhesive and ground behavior differ between film families.

Shielding Film vs Copper Foil, Conductive Tape and Shield Cans

Option	Best fit	Main trade-off
FPC EMI shielding film	Thin flexible circuits and folded assemblies	Requires controlled lamination and grounding
Copper foil with conductive adhesive	Local grounding, repair or simple shielding geometry	Can add stiffness and edge stress
Conductive fabric or tape	Conformable enclosure and gap treatments	Assembly consistency and long-term adhesion
Board-level shield can	Rigid PCB component regions	Height, soldering, seams and rework

Grounding Design Rules

Define where the film connects to the FPC ground rather than assuming full-area contact.
Use the supplier’s recommended exposed-ground geometry and press construction.
Keep the return path short and distributed where high-frequency performance requires it.
Do not bridge a true isolation barrier with shielding film or grounding features.
Check connector shells, chassis contacts and cable exits as part of the complete shield path.
Measure contact resistance after lamination and after environmental or flex testing.

Lamination and Assembly Process

Verify material identity, storage condition and shelf-life requirements.
Clean and inspect the FPC coverlay and exposed grounding regions.
Align the film without wrinkles, trapped contamination or unintended overlap.
Apply the supplier-specified temperature, pressure and time.
Remove transfer film in the correct sequence and inspect edges and apertures.
Measure dimensions, adhesion and ground continuity before final assembly.

Pressing parameters are a material-system requirement, not a universal FPC recipe. Excessive pressure can distort fine features or force adhesive into unintended areas; inadequate pressure can leave weak bonding and unstable contact.

Bend and Mechanical Design Checks

Keep abrupt film edges, grounding transitions and thickness steps away from the highest-strain bend zone. Evaluate the full laminated stack, not the base polyimide alone. Static installation bends and repeated dynamic flex require different evidence. Define bend radius, flex direction, cycle count, temperature and fixture geometry, then inspect resistance and shielding performance after testing.

Common Failures and Root Causes

Failure	Possible cause	Verification
Weak shielding	Poor ground contact, wrong film or uncontrolled aperture	Frequency-specific test and ground-resistance check
Delamination	Contamination, wrong press cycle or incompatible coverlay	Peel and environmental testing
Cracking at bends	Film too stiff, radius too small or edge in strain zone	Section inspection and flex cycling
Connector fit problem	Finished thickness not included in tolerance stack	Measure pressed stack and mating geometry
Intermittent noise	Ground contact changes during movement	Monitor resistance and RF behavior while flexing

Validation Checklist

Confirm film series, lot and storage history.
Document final thickness and dimensional change after pressing.
Measure grounding continuity and contact resistance.
Inspect film edges, apertures, wrinkles and adhesion.
Run bend testing that represents the final product motion.
Test emissions or susceptibility with the final cables, enclosure and operating modes.
Record the exact fixture, frequency range and acceptance limit.

FAQ

Can EMI shielding film be used on a rigid PCB?

Conductive films and tapes can be used in rigid assemblies, but FPC shielding film is optimized around flexible-circuit construction and lamination. Confirm compatibility with the actual surface and process.

Does thicker shielding film always work better?

No. Shielding depends on material, frequency, grounding, apertures and test conditions. Extra thickness can reduce flexibility and create mechanical problems.

Where should shielding film connect to ground?

Use defined exposed grounding features and the film supplier’s recommended construction. The connection must remain low impedance after pressing, bending and environmental exposure.

Can shielding film cross a dynamic bend?

Only when the selected film and complete FPC stack are qualified for the required bend radius, direction and cycle count. A static-fold product is not proof of dynamic-flex life.

Sources

For a flexible PCB stack-up, shielding-film opening and assembly review, send the controlled drawing, selected material series, bend requirements and validation targets to sales@bestpcbs.com.

MOSFET Pinout Guide to Identifying Gate, Drain and Source

October 6th, 2026

MOSFET pinout identifies which physical connections belong to the gate, drain and source. These terminal names stay familiar across many devices, but their pin numbers and positions can change with the part number and package. Reading the correct view matters: a connection that appears on the left in a front view may appear on the right when the component is turned over.

For boards using MOSFETs, correct pin mapping supports both reliable connections and accurate component placement. EBest Circuit provides PCB fabrication, SMT and through-hole assembly, and DFM support for customer designs. To discuss manufacturing and assembly for your MOSFET-based board, contact sales@bestpcbs.com.

What Do the Three MOSFET Pins Do?

The gate controls the conducting channel between the drain and source. In a typical discrete MOSFET, these three terminal functions are labeled G, D and S, even when the package has more than three physical connections.

Terminal	Function	What it means in a circuit
Gate (G)	Controls channel conduction through the gate-to-source voltage, VGS	The drive voltage is referenced to the source, which is not necessarily ground.
Drain (D)	One end of the controlled current path	Its connection must match the intended circuit and body-diode orientation.
Source (S)	The other end of the controlled current path and the reference for VGS	Source voltage determines the gate voltage needed to control the channel.

For an enhancement-mode N-channel MOSFET, a sufficiently positive gate-to-source voltage turns the channel on. For an enhancement-mode P-channel device, the required polarity is negative. The threshold voltage marks the start of conduction under specified test conditions; it is not the voltage that guarantees low on-resistance.

The insulated gate behaves capacitively. It needs charging and discharging during switching, even though steady-state gate current is very small. This also explains why a floating gate can produce confusing multimeter readings.

Terminal names and pin numbers describe different things. “Gate” describes an electrical function; “pin 1” identifies a physical connection in a particular package drawing. Pin 1 is not universally the gate.

How to Read a MOSFET Pinout Diagram

A MOSFET pinout diagram becomes useful only when its viewing direction matches the way you are looking at the component. Begin with the full part number and package variant, then read the view label and pin numbering together.

Front view: Often used for upright through-hole packages. Follow the drawing’s indicated face and lead direction before interpreting left-to-right order.
Top view: Looks down onto the component body. Pin 1 may be identified by a dot, chamfer or another feature defined in the package drawing.
Bottom view: Looks toward the underside or solder connections. Copying this arrangement directly into a top-view sketch can reverse the apparent positions.

Match numbered connections to the pin-function table rather than inferring their functions from the outline alone. A schematic symbol shows electrical relationships; its visual arrangement does not establish the physical pin order.

For example, the IRLZ44N in its TO-220 package has pin assignments 1 = Gate, 2 = Drain and 3 = Source. That numbered assignment remains the same when you rotate the device, but the apparent left-to-right order changes. Remembering “G-D-S” without remembering the viewing direction loses essential information.

The pin diagram and recommended PCB land pattern also serve different purposes. The first identifies connections; the second describes the copper pads used to mount the package. Both are needed when translating the component into a PCB footprint.

MOSFET Pin Configuration in Common Packages

Package size and shape do not define one universal MOSFET pin configuration. The following examples show why the exact device matters.

Device and manufacturer	Package	Connection assignment
IRLZ44N, Infineon	TO-220	Pin 1 = G; pin 2 = D; pin 3 = S; metal tab = D
2N7002, Nexperia	SOT23	Pin 1 = G; pin 2 = S; pin 3 = D
CSD17302Q5A, Texas Instruments	SON, 5 mm × 6 mm	Pins 1–3 = S; pin 4 = G; pins 5–8 = D; exposed pad = D

The two three-lead examples already show a key difference: pin 2 is the drain on the IRLZ44N, but the source on the 2N7002. Applying a familiar three-pin sequence to a different device can therefore swap its power connections.

A small SOT23 device also cannot be read as a straight row of three pins: two leads sit on one side and the third sits opposite them. Its outline and numbering must be interpreted together.

In a leadless power package, some connections lie underneath the body. A top photograph alone cannot show the complete solder interface. The exposed pad may carry an electrical connection as well as conduct heat, so treating it as an electrically neutral heatsink area can create a PCB error.

These examples are specific device assignments, not rules for every TO-220, SOT23 or SON MOSFET. Likewise, an eight-pin package can contain one transistor or multiple transistors, depending on the part number.

Why Do Some MOSFETs Have More Than Three Pins?

More physical pins do not necessarily mean more independently controlled terminals. Power MOSFET packages often provide several connections to the same source or drain, creating parallel paths between the die and the PCB. Larger metal connections also help conduct heat away from the device.

An exposed pad is another physical connection that may share a source or drain net. Its electrical identity comes from the device’s pin information, not from its size or central position.

Some four-pin power MOSFETs have a Kelvin source connection. This provides a separate source reference for the gate driver, while the main source lead carries load current. Separating these paths reduces the influence of voltage developed across the shared source inductance during rapid current changes. Although both connections reach the source internally, their PCB routing serves different purposes.

The body, or bulk, terminal is a separate concept. MOSFET device theory describes gate, drain, source and body; many discrete devices connect body to source internally. A four-pin Kelvin-source package should therefore not be assumed to expose an independent body terminal.

How to Identify MOSFET Pins with a Multimeter

A multimeter can help distinguish terminals on a suitable discrete MOSFET, but it cannot reliably identify every unknown package. The method below applies to a conventional, isolated, enhancement-mode silicon MOSFET with an intrinsic body diode. Integrated protection, multiple transistors and unusual internal connections can change the readings.

Prepare the device. Disconnect power, discharge stored energy and isolate the component from other circuit paths. Use ESD precautions and a meter whose test voltage is suitable for the device. Confirm the meter’s probe polarity in diode mode.

Locate the likely gate. On a device without internal gate-protection paths, the gate should show very high resistance to both remaining terminals in either polarity, after charging effects settle. This is an identification clue, not proof: protection structures and damage can produce different results.

Identify the drain-source diode direction. Once a likely gate is identified, keep it connected to the candidate source so that VGS remains zero during each diode test. For a known channel type, the expected forward direction is:

Channel type	Positive probe	Negative probe	Expected indication with channel off
N-channel	Source	Drain	Forward body-diode reading
P-channel	Drain	Source	Forward body-diode reading

With the probes reversed, the device should normally block at the meter’s test voltage. The forward reading varies with the device, temperature and meter test current; one fixed voltage is not a universal pass criterion.

If the channel type is unknown, diode direction alone cannot uniquely establish both the channel type and the source/drain labels. Part markings and the corresponding datasheet remain important.

Account for gate charge and surrounding circuitry. A meter can charge the gate and turn the channel on, causing conduction that obscures the body-diode result. Gate-to-source discharge removes that stored charge on an isolated enhancement-mode device. On an assembled board, resistors, drivers and parallel semiconductors may create additional current paths.

These measurements support identification and basic troubleshooting. They do not establish rated-voltage performance, switching behavior or on-resistance under operating load.

How MOSFET Pin Numbers Map to PCB Footprint Pads

A PCB connects a MOSFET correctly when the schematic pin numbers correspond to the physical terminal numbers represented by the footprint pads. Matching the package dimensions alone is insufficient.

For the Nexperia 2N7002 example, the mapping is:

Schematic terminal	Device pin	Corresponding footprint pad
Gate	1	1
Source	2	2
Drain	3	3

If a symbol instead assigns drain to pin 2 and source to pin 3, the device may still fit the footprint perfectly. The board can even pass connectivity checks against that incorrect library mapping, yet connect the transistor incorrectly. This is why a footprint’s name or 3D appearance cannot establish electrical compatibility.

For packages with repeated source or drain terminals, every required connection must reach the intended net. The exposed pad must also have the correct electrical assignment. CAD libraries may represent shared connections differently, but the resulting physical connections must agree with the device.

Orientation is equally important during assembly. The footprint’s pin-1 reference, component placement rotation and actual package marking need to describe the same orientation. An otherwise correct pad mapping will not compensate for a rotated component.

FAQs About MOSFET Pinout

Can the drain and source be swapped?

Not as a general replacement rule. An enhanced channel can conduct in either direction under suitable conditions, but the body diode and gate-to-source reference make drain and source behave differently in a circuit. Reverse channel conduction does not make the pins interchangeable.

Do N-channel and P-channel MOSFETs always have different pin orders?

No. Channel type describes electrical behavior, not a mandatory package pin order. Two devices may share the same arrangement while requiring opposite gate-drive polarity.

Is a MOSFET source always connected to ground?

No. That is common in an N-channel low-side switch, but the source can sit at another voltage in other circuit arrangements. Gate drive is determined relative to the source.

Can a short SMD marking uniquely identify a MOSFET?

Not always. Short codes can be reused across manufacturers or device families. Package dimensions, manufacturer identification and the complete marking help distinguish possible matches.

Does a matching pinout make two MOSFETs interchangeable?

No. Voltage rating, gate-drive requirements, on-resistance, switching characteristics, thermal behavior and package dimensions must also suit the circuit. Matching pins establish only part of the compatibility.

For PCB fabrication and assembly of your MOSFET-based design, contact EBest Circuit at sales@bestpcbs.com to discuss the board, package and MOSFET pinout requirements.

Selective Soldering Process: How Each Stage Controls Joint Quality

October 6th, 2026

The selective soldering process creates through-hole solder joints only at programmed locations on a PCB assembly. It is commonly used after SMT reflow when connectors, relays, transformers, terminals, switches, or other plated through-hole components still need to be soldered without exposing the entire underside of the board to a full solder wave.

Its advantage is control, but localized soldering does not automatically guarantee good joints. Flux placement, preheat, nozzle condition, solder contact, travel direction, withdrawal, PCB thermal mass, and inspection must work as one connected process. A setting that produces complete barrel fill on a plane-connected power pin may overheat a nearby low-mass joint. A nozzle path that works on an open connector row may bridge pins when an adjacent component changes the solder flow.

This guide explains how each stage works, which variables change the result, and how a stable selective soldering process turns mixed SMT and through-hole assemblies into repeatable production builds.

What Is the Selective Soldering Process?

Selective soldering is an automated through-hole assembly process that delivers flux, heat, and molten solder to chosen joints instead of treating the entire PCB underside. A programmed system moves either the PCB or a small solder nozzle so that the solder fountain reaches the required pins while avoiding nearby areas.

The method is especially useful after one or both PCB sides have already passed through SMT reflow. Bottom-side resistors, capacitors, ICs, or other packages may sit close to the remaining through-hole pins. Full wave soldering could require a protective pallet or expose too much of the assembly to heat, while extensive hand soldering may add operator variation. Selective soldering in PCB assembly gives the assembler a repeatable route to the remaining joints when the layout provides sufficient access.

The process is not simply a smaller version of wave soldering. Each target receives its own controlled flux pattern and thermal history. The machine program must account for connector geometry, pin spacing, component mass, copper distribution, board thickness, solder alloy, surface finish, and the location of nearby components.

Selective Soldering Process Steps from Fluxing to Inspection

A production cycle normally follows five connected stages:

Flux application: Flux is deposited only where the selected through-hole joints need it.
Preheating: The PCB and component leads are brought to a suitable temperature so that the flux activates and the joint can accept solder.
Localized soldering: A nozzle creates a stable mini-wave and follows the programmed path beneath the required pins.
Cooling: The solder solidifies while the component and PCB remain stable.
Inspection: The finished joints are checked for wetting, barrel fill, bridging, solder balls, damage, and other agreed acceptance criteria.

These stages cannot be tuned independently. Too much flux may spread beyond the intended area or leave active residue when preheat is insufficient. Weak preheat may force a longer solder-contact time, which can increase copper dissolution and thermal exposure. An unstable solder fountain can make a correct travel path produce inconsistent results.

For this reason, the first article should use the actual PCB, components, alloy, flux, nozzle, and production program. Once the joint results are approved, the program and material combination should remain under revision control.

How Flux Application and Preheating Prepare the PCB

Flux prepares the metal surfaces for wetting. It removes light oxides from the PCB finish and component leads, then helps molten solder spread into the plated hole. Selective equipment usually applies a controlled drop, jet, or spray pattern around the target area rather than coating the complete underside.

The deposit must reach the joint without flooding nearby components. Too little flux can cause non-wetting or incomplete barrel fill. Too much flux can splash, spread under low-clearance components, create solder balls, or leave residues that have not received enough heat to become benign. Flux chemistry must also match the alloy, board finish, cleaning plan, and product reliability requirements.

Preheat then activates the flux and reduces the temperature difference between the assembly and the molten solder. This is especially important for thick PCBs, heavy-copper constructions, large connector pins, and pins tied to power or ground planes. These structures draw heat away from the barrel. Without enough preheat, solder may wet the bottom pad but fail to rise adequately through the hole.

More heat is not always the answer. Excessive preheat can exhaust the useful flux activity before solder contact, stress temperature-sensitive parts, warp the PCB, or reduce the margin for nearby low-mass joints. A stable profile prepares the most demanding joints without overheating the rest of the assembly.

How the Solder Nozzle Forms Through-Hole Joints

The nozzle pumps molten solder into a small, continuously flowing fountain. The PCB or nozzle moves until the selected pins enter the controlled solder wave. Heat transfers through the leads, pads, and plated barrels; activated flux supports wetting; and capillary action helps solder rise through the hole.

Nozzle diameter and shape must suit the accessible space and joint group. A larger nozzle can transfer more heat and process a row efficiently, but it requires more clearance. A smaller nozzle can reach isolated pins close to bottom-side SMDs, although its narrower thermal capacity may require a different speed or contact time.

Movement is part of joint formation. Approach direction, immersion depth, travel speed, dwell time, solder-flow height, and withdrawal angle affect how solder enters and leaves the joint. If the nozzle pauses too long, the PCB receives unnecessary heat. If withdrawal is poorly controlled, solder may remain between adjacent pins and create a bridge or icicle.

The nozzle also needs a clean and stable surface. Oxide buildup, contamination, uneven solder flow, or incorrect pump behavior can change the fountain even when the program remains unchanged. Routine nozzle maintenance and process checks therefore protect repeatability as directly as the stored motion program.

Which Parameters Control Selective Soldering Results?

The result comes from the combined thermal, chemical, mechanical, and geometric conditions at each joint. The most influential parameters include:

Control	If it is too low or too short	If it is too high or too long
Flux deposit	Non-wetting or poor fill	Residue, splashing, or solder balls
Preheat	Inactive flux and cold barrels	Flux exhaustion, warpage, or component stress
Solder contact	Incomplete wetting or fill	Excess heat and copper dissolution risk
Travel speed	Insufficient heat transfer	Bridging or prolonged exposure
Solder-wave height	Unstable contact	Flooding or contact with nearby areas

Board construction determines how those settings behave. Finished hole size, lead diameter, copper weight, plane connections, thermal reliefs, PCB thickness, surface finish, and component mass can make two visually similar pins need different thermal treatment.

The correct process window therefore comes from the actual assembly, not a universal temperature or speed copied from another job. When one pin is difficult, the team should identify whether the restriction comes from solderability, flux delivery, hole fit, thermal mass, nozzle access, or motion before changing the complete profile.

Selective Soldering Defects and Their Process Causes

Selective soldering defects are usually the visible result of an earlier process condition. Effective correction starts by tracing the defect back to fluxing, preheat, geometry, solder contact, movement, materials, or handling.

Defect	Likely process causes	Practical investigation
Bridging	Excess contact, tight pitch, poor withdrawal, unstable flow	Check path, speed, nozzle, lead length, and mask geometry
Poor barrel fill	Low preheat, high thermal mass, weak wetting, unsuitable hole fit	Compare difficult pins with ordinary pins and review the thermal path
Non-wetting	Oxidized finish or leads, insufficient flux, contamination	Check storage, solderability, flux delivery, and surface condition
Solder balls	Excess flux, splashing, moisture, inadequate preheat	Review deposit volume, drying, material condition, and nozzle stability
Icicles	Slow or unstable withdrawal, excess solder contact	Review exit direction, travel speed, wave height, and lead protrusion
Pad or barrel damage	Excessive heat or repeated touch-up	Review contact time, solder temperature, rework history, and PCB condition

Increasing solder temperature can appear to improve fill, but it can also accelerate copper dissolution, shorten the usable flux window, and increase thermal stress. Likewise, adding more flux may temporarily improve wetting while creating residue or reliability concerns elsewhere.

A useful defect review compares the failed joint with a successful joint on the same assembly. Differences in plane connection, pin mass, hole fit, local clearance, nozzle direction, or flux coverage often reveal the actual cause faster than changing several machine settings at once.

Selective Soldering vs Wave Soldering Process Differences

Both methods solder plated through-hole components with molten solder, but they create very different exposure and production conditions.

Process factor	Selective soldering	Wave soldering
Solder contact	Programmed joints or groups	Most of the PCB underside
Typical fit	Mixed SMT/THT assemblies	THT-heavy, wave-compatible layouts
Main setup	Flux pattern, nozzle, path, and local profile	Conveyor profile, full wave, pallet or masking
Cycle behavior	Time grows with the programmed path	Many accessible joints solder at once
Main limitation	Nozzle access and local cycle time	Broad heat exposure and component protection

Selective soldering is often preferable when bottom-side SMDs sit near a limited number of THT locations, when a connector needs more consistency than repeated hand soldering, or when board variants change the required joint locations. Wave soldering can remain more efficient when the underside is designed for broad solder exposure and many through-hole joints must be processed in one pass.

The choice should reflect the actual board. A selective process may avoid a dedicated wave pallet and reduce touch-up, yet its programmed cycle may be slower. Wave soldering may offer higher throughput, but masking, pallet cost, heat exposure, and rework can change the total production result.

Selective Soldering Process for Mixed SMT and Through-Hole Assemblies

Consider a double-sided SMT assembly that receives a multi-pin connector, a relay, and a plane-connected power terminal after reflow. Bottom-side passives sit close to the connector pins, while the power terminal draws heat into a large copper area.

The connector row may suit a shaped nozzle that solders several pins along one controlled path. Nearby SMDs determine the available nozzle diameter and travel direction. The power terminal may need stronger preheat or a separate dwell condition because its copper connection removes heat faster than the connector pins. The relay body and leads must remain clear of the nozzle approach and withdrawal path.

This assembly should not be validated by looking only at the easiest connector pins. Inspection must include the plane-connected terminal, the connector ends where bridging may occur, and any joint close to a bottom-side package. If those locations meet the agreed criteria without excessive touch-up, the process has demonstrated control across the actual thermal and geometric range of the PCB.

If the nozzle cannot reach a pin, the solution may require a layout adjustment, different PCB assembly fixtures or panel support, another nozzle, approved hand soldering for that location, or a different overall soldering method. Programming cannot recover physical access that the assembled board does not provide.

How EBest Circuit Controls the Selective Soldering Process

For a released PCBA project, EBest Circuit reviews the board data, BOM, assembly drawing, component geometry, panel method, soldering requirements, and inspection criteria before production. This helps identify blocked joints, high-thermal-mass pins, tight connector spacing, special alloy or cleaning requirements, and locations that may need separate process treatment.

PCBA process control focuses on the items that determine repeatability:

matching the PCB and assembly revisions to the approved production package;
confirming component orientation, insertion, lead condition, and accessibility;
setting flux, preheat, nozzle, path, and solder-contact conditions for the actual board;
checking ordinary joints and thermally demanding joints during the first article;
recording the approved process and controlling later changes;
inspecting finished joints against the customer’s specified workmanship criteria;
completing agreed electrical testing, traceability, and production records.

The customer remains responsible for the released circuit design, component approval, regulatory requirements, and final product validation. EBest Circuit’s role is to turn the approved PCB and PCBA data into a controlled manufacturing process and to resolve manufacturability questions before they become repeated soldering defects.

For a selective-soldering review, send the Gerber files, drill data, BOM, placement file, assembly drawing, component details, quantities, solder alloy, cleaning requirements, and inspection or testing requirements to sales@bestpcbs.com.

FAQs About the Selective Soldering Process

Is selective soldering used before or after SMT reflow?

It is commonly used after SMT reflow. The SMT components are soldered first, and the remaining through-hole connectors, terminals, relays, or other components are then processed at selected locations.

Is selective soldering the same as selective wave soldering?

Selective wave soldering is the common automated method that uses a localized mini-wave or nozzle. “Selective soldering” is the broader term and can include other localized soldering methods.

Can every through-hole component be selectively soldered?

No. The nozzle needs physical access, suitable clearance, a stable thermal path, and a workable soldering surface. Blocked pins or incompatible component geometry may require a layout change or another approved process.

What usually causes poor hole fill in selective soldering?

Common causes include insufficient preheat, high copper mass, unsuitable hole-to-lead fit, weak solderability, inadequate flux activation, or too little solder-contact time. The cause should be identified before raising temperature or dwell time.

Does selective soldering eliminate manual soldering?

It can greatly reduce manual work on accessible, repeatable joint groups. Very low-volume builds, blocked joints, wires, or exceptional component locations may still require a controlled and approved manual operation.

The best selective soldering process is not the one with the highest temperature or the longest contact time. It is the process that delivers enough flux and heat to every required joint, avoids unnecessary exposure elsewhere, and produces repeatable evidence that the complete assembly meets its approved acceptance criteria. Send your PCB files, BOM, quantities, and requirements to sales@bestpcbs.com for a PCBA manufacturing review.

IC Substrate vs PCB: Differences and How They Work Together

October 5th, 2026

In an IC substrate vs PCB comparison, the two may look similar because both contain patterned copper conductors, insulating materials, vias, and multiple layers. However, they perform different jobs at different levels of an electronic system. An IC substrate connects a semiconductor die to the next level of packaging or to a PCB, while the PCB connects the packaged IC to memory, power devices, connectors, sensors, and other components.

Understanding this distinction helps engineers and sourcing teams avoid treating an IC substrate as simply a smaller PCB. The differences affect materials, conductor geometry, via technology, registration, inspection, manufacturing yield, and supplier selection.

EBest Circuit supports customers with IC substrate and PCB manufacturability review, material and stackup coordination, precision fabrication, inspection, and production planning. If you are comparing the two technologies for an upcoming project, send your drawings, stackup, critical dimensions, and volume requirements to sales@bestpcbs.com for an initial manufacturing review.

What Is an IC Substrate?

An IC substrate is the interconnection platform that supports a semiconductor die and connects its dense array of terminals to larger, more widely spaced connections. It is commonly located inside an IC package, between the die and the main PCB.

The substrate performs several jobs at once:

It mechanically supports the semiconductor die.
It redistributes very fine die-level connections to a larger connection pattern.
It carries power and electrical signals between the die and the PCB.
It provides controlled electrical paths for high-speed or high-frequency signals.
It contributes to heat transfer and package reliability.

Depending on the package, the die may connect to the substrate through wire bonding or flip-chip interconnection. The substrate may then connect to the system PCB through a ball grid array or another package interface.

IC substrates can be made with organic build-up materials, BT resin systems, ceramics, or other specialized material systems. The appropriate construction depends on the package architecture, interconnection density, electrical requirements, thermal behavior, and reliability target.

An IC substrate is therefore not the chip itself and is not the main system board. It is the high-density bridge that allows a small semiconductor die to communicate with the larger electronic assembly.

Where Do IC Substrates and PCBs Fit in an Electronic System?

The easiest way to understand the distinction is to follow the electrical path from the chip to the finished product:

Semiconductor die → IC substrate → packaged IC → PCB → complete electronic system

The IC substrate works at the package level. It handles the transition from extremely small die connections to package-level terminals. The PCB works at the board and system level. It routes signals and power among the packaged IC and the rest of the electronic components.

The IC substrate focuses on one semiconductor package. Its design is closely tied to the die, package format, bump or bond-pad arrangement, and package reliability requirements.

The PCB supports the wider circuit. It connects processors, memory, power-management devices, connectors, passive components, sensors, and other packages required by the product.

This means the two technologies are usually complementary rather than competing choices. A processor may require an IC substrate inside its package and a multilayer PCB beneath that package. Removing either interconnection level would require a different package and system architecture—not a simple material substitution.

For customers, the practical implication is that the substrate and PCB cannot be specified independently when signal integrity, power delivery, thermomechanical behavior, or escape routing is critical. Their interface must be considered early enough to avoid incompatible pad geometries, stackups, assembly profiles, or reliability assumptions.

IC Substrate vs PCB: Key Differences at a Glance

The most important difference is scale. An IC substrate manages dense package-level interconnections close to the semiconductor die; a PCB manages board-level connections across the product.

Comparison	IC substrate	PCB
Primary role	Connects and supports a semiconductor die	Connects packaged components in a circuit
System position	Inside or directly beneath the IC package	Main board or functional circuit board
Interconnection density	Very high	Varies from conventional to advanced HDI
Typical conductor geometry	Finer lines, spaces, pads, and vias	Generally larger, depending on PCB technology
Material focus	Package-level electrical, thermal, and dimensional demands	Board-level electrical, mechanical, and assembly demands
Manufacturing control	Very tight registration and defect control	Broad range from standard PCB to advanced HDI control
Design dependency	Closely tied to die and package architecture	Closely tied to system circuit and component placement

These are general distinctions, not universal dimensional limits. Advanced HDI and substrate-like PCBs can use features much smaller than conventional PCBs, while different IC substrate technologies have different capabilities. The actual manufacturing boundary must be established from the proposed stackup and feature sizes.

How Do IC Substrate and PCB Structures Differ?

Both products can use multilayer constructions, but their structures are optimized for different interconnection levels.

An organic IC substrate often uses a core with fine-feature build-up layers on one or both sides. Microvias connect the build-up layers, while the routing redistributes die-side connections toward the package interface. Some advanced constructions may be coreless or use other specialized architectures.

A PCB may use plated through holes, buried vias, blind vias, stacked or staggered microvias, and sequential lamination. Its construction is selected around component escape routing, controlled impedance, power distribution, mechanical thickness, assembly, and product-level reliability.

The structural difference customers should notice is the transition in connection scale. The die-facing side of an IC substrate must accommodate a much denser terminal pattern than a typical component-facing PCB layer. That density drives finer conductors, smaller vias, tighter alignment, and more demanding inspection.

It is also important not to confuse an IC substrate with a substrate-like PCB. Substrate-like PCB technology narrows the gap between advanced HDI PCBs and package substrates by using finer board-level features. However, its role, production flow, and qualification requirements still depend on the specific product architecture. The terms should not be treated as interchangeable without reviewing the actual construction.

Before requesting a quotation, customers should identify which interface each drawing represents: die side, package side, component side, or system-board side. That one clarification prevents many incorrect capability comparisons.

What Materials Are Used in IC Substrates and PCBs?

Material selection follows the function of each product.

Organic IC substrates commonly use BT resin or ABF-based build-up materials, along with copper conductors and application-specific core materials. Ceramic substrates may use alumina, aluminum nitride, or other ceramic systems when thermal, dimensional, environmental, or electrical requirements justify them.

PCBs commonly use FR-4-class laminates, but that description covers a wide range of resin systems and glass constructions. High-speed, high-frequency, high-temperature, metal-core, flexible, and rigid-flex PCBs use different material families according to their operating requirements.

For an IC substrate, material decisions are closely tied to the package. Important factors can include dimensional stability, coefficient of thermal expansion, dielectric behavior, moisture response, warpage, copper adhesion, and compatibility with the selected package process.

For a PCB, material decisions are tied to the assembled product. The designer may prioritize controlled impedance, signal loss, thermal performance, voltage isolation, mechanical strength, soldering temperature, operating environment, and cost.

Customers should avoid selecting materials from a generic name alone. A commercially familiar resin family does not guarantee that every supplier, thickness, copper configuration, or build-up process will produce equivalent results. The fabricator needs the electrical targets, mechanical constraints, thermal conditions, reliability expectations, and approved-material requirements before confirming a practical construction.

Why Does an IC Substrate Require Greater Manufacturing Precision?

An IC substrate has to redistribute a large number of connections within a very small area. As die I/O density increases, the available routing space becomes more limited and small manufacturing variations consume a larger part of the tolerance budget.

Greater precision is normally required in several areas:

Fine lines and spaces: Dense routing demands narrower conductors and smaller separations.
Small microvias: Compact interconnections require carefully controlled via formation, metallization, and capture-pad alignment.
Layer registration: Small pads and conductors leave less room for layer-to-layer misalignment.
Dielectric thickness: Variations can affect impedance, via geometry, and overall package thickness.
Surface quality: Fine-pitch connections require suitable flatness, cleanliness, and finish control.
Warpage: Excessive deformation can interfere with die attachment, package assembly, or board-level soldering.
Defect detection: Small opens, shorts, voids, residues, and registration errors may require higher-resolution inspection.

These controls affect both feasibility and yield. A design may look complete in CAD but still be unsuitable for stable production if its minimum features sit too close to the supplier’s process limits across a large area or high layer count.

The customer benefit of an early manufacturability review is therefore not merely getting the design “approved.” It is identifying where tolerances, via structures, pad sizes, material behavior, or inspection limits could create yield and reliability risk before those risks become embedded in tooling and production.

How Does IC Substrate Manufacturing Differ from PCB Manufacturing?

Both manufacturing flows build patterned conductors and interlayer connections, but the equipment, process windows, materials, and control levels can differ substantially.

Conventional PCB production may include laminate preparation, imaging, etching, drilling, plating, lamination, solder-mask application, surface finishing, electrical testing, and final inspection. Advanced HDI PCB production adds sequential build-up cycles, laser-drilled microvias, via filling, tighter registration, and finer imaging.

IC substrate manufacturing generally pushes these controls further toward package-level feature density. Depending on the construction, production may involve repeated build-up formation, fine-feature patterning, microvia creation, copper deposition and plating, precision lamination, surface treatment, and high-resolution inspection.

The main manufacturing differences affect the customer’s project in four ways:

Design rules: Minimum conductors, spaces, via sizes, annular structures, and registration allowances must match the specific process.
Yield sensitivity: A small feature repeated thousands of times can become a meaningful yield driver.
Tooling and inspection: Finer features may require different imaging, drilling, metrology, and defect-detection capability.
Qualification and lead time: Material approval, process validation, samples, and reliability testing may require more planning than a standard PCB order.

Customers should compare suppliers using the proposed construction—not a general statement that a factory can manufacture “fine-pitch boards.” Useful evidence includes capability matched to the required stackup, demonstrated control of the critical feature, appropriate inspection methods, and a realistic prototype-to-volume plan.

Can a PCB Replace an IC Substrate?

In most conventional package architectures, no. A standard PCB is not a direct replacement for the IC substrate because it is designed for a different interconnection level.

The substrate must accept the die-side connection pattern, redistribute those connections, satisfy package-level mechanical and electrical requirements, and provide a suitable interface to the PCB. A conventional PCB normally does not provide the necessary combination of feature density, package geometry, material behavior, and assembly compatibility.

Advanced HDI or substrate-like PCB technologies can reduce the dimensional gap in certain applications. That does not automatically make them interchangeable with a package substrate. The decision depends on:

Die or package interconnection method
Required line, space, pad, and microvia geometry
Layer count and routing density
Electrical and power-delivery targets
Package thickness and warpage limits
Thermal and coefficient-of-expansion behavior
Assembly and reliability requirements
Qualified manufacturing process

The better question is not, “Can we use a cheaper PCB instead?” It is, “Which interconnection architecture satisfies the package, board, assembly, and reliability requirements with a manufacturable process?” Answering that question requires collaboration among the package designer, PCB designer, assembly provider, and fabricator.

How Do IC Substrates and PCBs Work Together?

The IC substrate and PCB form consecutive parts of the same electrical and mechanical path.

Signals and power travel from the semiconductor die through the substrate routing, across the package-to-board interface, and into the PCB. From there, the PCB distributes them to power circuits, memory, connectors, sensors, and other devices.

Because the two products meet at the package interface, several decisions must align:

Pad and ball geometry: The PCB land pattern must match the packaged device.
Escape routing: The PCB must route away from the package without violating impedance, spacing, or layer-transition requirements.
Power delivery: Package and board power structures must work together to control voltage drop, noise, and current density.
Signal integrity: The complete channel includes structures in both the substrate and PCB.
Thermal behavior: Heat spreading, copper distribution, vias, heatsinks, and airflow belong to one thermal system.
Warpage and assembly: Substrate, package, PCB, and solder-joint behavior affect board-level assembly yield and reliability.

For customers, this is why separate optimization can create system-level problems. A substrate may meet its standalone requirements while the PCB escape routing remains impractical. A PCB may pass its own electrical checks while the complete die-to-board channel does not meet the system target.

The safest development path is to review interface assumptions early, freeze compatible mechanical and electrical definitions, and communicate every stackup or material change that could affect the other interconnection level.

FAQs About IC Substrate vs PCB

Is an IC substrate a type of PCB?

They share basic interconnection principles, but an IC substrate is a specialized package-level platform with different feature density, materials, process controls, and interfaces. Calling it simply a small PCB hides the manufacturing and reliability differences that matter to the project.

What is the main purpose of an IC substrate?

Its main purpose is to support a semiconductor die and redistribute the die’s dense connections to a larger package interface that can connect to the system PCB.

Why are IC substrates generally more difficult to manufacture?

They typically require finer conductors, smaller vias, tighter registration, greater dimensional control, more demanding surface quality, and higher-resolution inspection. Their manufacturability is also closely tied to a specific package design.

Are all IC substrates made from ceramic?

No. IC substrates may use organic material systems such as BT resin or ABF build-up materials, as well as ceramic systems. The selection depends on the package, electrical, thermal, mechanical, reliability, and production requirements.

What is the difference between an IC substrate and a substrate-like PCB?

An IC substrate normally operates inside a semiconductor package. A substrate-like PCB uses finer board-level fabrication techniques to achieve higher routing density than conventional PCBs. The exact boundary varies by construction and process, so the product role and required design rules must be reviewed rather than inferred from the name.

What information should be reviewed before IC substrate fabrication?

The review normally needs the stackup, materials, finished thickness, conductor geometry, via structure, pad definitions, tolerances, surface-finish requirements, critical electrical targets, inspection criteria, reliability requirements, quantities, and intended package or assembly process.

Should the IC substrate and PCB be sourced from the same manufacturer?

Not necessarily. What matters is whether each supplier has the appropriate process capability and whether the interface requirements are consistently controlled. Using one manufacturing partner can simplify communication, but it does not replace technical qualification for both product types.

The essential conclusion in the IC substrate vs PCB comparison is that they solve different interconnection problems and usually work together. The substrate connects the semiconductor die to the package interface; the PCB connects that packaged device to the rest of the electronic system. Understanding the boundary early helps customers choose realistic design rules, materials, inspection methods, and production plans.

EBest Circuit can review your IC substrate or PCB data for manufacturability, material availability, stackup feasibility, critical feature control, inspection planning, and prototype-to-production considerations. Send your project files and key requirements to sales@bestpcbs.com to discuss the next manufacturing step.

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