Bismaleimide Triazine (BT Resin): Properties, BT Epoxy & FR-4 Comparison

September 18th, 2026

Bismaleimide triazine has become an important resin system for electronic materials that need more dimensional and thermal stability than conventional PCB laminates can provide. It is particularly well known in semiconductor packaging, where thin substrates, fine interconnections, repeated reflow cycles, and moisture sensitivity place tight demands on the laminate.

However, the terminology around BT materials is often inconsistent. BT resin, BT epoxy, BT laminate, BT PCB, and BT substrate do not mean exactly the same thing. Understanding these distinctions is important before comparing material properties or releasing a PCB or substrate specification.

Bismaleimide Triazine BT resin with multilayer PCB laminate and semiconductor package applications

Key Takeaways

Bismaleimide triazine, commonly called BT resin, is a high-performance thermosetting resin system used in PCB laminates and semiconductor package substrates.
BT is a material family rather than one fixed laminate grade. Tg, Dk, Df, CTE, moisture absorption, and other properties vary with resin formulation, reinforcement, fillers, and cure system.
BT epoxy usually refers to a BT resin system modified or blended with epoxy to improve processability, adhesion, toughness, resin flow, or other manufacturing characteristics.
BT laminate, BT PCB, and BT substrate are different terms: the first describes the supplied material, while the latter two describe finished electronic structures.
Compared with standard FR-4, BT materials are commonly selected where dimensional stability, thermal performance, moisture control, and package warpage are more demanding.
BT resin is widely associated with BGA, CSP, SiP, memory, and other organic semiconductor package substrates.
BT is not automatically better than FR-4. Standard or high-Tg FR-4 remains more practical for many conventional multilayer PCBs.
Engineers should specify an exact material manufacturer and grade instead of requesting only “BT material.”

What Is Bismaleimide Triazine (BT Resin)?

Bismaleimide triazine, or BT resin, is a high-performance thermosetting resin system based primarily on bismaleimide and cyanate-ester chemistry. It is widely used in electronic laminates and organic semiconductor package substrates.

The search phrase bismaleimide triazine BT resin refers to this formulated resin family rather than one universal commercial grade.

During curing, the reactive resin components form a highly crosslinked three-dimensional network. This structure can provide a useful combination of:

High glass-transition temperature
Dimensional stability
Low moisture absorption
Thermal resistance
Electrical insulation
Controlled dielectric properties
Good compatibility with multilayer structures

BT resin is not one single chemical compound or one fixed commercial material. Different suppliers can modify the formulation with epoxy, fillers, catalysts, flame retardants, reinforcement, and other additives.

For this reason, an engineer should not assume that every BT laminate has the same Tg, Dk, Df, CTE, or processing conditions.

How Is Bismaleimide Triazine Resin Structured and Cured?

BT resin should be understood as a crosslinked resin system rather than a single molecule with one fixed structure.

A bismaleimide triazine structure is best described as a cured network whose final properties depend on formulation and processing.

Its chemistry generally combines bismaleimide functionality with cyanate-ester chemistry. During curing, cyanate groups can react to form thermally stable triazine-ring structures, while the bismaleimide portion contributes additional crosslinking and heat resistance.

A simplified reaction concept is:

Bismaleimide + Cyanate-Ester Chemistry → Thermal Cure → Crosslinked BT Resin Network

The resulting network can be further modified to balance electrical, mechanical, and processing properties.

Bismaleimide Component

The bismaleimide portion contributes thermal stability and a highly crosslinked structure. Pure BMI systems can be relatively rigid or brittle, so practical electronic formulations are often modified.

Cyanate-Ester Component

Cyanate groups form triazine-ring structures during curing. These structures are associated with high-temperature performance and useful dielectric characteristics.

Modifiers

Commercial BT systems may incorporate epoxy or other modifiers to improve flow, toughness, adhesion, cure behavior, and PCB processing.

Therefore, drawings that show one exact “BT molecule” can be misleading. The material used in an actual laminate is a formulated thermoset system.

What Is the Difference Between BT Resin, BT Epoxy, BT Laminate and BT Substrate?

These terms describe different stages or forms of the material system.

Term	Meaning
BT resin	Bismaleimide-triazine thermosetting resin chemistry
BT epoxy	BT resin system modified or blended with epoxy
BT prepreg	Reinforcement impregnated with partially cured BT-based resin
BT laminate	Cured reinforced sheet material made with a BT resin system
BT PCB	Printed circuit board fabricated using BT-based laminate
BT substrate	Finished semiconductor package substrate using BT-based material

The distinction matters during RFQ and material selection. Asking for “BT resin” does not tell a PCB manufacturer which laminate construction, copper foil, glass style, resin content, or cured thickness to use.

Similarly, a BT substrate is not merely a sheet of BT laminate. It is a finished interconnect structure that can contain fine traces, microvias, solder-mask or build-up layers, package pads, and other features.

For more detail on package construction, SAP/mSAP processing, and BT vs ABF, see our BT Substrate: Material, Process and ABF Comparison guide.

BT resin BT epoxy BT laminate and BT substrate terminology comparison

What Properties Matter in a BT Resin Laminate?

The most important BT laminate properties depend on the application. Package substrates may prioritize dimensional stability and moisture behavior, while high-speed boards may place greater emphasis on Dk and Df.

Property	Why It Matters
Tg	Dimensional and mechanical behavior through thermal cycles
Td	Thermal decomposition resistance
X/Y CTE	In-plane dimensional stability
Z-axis CTE	Via and plated-hole reliability
Dk	Impedance, propagation velocity, and trace geometry
Df	Dielectric contribution to signal loss
Moisture absorption	Package reliability and reflow behavior
Peel strength	Copper-to-laminate adhesion
Flexural/mechanical properties	Thin-substrate handling and package stability

The values cannot be generalized to every BT material. For example, AGC’s N5000 is a commercially available BT epoxy laminate and prepreg with published dielectric values around Dk 3.6 and Df 0.01 under its specified test conditions.

Those numbers should be treated as one material-grade example, not as a universal BT specification.

Research and commercial formulations can show substantially different Tg and dielectric performance because resin chemistry, fillers, glass reinforcement, resin content, and test method all influence the result.

Always compare exact material grades using the same test method and frequency.

Key BT resin laminate properties including Tg Dk Df CTE moisture and thermal resistance

Why Is BT Resin Used for BGA, CSP and IC Package Substrates?

BT resin is widely used in organic package substrates because semiconductor packaging requires more than ordinary PCB electrical insulation.

A bismaleimide triazine substrate uses this material family to support fine package interconnections and repeated thermal cycles.

A package substrate must maintain dimensional control while dealing with:

Fine-pitch package routing
Thin core and dielectric structures
Multiple lead-free reflow cycles
Silicon-to-substrate CTE mismatch
Moisture exposure
BGA or CSP warpage
Fine via and pad registration
Package assembly stress

BT-based laminates can provide a useful balance of high-temperature stability, low moisture uptake, mechanical rigidity, and electrical performance.

This is particularly important in thin BGA and CSP structures. Even small dimensional changes can affect solder-ball coplanarity, substrate warpage, trace registration, or package reliability.

BT materials are therefore commonly associated with:

BGA substrates
CSP substrates
Memory packages
SiP modules
Flip-chip package structures
RF and communication modules

The final substrate performance still depends on the exact BT grade, stackup, copper pattern, package size, substrate thickness, and manufacturing process.

Bismaleimide Triazine applications including BGA substrate CSP memory package and RF module

BT Resin vs FR-4: What Is the Difference?

FR-4 and BT resin laminates are both organic electronic materials, but they are normally selected for different performance and cost targets.

Factor	FR-4	BT Resin Laminate
Primary use	General PCB manufacturing	Package substrates and higher-reliability structures
Resin system	Primarily epoxy-based	BT or BT-epoxy-based
Tg	Wide range by grade	Often high, but grade-dependent
Dimensional stability	Suitable for conventional PCB	Better suited to demanding package control
CTE control	Depends on grade and reinforcement	Low-CTE formulations available
Moisture behavior	Grade dependent	Often selected for lower moisture sensitivity
Dielectric properties	Standard to low-loss grades available	Grade dependent; can be optimized for package/high-speed use
Thin-substrate use	Possible but not its main strength	Common in package substrate applications
Processing familiarity	Very mature	More material-specific
Material cost	Lower	Generally higher

The main difference is not simply that BT has a higher Tg. High-Tg FR-4 materials can also provide strong thermal performance.

BT becomes more attractive when several requirements appear together, such as high dimensional stability, low package warpage, moisture resistance, thin substrate construction, repeated reflow reliability, and fine-pitch interconnection.

FR-4 remains the more economical and widely available choice for most conventional PCBs.

Is BT Resin Always Better Than FR-4?

No. BT resin is not automatically a better PCB material than FR-4. It is better suited to certain applications where its material characteristics solve specific reliability or dimensional problems.

Standard or high-Tg FR-4 is usually the practical choice for:

Industrial control boards
Consumer electronics
General multilayer PCBs
Power-control boards
Cost-sensitive products
Conventional SMT assemblies
Moderate-density HDI designs

BT becomes more attractive when the product requires:

Semiconductor package substrate construction
Very thin organic substrates
Tighter dimensional stability
Lower package warpage
Fine-pitch BGA or CSP structures
Low moisture sensitivity
Higher package-level thermal reliability

Using BT where ordinary FR-4 already meets the electrical and reliability requirements can increase material cost and supply complexity without creating a meaningful product benefit.

The correct decision should come from the complete stackup, package geometry, thermal cycle, electrical requirements, warpage target, and qualification specification.

Where Is Bismaleimide Triazine Used in Electronics?

Bismaleimide triazine materials are most strongly associated with semiconductor packaging, but their use is not limited to one product type.

A bismaleimide triazine PCB may also be specified when a conventional board needs the qualified thermal or dimensional behavior of a BT laminate.

Common applications include:

BGA package substrates
CSP substrates
Memory package substrates
System-in-Package modules
RF modules
Communication modules
Selected LED package substrates
High-reliability electronic modules
Selected high-frequency PCBs
Thin multilayer interconnect structures

A BT laminate can also be used for conventional PCB structures when its thermal or dimensional characteristics provide a useful engineering advantage.

However, it should not be assumed that every high-speed PCB needs BT resin. Modern high-speed boards can use multiple material families, including low-loss FR-4 derivatives, PPE/PPO systems, PTFE-based laminates, hydrocarbon ceramics, and other specialty materials.

The application requirement should determine the laminate family, not the material’s reputation alone.

What Are the Manufacturing Challenges of BT Epoxy Laminate?

BT epoxy laminate can require tighter material and process control than a standard FR-4 production flow.

Important manufacturing factors include:

Material storage
Moisture control
Prepreg handling
Lamination temperature and pressure
Resin-flow control
Cure profile
Dimensional movement
Drilling parameters
Desmear conditions
Copper adhesion
Thin-board handling
Warpage control

Moisture Management

Low moisture absorption is an important material characteristic, but storage and handling still matter. Prepreg and thin laminate structures should follow supplier recommendations.

Lamination

BT resin flow and cure behavior differ by formulation. The press cycle should follow the actual laminate supplier’s process window rather than an FR-4 recipe being reused automatically.

Drilling and Hole Preparation

Drill parameters, smear behavior, and desmear chemistry can depend on the cured resin system and glass construction.

Dimensional Stability

Package substrates and thin BT boards may require tighter compensation because small X/Y movement can affect fine-pitch registration.

Warpage

Thin BT-based structures can still warp if copper distribution, build-up symmetry, substrate thickness, package design, or lamination stress is unbalanced. A high-performance resin does not eliminate the need for mechanical stackup control.

How Should Engineers Specify BT Material for PCB Fabrication?

A production drawing should identify the exact BT laminate requirements rather than simply stating “BT material.”

Useful information includes:

Material manufacturer
Exact material grade
Core or prepreg designation
Finished dielectric thickness
Glass style
Resin content
Copper foil type and weight
Tg and test method
Dk and Df test frequency/method
X/Y and Z-axis CTE where critical
Moisture requirement
Finished board thickness
Surface finish
Controlled impedance
Approved alternative materials

For high-frequency designs, Dk and Df values should be tied to the relevant test method and frequency. A Dk value measured by one method should not automatically replace a design Dk obtained through another method.

For thin or packaging-related structures, engineers should also specify dimensional, warpage, and registration requirements where applicable.

“Use BT material” is not enough for a controlled production release. Two BT laminates may differ significantly in processing behavior and electrical performance.

BT laminate specification guide including material grade Tg Td Dk Df glass style copper type and thickness

When Should You Choose BT Resin Instead of Another PCB Material?

Material selection should start from the product requirement rather than choosing BT first and designing around it.

Requirement	Material Direction to Consider
General multilayer PCB	Standard or high-Tg FR-4
Cost-sensitive electronics	FR-4
High-reliability conventional PCB	High-Tg / specialty FR-4
BGA/CSP organic package substrate	BT resin commonly considered
Thin warpage-sensitive package	BT or another qualified package substrate material
Very high-speed PCB	Low-loss FR-4, PPE/PPO, PTFE/hydrocarbon or other high-speed materials
Flexible circuit	Polyimide
Very high thermal conductivity	Ceramic or metal-based structures
Advanced high-density IC build-up	BT core, ABF, or other package-specific systems

BT is strongest when thermal, moisture, dimensional, and package-level requirements need to be balanced in one organic material system.

It is not necessarily the first choice for ultra-high-frequency transmission, extreme thermal conductivity, flexible construction, or every advanced IC substrate architecture.

The material decision should therefore consider the entire structure: electrical performance, package geometry, process capability, reliability, cost, supply availability, and customer qualification.

FAQ About Bismaleimide Triazine

1. What does BT stand for in PCB materials?
BT stands for Bismaleimide Triazine, a high-performance thermosetting resin system used in electronic laminates and package substrates.

2. Is BT resin the same as BT epoxy?
No. BT epoxy generally refers to a BT resin system that has been modified or blended with epoxy to adjust processing, adhesion, toughness, or other material properties.

3. Is BT resin better than FR-4?
Not for every PCB. BT is most useful when thermal stability, dimensional control, moisture behavior, package warpage, or semiconductor-substrate requirements justify the additional material cost.

4. Is BT resin used for BGA substrates?
Yes. BT resin is widely associated with BGA, CSP, memory, SiP, and other organic semiconductor package substrates.

5. Does every BT laminate have the same Tg and Dk?
No. BT is a material family. Tg, Dk, Df, CTE, moisture absorption, and other values vary by formulation, reinforcement, resin content, and test method.

6. Is a BT substrate the same as an IC substrate?
A BT substrate is one type of organic IC package substrate. Other IC substrates can use ABF and additional material systems depending on package architecture and interconnect density.

Bismaleimide triazine should therefore be specified as a material system, not as a single fixed-property laminate. Resin formulation, epoxy modification, glass reinforcement, copper construction, thickness, and processing conditions all influence how the finished PCB or substrate performs.

For a PCB project requiring BT laminate or another specialty material, EBest Circuit can review the material grade, stackup, dielectric thickness, copper construction, impedance requirements, finished thickness, and manufacturing constraints before fabrication. Send your project files to sales@bestpcbs.com for DFM review.

HVLP Copper Foil for AI Server PCBs: M9, 52-Layer Designs & Signal Loss

September 17th, 2026

AI server PCB materials are entering another upgrade cycle. A September 16, 2026 industry report highlighted movement toward 52-layer PCB architectures and M9-class CCL as cloud providers continue expanding AI infrastructure. The change is not simply more copper layers; higher data rates are forcing designers to control dielectric loss, conductor loss, impedance consistency, and phase behavior together.

That is why HVLP copper foil is becoming more important. As resin and glass systems reduce dielectric loss, rough copper can consume a larger portion of the channel-loss budget. The practical question for PCB engineers is therefore no longer only “Which laminate grade should I use?” but also which copper profile is needed, on which layers, and how should that low roughness be preserved through fabrication?

HVLP copper foil for AI server PCBs with M9 materials and 52-layer high-speed design

Key Takeaways

HVLP copper foil is used to reduce conductor loss in high-speed PCB channels by lowering the surface profile at the copper-dielectric interface.
AI server PCBs are moving toward higher layer counts and lower-loss M9-class material systems, making copper roughness increasingly important alongside resin Df and glass construction.
HVLP describes copper surface profile, not copper thickness. An 18 μm or 35 μm foil can still be a low-profile copper construction.
A 52-layer PCB does not necessarily require HVLP on every layer. Long high-speed signal channels usually deserve the lowest-profile copper first.
HVLP3, HVLP4, and HVLP5 are not universal IPC roughness classes. Engineers should verify actual Rz/Rq, foil thickness, treatment side, peel strength, and insertion-loss data.
Very smooth copper creates a manufacturing trade-off: lower conductor loss must be balanced with sufficient copper-to-resin adhesion.
PCB processing also matters. Aggressive inner-layer pretreatment can increase roughness and reduce the signal-integrity advantage of the incoming HVLP foil.

Why Is HVLP Copper Foil Demand Rising in AI Server PCBs?

HVLP copper foil demand is rising because AI server boards are combining more PCB layers with faster, longer loss-sensitive channels. The current AI infrastructure cycle is pushing higher-layer-count architectures together with M9-class material upgrades.

Three changes are happening at the same time:

PCB layer counts are increasing.
SerDes data rates continue moving toward 112G and 224G-class links.
CCL systems are reducing dielectric loss, making conductor loss more visible.

The demand increase therefore comes from both more high-speed PCB material per server and a higher proportion of signal layers requiring smoother copper.

What Is HVLP Copper Foil?

HVLP copper foil is a very-low-profile copper construction designed to maintain a smoother copper-dielectric interface than conventional electrodeposited copper.

The exact terminology varies by supplier. Some suppliers describe HVLP as ultra-low-profile copper, while the industry also uses “hyper very low profile” informally. What matters electrically is the actual surface morphology and measured roughness rather than the name alone.

Typical parameters to review include:

Rz surface roughness
Ra, Rq, or Sq where specified
Treatment-side roughness
Foil thickness
Tensile strength
Elongation
Peel strength

Copper profile and copper thickness are different parameters. A smoother HVLP foil can still be supplied in common thicknesses such as 12, 18, or 35 μm.

HVLP copper foil smooth surface compared with rough standard copper foil

HVLP vs VLP vs RTF vs Standard Copper Foil: What Changes?

The main difference is the surface profile presented to the dielectric. Lower-profile foil reduces the microscopic path length seen by high-frequency surface current.

Copper Foil Type	Surface Character	Typical Design Direction
Standard ED	Relatively rough	General-purpose PCB
RTF	Reduced profile on functional side	Mid- to high-speed PCB
VLP	Low profile	High-speed digital / RF
HVLP	Very low profile	Very-high-speed low-loss channels
Advanced HVLP	Extremely low profile	112G/224G, AI server, mmWave-class applications

These categories should not be treated as fixed global roughness ranges. Supplier processes, treatment methods, and naming conventions differ. For design work, the grade name should therefore be followed by the actual roughness specification and measured electrical performance.

HVLP VLP RTF and standard ED copper foil surface roughness comparison

Why Does M9-Class CCL Still Need Smoother Copper Foil?

M9-class material reduces dielectric loss, but total channel loss also includes conductor loss. Improving only the resin and glass system does not eliminate loss caused by rough copper.

Material Element	Main Role
Low-loss resin	Reduces dielectric loss
Low-Dk / advanced glass	Improves dielectric behavior and dimensional control
HVLP copper foil	Reduces conductor and insertion loss
Complete low-loss CCL	Balances all three for the required channel target

At lower frequencies, dielectric loss may dominate enough that moderate copper roughness is acceptable. As signaling frequency rises, however, current becomes increasingly concentrated near the conductor surface.

That makes the microscopic copper profile part of the signal path. A very-low-Df resin paired with unnecessarily rough copper can therefore surrender part of the improvement gained from the dielectric system. M9 should be evaluated as a complete laminate system rather than as a resin grade alone.

M9-class CCL structure with low-loss resin advanced glass and HVLP copper foil

How Does Copper Roughness Increase Conductor and Insertion Loss?

At high frequency, current flows primarily near the copper surface because of skin effect. When that surface is rough, the current follows a more complex microscopic path and experiences higher effective resistance.

The practical effects can include:

Higher conductor loss
Higher insertion loss
Apparent changes in effective Dk
Additional phase variation
Greater channel-to-channel variation

Published test data has shown that copper profile alone can materially change insertion loss even when the dielectric material remains the same. The exact dB/in change depends on substrate, trace geometry, frequency, and foil construction, so loss figures should always be tied to the actual test vehicle.

Smooth copper versus rough copper showing lower and higher insertion loss

Why Do 52-Layer AI Server PCBs Increase HVLP Copper Foil Demand?

Higher layer counts increase HVLP demand through both a quantity effect and a material-mix effect.

Quantity effect

More copper foil
More CCL cores
More prepreg
More signal-layer area
More lamination materials

Mix effect

At the same time, more routing may move from conventional foil or older low-profile grades toward lower-profile constructions as channel loss budgets tighten.

However, a 52-layer PCB does not mean all 52 layers use HVLP copper foil. Ground planes, power planes, short control traces, and lower-speed auxiliary layers may use different copper constructions.

52-layer AI server PCB showing quantity effect and mix effect on HVLP copper foil demand

Which PCB Layers Actually Need HVLP Copper Foil?

HVLP should normally be prioritized according to channel-loss sensitivity rather than applied to every copper layer by default.

Typical candidates include:

Long SerDes routing
112G/224G-class channels
PCIe and other high-speed differential links
Switch and accelerator interconnects
Backplane or midplane routing
Loss-sensitive memory/network interfaces
High-frequency RF or mmWave layers where applicable

Layers that may not require the same profile include:

Power planes
Ground planes
Short GPIO routes
Low-speed management buses
Short local control connections

The actual choice depends on trace length, data rate, dielectric thickness, insertion-loss budget, and laminate system.

AI server PCB layer stack highlighting high-speed layers that should prioritize HVLP copper foil

HVLP3 vs HVLP4 vs HVLP5: How Should Engineers Interpret the Grades?

HVLP3, HVLP4, and HVLP5 generally indicate progressively smoother copper within a supplier’s product family, but these labels are not universal IPC roughness classifications.

When comparing grades, engineers should request:

Rz
Ra / Rq / Sq where available
Treatment-side roughness
Copper thickness
Treatment chemistry
Peel strength
Resin compatibility
Insertion-loss test data

A buyer should therefore avoid specifying only “HVLP4 required.” A better requirement links the foil grade to a named laminate construction, roughness target, and electrical loss objective.

What Manufacturing Challenges Come with HVLP Copper Foil?

The manufacturing challenge with HVLP is to keep the copper surface smooth enough for low loss while maintaining enough adhesion to survive lamination, thermal cycling, and assembly.

Important controls include:

Copper-to-resin bonding
Inner-layer pretreatment
Brown oxide or alternative oxide chemistry
Lamination pressure and temperature
Resin compatibility
Etching compensation
Peel strength
Impedance consistency
Layer registration
High-layer-count warpage

PCB processing can change the incoming copper surface. The relevant question is not only “Was HVLP purchased?” but also “What roughness remains at the finished signal interface after fabrication?”

HVLP copper foil manufacturing process and engineering specification checklist

How Should Engineers Specify and Verify HVLP Copper Foil?

An HVLP requirement should connect the material specification to the actual electrical channel requirement.

For quotation or stackup review, provide:

Target data rate
Operating or Nyquist frequency
PCB layer count
Laminate family
Copper foil supplier and grade, if mandatory
Copper thickness
Required Rz / Rq / Sq
Treatment side
Layers requiring HVLP
Impedance tolerance
Maximum insertion loss
Critical trace length
Peel-strength requirement
Thermal and reliability requirements

Verification may include:

Impedance coupons
TDR
Insertion-loss coupons
VNA / S-parameter testing
Material certificate or COC
Lot traceability

For very-high-speed projects, the laminate, glass style, copper foil, stackup geometry, and fabrication treatment should be qualified together rather than approved as independent specifications.

What Cost and Supply Risks Should Buyers Check for HVLP4 and HVLP5?

Higher-grade HVLP introduces both material-cost and supply-chain risk because qualification is more restrictive than for standard copper foil.

When selecting an HVLP copper foil supplier, compare the actual Rz/Rq limits, treatment method, laminate qualification, and measured channel-loss data rather than relying on the grade name alone.

Buyers should check:

Qualified copper-foil suppliers
Qualified CCL combinations
Minimum order quantities
Lead time
Alternative material approval
Lot-to-lot roughness control
Qualification quantities
Insertion-loss validation
Whether substitutions require customer approval

A lower-cost foil with the same “HVLP4” label should not automatically be treated as electrically or mechanically equivalent. The actual laminate system, surface treatment, roughness, adhesion, and measured channel loss still need qualification.

FAQ About HVLP Copper Foil

1. What does HVLP mean in copper foil?
HVLP refers to very-low-profile copper foil developed for lower conductor loss. Supplier terminology varies, so the actual Rz/Rq and product specification are more important than the acronym alone.

2. Is HVLP copper thinner than standard copper foil?
No. Copper thickness and copper surface profile are separate parameters. HVLP can be supplied in common foil thicknesses such as 12, 18, or 35 μm.

3. What is the difference between VLP and HVLP copper foil?
Both reduce copper surface roughness, but HVLP generally targets a lower surface profile and more demanding high-speed channels. Exact roughness limits depend on the supplier.

4. Does M9 CCL always use HVLP5 copper foil?
No. M9-class material systems vary by laminate supplier and application. The required copper profile depends on data rate, stackup, trace length, insertion-loss target, and qualified material construction.

5. Does every signal layer need HVLP copper foil?
No. HVLP is normally prioritized for the most loss-sensitive signal layers. Short low-speed routes and non-signal planes may use other copper constructions.

6. What roughness value should I specify for a high-speed PCB?
There is no universal Rz value for every high-speed design. The correct target should be derived from the channel-loss budget and verified against the actual foil, laminate, stackup, and fabrication process.

Planning a High-Speed PCB with HVLP Copper Foil?

HVLP selection is only one part of a high-speed material system. Laminate Dk/Df, glass style, copper profile, trace geometry, layer assignment, impedance, inner-layer treatment, and insertion-loss testing all need to work together.

EBest Circuit can review stackup requirements, impedance targets, copper thickness, laminate availability, HVLP requirements, and manufacturability before quotation. For advanced low-loss PCB projects, send your Gerber files, stackup, material requirement, target impedance, and loss specification to sales@bestpcbs.com for engineering review.

7628 Fiberglass Cloth for PCB: Specs, Uses, Limits & Cost Impact

September 17th, 2026

7628 fiberglass cloth is one of the heavier standard electronic glass fabrics used to reinforce FR-4 laminate and prepreg. It is not dedicated to one particular PCB category. Its main value is structural: compared with thinner glass styles such as 2116 or 1080, 7628 can establish a relatively thick dielectric section with fewer plies.

That makes 7628 especially relevant to conventional FR-4 boards where board thickness, mechanical rigidity, and larger layer-to-layer spacing matter more than extreme routing density. It may still appear in advanced multilayer boards, but high-speed, HDI, CAF-sensitive, and thin-dielectric regions often need closer material evaluation.

7628 fiberglass cloth for PCB stackups with copper foil prepreg and FR-4 core layers

Key Takeaways

7628 fiberglass cloth is a relatively thick, heavy plain-weave E-glass fabric commonly used in FR-4 laminate and prepreg constructions.
Dry 7628 cloth is typically about 0.17 mm thick and 206 g/m², while common resin-impregnated 7628 prepregs can be around 0.20–0.22 mm thick.
It is especially useful when a PCB stackup needs a larger dielectric thickness with fewer prepreg plies.
Conventional FR-4 double-sided boards, industrial multilayers, power boards, automotive control boards, and other moderate-density PCBs are common application areas.
Heavy use of 7628 is less attractive for ultra-thin HDI, very fine via pitch, high-CAF layouts, and high-speed differential routing sensitive to glass-weave effects.
7628 needs careful validation in lead-free and high-CAF designs, particularly where hole-wall spacing becomes tight.
A rise in 7628 fiberglass cloth price does not increase every PCB price by the same percentage; the impact depends on how much 7628-based laminate or prepreg the stackup actually uses.

What Is 7628 Fiberglass Cloth?

7628 fiberglass cloth is a relatively thick electronic-grade E-glass fabric woven in a plain pattern and widely used as reinforcement in FR-4 PCB laminates and prepregs.

The dry fabric itself consists of glass yarn rather than resin. A typical construction uses ECG75 yarn with a nominal 44 warp × 31 fill count per inch. The dry cloth weighs about 206 g/m² and measures about 0.17 mm thick.

In PCB manufacturing, this dry glass fabric is impregnated with epoxy or another resin system before it becomes part of a usable laminate or prepreg construction. Terms such as resin content, prepreg thickness, and cured dielectric thickness describe the resin-impregnated material, not the dry 7628 cloth by itself.

What Are the Typical Specifications of 7628 Fiberglass Cloth?

Typical 7628 parameters are relatively stable at the dry-glass level, while resin content and final prepreg thickness vary by laminate supplier and resin system.

Parameter	Typical Value
Glass type	E-glass
Weave	Plain weave
Dry cloth thickness	~0.17 mm
Fabric weight	~206 g/m²
Warp × fill count	~44 × 31/in
Typical yarn	ECG75 1/0
Typical prepreg resin content	~46–51% in common constructions
Typical prepreg thickness	~0.20–0.22 mm in common higher-RC constructions

Resin content should therefore be treated as a prepreg parameter, not a fixed property of 7628 fiberglass cloth.

7628 E-glass plain weave fiberglass cloth with dry cloth and prepreg thickness specifications

Where Is 7628 Used in a PCB Stackup?

7628 is normally used inside FR-4 cores or prepregs where the stackup needs a relatively large dielectric build between copper layers.

Typical positions include:

Between inner signal and plane layers
Between two power or ground planes
Inside thicker multilayer core constructions
In FR-4 laminate used for conventional double-sided PCBs
In multilayer stackups where one ply needs to add significant dielectric thickness

A simplified multilayer stackup might combine several glass styles rather than using 7628 everywhere. Thinner 1080 or 2116 prepreg may be placed close to dense signal layers, while 7628 is used deeper in the board where more separation is required.

In a 1.6 mm multilayer PCB, this mixed-glass approach can help the fabricator meet total thickness without stacking an excessive number of thin prepreg plies.

Multilayer PCB stackup using 7628 prepreg to create thicker dielectric sections

Which PCBs Commonly Use 7628 Fiberglass Cloth?

7628 is most relevant to conventional FR-4 PCBs that need relatively thick dielectric sections rather than extremely thin, high-density stackups.

Common applications include:

Standard double-sided FR-4 PCBs
4-layer and general multilayer industrial boards
Power supply boards
Appliance control boards
Automotive control electronics
LED and charging equipment
General communication control boards
Multilayer PCBs requiring larger inner-layer spacing
Designs where board rigidity and finished thickness matter

These applications often use moderate line widths, conventional through holes, and relatively generous dielectric spacing. 7628 is therefore less about the end product category and more about how the FR-4 stackup is built.

PCB applications that commonly use 7628 fiberglass cloth including FR-4 industrial power automotive and charger boards

Why Is 7628 Useful for Thick PCB Dielectric Layers?

The main advantage of 7628 is that one ply can create substantially more dielectric thickness than thinner glass styles.

Glass Style	Example Prepreg Thickness
1080	~0.079–0.089 mm
2116	~0.119–0.135 mm
7628	~0.201–0.221 mm

Using 7628 can help:

Build larger layer-to-layer spacing with fewer plies
Reach standard board thickness more efficiently
Increase mechanical stiffness
Simplify some conventional multilayer stackups
Reduce the need to stack several thin prepregs in one dielectric section

Dielectric build per ply comparison of 1080 2116 and 7628 PCB prepreg

Which PCBs Are Less Suited to Heavy Use of 7628?

7628 is usually not the first choice near the most density-sensitive or signal-sensitive structures in an advanced PCB.

Designs that may favor thinner or more uniform glass styles include:

Ultra-thin HDI boards
Any-layer HDI
Fine-pitch microvia structures
Mobile and wearable products requiring very thin dielectrics
Tight hole-to-hole or plane-to-hole spacing
112G/224G high-speed channels
Millimeter-wave circuits
Differential pairs with strict skew limits
Stackups with demanding impedance uniformity

The reason is not that 7628 is unusable in an advanced PCB. A complex board may still use it in less critical internal regions. The concern is heavy use around the most sensitive layers, where its thicker weave, larger glass bundles, and greater dielectric build can make routing density, resin distribution, CAF margin, and high-speed performance harder to control.

Ultra-thin HDI fine via pitch high-speed differential and thin mobile PCBs less suited to heavy use of 7628 fiberglass cloth

What CAF, Wet-Out and Delamination Risks Should Be Checked with 7628?

7628 requires careful validation in high-CAF, tight-hole-spacing, and high-temperature lead-free applications because its heavy glass weave is harder to fully wet with resin.

The main concerns are:

Incomplete resin wet-out at yarn intersections
Limited resin between tightly packed glass fibers
Weak resin-to-glass bonding
Measling
Crazing
Delamination
CAF formation under moisture and electrical bias

Lead-free assembly can add additional thermal stress because the PCB experiences higher process temperatures. The actual risk depends on resin system, hole geometry, process quality, moisture exposure, voltage gradient, and stackup design.

7628 fiberglass cloth cross-section showing resin wet-out tight hole spacing CAF risk and delamination check

How Does 7628 Affect High-Speed Signals and Fiber Weave Effect?

7628 has a relatively visible, coarse glass-weave structure, which can increase local dielectric variation around high-speed traces.

A PCB dielectric is not perfectly homogeneous. Glass-rich regions and resin-rich regions have different dielectric properties. When a trace passes over different portions of the weave, the effective local Dk can vary.

For a differential pair, possible effects include:

Differential skew
Phase-delay mismatch
Local impedance variation
Timing uncertainty
Greater sensitivity at very high data rates

This is one reason high-speed designs may use spread glass, mechanically spread glass, thinner glass styles, or other more uniform constructions around critical channels. 7628 can still exist elsewhere in the same multilayer board where high-speed skew sensitivity is lower.

PCB fiberglass styles and differential pair skew comparison from 7628 to spread glass

7628 vs 2116 vs 1080 vs 106: What Is the Difference?

The main difference between these PCB glass styles is their fabric thickness, yarn structure, resin capacity, and the dielectric thickness they help create after lamination.

Glass Style	General Character	Typical PCB Use
7628	Thick, heavy weave	Standard FR-4, thicker dielectric sections
2116	Medium thickness	General multilayer PCB
1080	Thin, higher resin proportion	Thin multilayer and HDI structures
106 / 1037	Very thin	HDI and thin dielectric layers
Spread Glass	More uniform fiber distribution	High-speed, low-skew designs

7628 is useful when the stackup needs thickness quickly, while 2116 provides a more moderate dielectric build. 1080 and 106-class fabrics are better suited to thinner layer spacing.

No single glass style is automatically better. A production stackup often combines several styles to balance total thickness, resin flow, impedance, mechanical strength, and manufacturing yield.

How Do 7628 Fiberglass Cloth Price Changes Affect PCB Cost?

A 7628 price increase does not translate into the same percentage increase for every PCB because glass cloth is only one part of the laminate, prepreg, and total PCB manufacturing cost.

The effect is more direct on products that use substantial amounts of conventional FR-4 and thick dielectric structures, including:

Industrial multilayer PCBs
Power supply boards
Automotive control boards
Appliance electronics
LED and charging products
Standard thick FR-4 assemblies

The final PCB cost also depends on the number of 7628 plies, board layer count, total FR-4 thickness, laminate and prepreg supplier, resin system, material inventory, panel utilization, and order volume.

Ultra-thin HDI or advanced high-speed boards may rely more heavily on other glass styles and specialized laminates, so their cost response to 7628 alone can be smaller.

How Should Engineers Decide Whether to Use 7628?

7628 is a good candidate when the PCB needs conventional FR-4 processing and relatively large dielectric thickness without excessive stackup complexity.

Consider 7628 when:

A larger dielectric build is required
Overall PCB thickness or stiffness matters
Routing density is moderate
Through-hole spacing is adequate
Severe differential-skew control is not required
The material has already been qualified by the fabricator

Consider thinner or more uniform glass constructions when:

Very thin dielectric layers are required
Microvia density is high
Hole spacing creates CAF concerns
High-speed differential skew is critical
Millimeter-wave routing is present
Impedance uniformity requires tighter material control

At EBest Circuit, glass style is reviewed together with resin content, finished dielectric thickness, copper weight, via geometry, impedance requirements, and PCB manufacturing capability during stackup and DFM review.

FAQ About 7628 Fiberglass Cloth

1. Is 7628 fiberglass cloth used in FR-4 PCB?
Yes. 7628 is a common E-glass reinforcement style used in FR-4 laminate and prepreg constructions.

2. How thick is 7628 fiberglass cloth?
Dry 7628 fabric is typically about 0.17 mm thick. A resin-impregnated 7628 prepreg may be around 0.20–0.22 mm, depending on resin content and material system.

3. Is 7628 thicker than 2116?
Yes. In common PCB prepreg constructions, 7628 produces significantly more dielectric thickness per ply than 2116.

4. Can 7628 be used in HDI PCB?
Yes, but it is usually not the preferred material for very thin HDI dielectric layers or fine-pitch microvia regions. It may still be used elsewhere in the same multilayer stackup.

5. Does 7628 increase CAF risk?
Not automatically. However, 7628 requires closer evaluation in high-CAF designs with tight hole spacing because its heavy weave is more difficult to fully wet with resin.

6. Does a rise in 7628 fiberglass cloth price increase all PCB prices?
No. The effect depends on how much 7628-based laminate or prepreg the PCB stackup uses, along with layer count, board thickness, resin system, supplier pricing, and order volume.

Need Help Reviewing a 7628-Based PCB Stackup?

Using 7628 is mainly a stackup decision. Its suitability depends on required dielectric thickness, via spacing, resin system, signal speed, total board thickness, and the location of critical routing layers.

EBest Circuit can review FR-4 stackups, prepreg selection, controlled impedance, via geometry, CAF-sensitive spacing, and manufacturing requirements before fabrication. For a new PCB project, send your Gerber files, stackup requirements, material specification, and target board thickness to sales@bestpcbs.com for DFM review.

Positive vs Negative Photoresist: What’s the Difference and Which Should You Use?

September 16th, 2026

Positive vs negative photoresist differs in what happens to the exposed coating during development. In a positive resist, the exposed area becomes soluble and is removed. In a negative resist, exposure hardens or crosslinks the material, so the exposed area remains.

That reversal changes mask polarity, but tone alone does not decide which resist will print the smallest feature or survive the next process. Choose by required line and space, film thickness, exposure system, substrate, developer, etching or plating chemistry, and stripping method.

Positive vs negative photoresist, coated wafer, photomask and PCB coupon at a photolithography workstation

What Are Positive and Negative Photoresists?

Positive and negative are imaging tones: they identify which part of a light-sensitive coating remains after development. The terms do not indicate electrical polarity, film color, or product quality.

In a positive photoresist, the developer removes the areas that received enough exposure. The unexposed coating stays on the substrate and protects the material below. This creates a resist image that follows the dark regions of the photomask.

In a negative photoresist, exposure makes the illuminated areas resistant to the developer. The unexposed coating is washed away, so the remaining resist follows the clear regions of the mask. That image may act as an etch barrier, a plating mold, a temporary process film, or a permanent microstructure, depending on the product.

How Do Positive and Negative Photoresists Work?

Both materials convert an optical image into a patterned coating, but exposure changes their solubility in opposite directions. The full imaging sequence is coat or laminate, expose through a mask or direct-imaging system, and develop.

Positive resist chemistry is formulated so that sufficient exposure makes the illuminated polymer easier for the specified developer to dissolve. Development therefore clears the exposed regions and leaves the unexposed film. The printed edge depends on how sharply the chemistry changes from insoluble to soluble across the exposure boundary.

Negative resist chemistry polymerizes, crosslinks, or otherwise hardens where it receives sufficient light. Development removes the unexposed regions and leaves the exposed network. Crosslink density affects sidewall shape, adhesion, chemical resistance, and how readily the film can be stripped later.

Exposure dose must match the resist thickness and light source. Too little energy may leave a positive resist incompletely cleared or a negative resist insufficiently crosslinked. Excess energy can widen or narrow the printed feature by moving the effective image boundary.

Positive vs Negative Photoresist: What Are the Main Differences?

The central difference is simple: exposed positive resist is removed, while exposed negative resist remains. This positive vs negative photoresist comparison shows how that reversal affects the image and the processes each tone commonly serves.

Property	Positive Resist	Negative Resist
Exposed area	Removed	Remains
Unexposed area	Remains	Removed
Image formation	Exposure opens the coating	Exposure hardens the coating
Fine features	Often favored for high-resolution thin-film imaging	Capable when the material and process are optimized
Film thickness	Common in thinner coatings	Widely available as thick liquid or dry film
Adhesion	Controlled by formulation and surface preparation	Often strong after crosslinking
Typical uses	Semiconductors, microfabrication, selected PCB processes	PCB dry film, pattern plating, tenting, thick microstructures
Stripping	Often easier with the specified remover	May require a stronger or tightly controlled strip process

How Does Photoresist Type Affect Mask Polarity?

The same clear mask area produces opposite developed results. A clear area lets light reach the resist; whether that location opens or stays protected depends on the resist tone.

Positive vs negative photoresist, glass photomask above positive and negative developed copper coupons

Positive resist: A clear mask area exposes the resist; the developer removes that coating and opens the substrate at the same location.
Negative resist: A clear mask area exposes and hardens the resist, so the substrate remains protected at the same location.

Start with the final surface that must be open for etching, plating, deposition, or another operation. Trace that area backward through development and exposure to determine whether it should be clear or opaque on the mask. If a process changes from positive to negative tone, the image logic normally has to be inverted; reusing the old artwork can reverse protected and open areas.

Which Photoresist Offers Better Resolution and Fine-Line Performance?

Positive photoresist is often associated with finer imaging, but resist tone does not set the minimum feature size by itself. A qualified negative material can outperform a poorly matched positive process, especially when the film, exposure tool, developer, and substrate preparation were developed as one system.

Positive resists can produce steep profiles because the exposed material dissolves rather than forming a crosslinked network that may swell during development. This behavior is useful in thin-film semiconductor and microfabrication processes. It does not mean every positive formulation is suitable for every wavelength, thickness, or substrate.

For an actual line-and-space target, compare these inputs:

Resist thickness: Thicker films are harder to expose uniformly through their depth and can reduce aspect-ratio margin.
Exposure wavelength and dose: The resist must absorb and react correctly at the tool’s wavelength, with enough latitude to hold the intended edge.
Imaging geometry: Mask contact, collimation, direct-imaging focus, registration, and scattered light alter the printed feature.
Development: Developer type, concentration, temperature, spray pressure, and dwell time affect clearing, swelling, and sidewall loss.
Substrate condition: Surface roughness, oxide, contamination, and adhesion treatment change both image integrity and downstream yield.

Use the supplier’s resolution data only when its test thickness, exposure method, and process conditions are comparable to yours. For PCB work, the finished copper line after etching or plating matters more than the resist image alone.

How Do Positive and Negative Photoresists Compare in Thickness, Adhesion, and Durability?

Negative resists are often selected when the patterned film must be thick, mechanically robust, or resistant to prolonged chemical processing. Exposure builds a crosslinked structure that can hold tall features, bridge holes in a tenting process, or remain intact during plating.

Positive resists are widely used as thinner liquid coatings where clean development and fine profile control are priorities. Their adhesion and chemical endurance still depend on the formulation, bake sequence, surface preparation, and downstream chemistry. A thin positive film may be entirely suitable for a short etch but poorly matched to a long plating cycle.

For thick films: Check whether the resist can be exposed through its full depth without a weak base or distorted sidewall.
For adhesion: Match the resist to copper, silicon, glass, ceramic, or the actual substrate, then verify cleaning and bake conditions.
For chemical durability: Compare the specified etchant, plating bath, cleaning steps, temperature, and dwell time with the material data.
For stripping: Confirm that the hardened image can be removed without attacking the plated metal, substrate, or permanent coating that must remain.

Where Are Positive and Negative Photoresists Commonly Used?

Positive resists are common in fine-pattern thin-film work, while negative resists are common where the image must be thick or durable.

Positive photoresist applications include semiconductor lithography, microfabrication, lift-off processes using a suitable profile, photomask production, presensitized prototype PCBs, and selected liquid-resist PCB processes. These applications often value clean feature definition and predictable removal of the exposed region.

Negative photoresist applications include PCB dry-film imaging, pattern plating, hole tenting, thick electroforming molds, MEMS structures, and permanent epoxy-based features such as those made with SU-8. These processes often need film strength, thickness, adhesion, or resistance to later chemistry.

The same application category can use either tone when materials and equipment differ. If the existing line already meets the finished feature and reliability target, changing tone means reworking the mask logic, developer, exposure window, and stripping route.

Which Photoresist Is Commonly Used in PCB Manufacturing?

Negative-working dry film is widely used for commercial PCB imaging because it laminates uniformly, can tent selected holes, and forms a durable image for etching or pattern plating. Direct imaging and phototool exposure can both be used when the film is designed for the relevant wavelength and process.

Positive vs negative photoresist, blue dry film laminated onto a copper PCB production panel

Positive photoresist also has a place in PCB production. Positive presensitized boards are familiar in prototype and educational work, and positive liquid resists may be used in specialized or established imaging lines. A shop may also use different resist systems for inner layers, outer-layer pattern plating, solder mask, or non-PCB microfabrication, so “PCB photoresist” is not one universal chemistry.

For a PCB order, the customer usually does not need to prescribe resist tone. The useful inputs are finished copper thickness, minimum line and space, annular-ring and registration requirements, via structure, plating build, and surface finish. The fabricator can then choose a qualified imaging route that meets the finished-board drawing.

How Do Etching and Plating Requirements Affect Photoresist Selection?

Etching and pattern plating load the resist in different ways, so the downstream operation can decide which product is suitable even when both tones can print the artwork.

For an etch resist, the film must adhere through cleaning and etchant exposure, protect the copper or substrate without pinholes, and preserve the intended edge as material is removed beside it. Film thickness, sidewall shape, etchant resistance, and stripping after etch all affect the finished line width.

For pattern plating, the developed openings act as a mold. The resist must tolerate the plating chemistry and current distribution, remain bonded during the cycle, and provide enough thickness for the plated build without excessive mushrooming over the resist edge. Hole tenting or selective openings may further favor a robust dry film.

Specify the finished feature and downstream chemistry first. Then compare resist compatibility, required thickness, opening profile, adhesion, maximum process time, and removal method. This prevents a material that images cleanly from failing later in the line.

How Should You Choose Between Positive and Negative Photoresist?

Choose the resist that can produce the required finished feature within your existing exposure, development, and downstream process. Tone is one input; the qualified material system is the decision.

Consider positive resist for a thin-film process that prioritizes fine feature definition, uses a compatible positive-tone mask, and already has controlled coating, exposure, development, and stripping conditions.
Consider negative resist when the process needs a thicker or tougher image, dry-film lamination, hole tenting, pattern plating, prolonged chemical resistance, or a permanent crosslinked structure.
Keep the existing qualified tone when it already meets the finished geometry and reliability requirement. Changing tone also changes mask logic, process chemistry, exposure latitude, and verification work.

Make the decision from measurable requirements: minimum line and space, resist thickness, substrate topography, exposure wavelength, available dose window, developer, etchant or plating bath, stripping limit, throughput, and defect tolerance. If two candidates remain, compare them on the actual substrate at the intended thickness and judge the developed image and finished feature, not the brochure category.

What Should You Check Before Selecting a Photoresist Material?

A tone choice becomes a usable material choice only when the product matches the equipment, substrate, chemistry, and finished feature. Check the following items on the current technical data sheet and process specification:

Tone and format: Positive or negative; liquid, electrodeposited, or dry film; temporary or permanent.
Coating thickness: Nominal and working range after coating, lamination, bake, exposure, and development.
Exposure compatibility: Supported wavelength, recommended dose range, photospeed, and the capability of the mask aligner or direct-imaging tool.
Development: Developer chemistry, concentration, temperature, time, rinse, and the observable clearing endpoint.
Thermal steps: Soft bake, post-exposure bake, hard bake, and allowable substrate temperature.
Substrate and adhesion: Approved surface materials, cleaning method, roughness, adhesion promoter, and topography limits.
Downstream resistance: Compatibility with the actual etchant, plating bath, cleaner, solvent, and process duration.
Stripping: Specified remover, temperature, time, residue risk, and compatibility with the finished metal or device.
Storage and handling: Shelf life, refrigeration or humidity limits, yellow-room requirements, and equilibration before use.

Before releasing a full wafer lot or PCB panel, expose and develop a representative coupon using the intended thickness, substrate, artwork, and equipment. Inspect clearing, feature width, sidewalls, adhesion, and the result after the relevant etch or plating step. Freeze the production settings only after the coupon meets the finished-feature requirement.

FAQs About Positive vs Negative Photoresist

Q1: Is positive or negative photoresist better?

A1: Neither tone is better for every process. Positive resist is often chosen for thin, fine-feature imaging; negative resist is often chosen for thicker, durable films. The correct material must match the exposure tool, substrate, developer, downstream chemistry, and finished geometry.

Q2: Which photoresist is better for fine features?

A2: Positive resist is common in high-resolution thin-film lithography, but a modern negative resist can also resolve fine features. Compare data and test results at the required thickness and wavelength rather than selecting by tone alone.

Q3: Is PCB dry film photoresist positive or negative?

A3: Most common PCB imaging dry films are negative-working: exposed areas polymerize and remain after development. Confirm the exact product because specialized materials may use a different chemistry.

Q4: Is SU-8 a positive or negative photoresist?

A4: Standard SU-8 is an epoxy-based negative photoresist. Exposed regions crosslink and remain, which makes the material useful for thick, high-aspect-ratio and permanent microstructures.

Q5: Do positive and negative photoresists use the same developer?

A5: Not necessarily. Developer chemistry is product-specific; some systems are aqueous, while others use organic solvents or proprietary formulations. Use the developer and concentration stated for the exact resist.

Q6: Do you need to invert the mask when changing photoresist type?

A6: Usually yes, if the final protected and open areas must remain the same. Positive and negative tones respond oppositely under the same clear mask area, so confirm the mask polarity with a small exposure before production.

Q7: Can negative photoresist achieve fine lines?

A7: Yes. Fine-line performance depends on the specific material, film thickness, exposure optics, dose, development, surface condition, and the following etch or plating process. Negative-working dry films are used for fine PCB imaging when the complete process is qualified.

Q8: Which photoresist is easier to strip?

A8: Positive resists are often easier to remove because they do not form the same heavily crosslinked network, but removal still depends on the formulation and bake history. Check that the specified stripper will not damage the substrate or plated metal.

Q9: Can positive photoresist be used for PCB manufacturing?

A9: Yes. Positive presensitized boards and selected liquid-resist processes are used in PCB prototyping and specialized production. Commercial volume fabrication commonly uses negative dry film, but equipment and qualified process capability decide the actual route.

Q10: Why is negative dry film common in PCB fabrication?

A10: It can be laminated at a controlled thickness and forms a strong image that suits tenting, etching, and pattern plating. It also integrates well with established phototool and direct-imaging lines.

Positive photoresist removes exposed regions during development, while negative photoresist retains them. That difference changes mask polarity, but it does not by itself determine resolution or manufacturability. Film thickness, exposure conditions, adhesion, downstream chemistry, and stripping requirements decide whether a specific material fits the process.

For PCB production, judge the imaging process by whether it can repeatedly achieve the required line width, spacing, copper thickness, plating structure, and finished-board tolerances. Send your Gerber files, stackup, copper weight, minimum line and space, quantity, target delivery date, and any plating or inspection requirements to sales@bestpcbs.com for a manufacturability review and quotation.

InP Substrate Guide: Types, Applications, Suppliers, Prices, and Supply Risks

September 7th, 2026

Indium phosphide is a key semiconductor material for optical communication, high-speed photonics, infrared detection, and selected RF devices. Demand has also grown with AI data-center infrastructure, where high-speed optical links increasingly rely on InP-based lasers, detectors, and photonic components.

For engineers and buyers, however, choosing an InP substrate is not simply a matter of ordering a 2-inch or 4-inch wafer. Conductivity type, dopant, crystal quality, EPD, orientation, surface condition, and supplier consistency can all affect epitaxial growth and device yield. This guide explains the main types, applications, available sizes, material alternatives, pricing factors, suppliers, and current supply risks.

InP substrate wafers in a semiconductor photonics laboratory

What Is an Indium Phosphide (InP) Substrate?

An InP substrate is a single-crystal wafer made from indium phosphide, a III-V compound semiconductor consisting of indium and phosphorus.

It is mainly used as the crystalline foundation on which additional semiconductor layers are grown. Materials such as InGaAs, InGaAsP, and InAlAs can be deposited on InP to form active device structures for lasers, photodetectors, modulators, HBTs, HEMTs, and photonic integrated circuits.

The terms InP wafer and InP substrate are often used interchangeably, but the manufacturing context matters:

Bare InP substrate: A polished single-crystal wafer before epitaxial growth.
Epi-ready InP substrate: A polished and cleaned wafer prepared for MOCVD or MBE epitaxy.
InP epiwafer: An InP substrate with one or more epitaxial semiconductor layers already grown on it.

This distinction matters in sourcing. A company that grows bulk InP crystals and supplies polished substrates is providing a different product from an epitaxy supplier offering a completed device layer structure.

What Is an InP Substrate Used For?

InP substrates are mainly used where the device requires long-wavelength photonics, high-speed optical conversion, infrared detection, or very high-frequency electronic performance.

InP substrate applications including optical transceivers, laser diodes, photodetectors, photonic ICs, and RF devices

Typical applications include:

Optical transceivers for telecom networks and data centers
DFB and FP laser diodes
Electro-absorption modulated lasers
PIN photodiodes and avalanche photodiodes
Photonic integrated circuits
Optical modulators and amplifiers
Short-wave infrared detectors
LiDAR and optical sensing
HBT and HEMT devices
Millimeter-wave electronics

One of InP’s strongest application areas is optical communication around 1310 nm and 1550 nm. The substrate supports III-V epitaxial systems such as InGaAsP and InAlGaAs that can be engineered for these telecom wavelength bands.

This makes InP particularly useful in laser sources, detectors, and integrated photonic devices used in high-speed optical links. Silicon photonics may handle routing and passive functions in the same module, but active light generation and detection often still rely on III-V materials.

What Types of InP Substrates Are Available?

InP substrates are usually classified by conductivity type and dopant.

Undoped, n-type, p-type, and semi-insulating InP substrate types

InP Substrate Type	Common Dopant	Electrical Behavior	Typical Use
Undoped InP	None	Usually lightly conductive	Epitaxy, research, special structures
n-Type InP	S or Sn	Electron-conducting	Lasers, detectors, optoelectronics
p-Type InP	Zn	Hole-conducting	Selected device structures
Semi-insulating InP	Fe	Very high resistivity	RF, HBT, HEMT and isolated device structures

Semi-insulating InP substrate is especially important for high-frequency electronics. Its high resistivity helps limit unwanted current paths through the substrate and improves isolation between active areas.

Specifying only “n-type” or “semi-insulating” is not enough for production purchasing. The RFQ should also define the required:

Carrier concentration
Resistivity
Mobility, where relevant
Dopant type
Electrical tolerance range

Two wafers sold under the same general category can still have substantially different electrical characteristics.

What Sizes Are InP Substrates Available In?

Commercial InP substrates are commonly available in 2-inch, 3-inch, and 4-inch diameters, while 6-inch InP is becoming more important for higher-volume manufacturing.

Comparison of 2-inch, 3-inch, 4-inch, and 6-inch InP substrate wafer sizes

Nominal Size	Diameter	Typical Use
2 inch	50.8 mm	R&D, legacy production, specialty devices
3 inch	76.2 mm	Established compound-semiconductor production
4 inch	100 mm	Common modern production platform
6 inch	150 mm	Higher-volume and newer manufacturing platforms

Availability varies by supplier. A manufacturer that routinely ships 3- or 4-inch material may not have qualified 6-inch capacity.

Larger wafers can improve production economics because more dies are processed in one batch, but scaling InP crystal growth is difficult. Maintaining low EPD, good flatness, uniform electrical properties, and acceptable yield becomes harder as crystal diameter increases.

For that reason, a 6-inch requirement should be discussed with suppliers early. Do not assume it will have the same lead time, grade availability, or supplier base as 4-inch material.

InP vs GaAs vs Silicon: When Should You Use Each Substrate?

InP is not the best substrate for every semiconductor device. It becomes attractive when its material system provides a performance advantage that is difficult to reproduce with GaAs or silicon.

Selection Factor	InP	GaAs	Silicon
1310/1550 nm photonics	Excellent	Limited	Strong passive platform
Native light generation	Excellent	Excellent in suitable wavelengths	Poor
High-frequency electronics	Excellent	Excellent	Good
Photonic integration	Strong	Application-dependent	Very strong ecosystem
Large wafer availability	Limited	Better than InP	Excellent
Material cost	High	High	Low
Manufacturing scale	Specialized	Mature III-V	Extremely mature

Use InP when the device architecture depends on:

InGaAs-based photodetection
Long-wavelength semiconductor lasers
High-speed InP HBTs
Integrated III-V photonics
Epitaxial structures lattice-matched to InP

GaAs is often more suitable for VCSELs, RF amplifiers, LEDs, and some sensing systems. Silicon remains the preferred choice when low cost, large wafer size, CMOS compatibility, and mature manufacturing are more important than native III-V optical performance.

The material choice should therefore start with device physics rather than wafer price.

How Much Does an InP Substrate Cost?

InP substrate prices vary widely, so there is no reliable single market price.

InP substrate supply and price drivers including wafer diameter, dopant, EPD, supplier capacity, and AI optical demand

Small research-grade wafers may cost hundreds of dollars, while larger production-grade, low-defect, or epi-ready wafers can reach four-figure prices per wafer. During supply shortages, pricing can rise well beyond normal levels.

An InP substrate price quote should therefore be compared against the complete wafer specification and supply terms. The main price drivers include:

Wafer diameter
Conductivity type
Dopant
EPD requirement
Crystal quality
SSP or DSP polishing
Epi-ready finishing
Orientation tolerance
Flatness requirements
Inspection level
Quantity
Supplier capacity

A quotation issued during a shortage may also reflect capacity allocation rather than normal manufacturing cost.

When comparing InP substrate suppliers, send the same specification to each company. Otherwise, a lower price may simply correspond to a higher EPD, wider geometric tolerance, different polishing grade, or less demanding inspection criteria.

Why Are InP Substrates in Short Supply?

The current shortage is largely the result of fast-growing optical demand meeting a relatively concentrated substrate manufacturing base.

Several factors are involved:

AI data-center growth: Faster optical interconnects require more lasers, detectors, and optical transceiver components.
Limited crystal-growth capacity: High-quality InP single-crystal production is difficult to scale quickly.
Supplier concentration: Only a limited number of companies can manufacture qualified production-grade material at volume.
Long qualification cycles: Switching substrate suppliers can require new epitaxy, wafer-fab, reliability, and customer validation.
6-inch transition: Larger-diameter production requires new crystal-growth capability and downstream qualification.
Trade restrictions: Export controls and geographic concentration can create regional availability problems.
Capacity reservation: Large device manufacturers increasingly secure substrate volumes through long-term agreements.

For procurement teams managing InP substrate shortages, the useful response is not simply buying excess inventory. Our overview of critical semiconductor supply-chain materials provides additional context for qualification and continuity planning. Better controls include:

Qualifying a second source
Providing suppliers with realistic demand forecasts
Identifying acceptable alternative grades
Tracking lead-time changes
Reserving capacity for production programs
Requalifying material changes before volume release

Main InP Substrate Companies Globally

The global InP supply chain includes bulk crystal growers, polished substrate manufacturers, epitaxy companies, device fabs, and distributors. They should not be treated as the same type of supplier.

Several established InP substrate companies with documented substrate capabilities include:

Company	Region	InP Capability	Buyer Should Confirm
Sumitomo Electric	Japan	Semi-insulating and conductive InP substrates	Diameter, grade and available capacity
JX Advanced Metals	Japan	Multiple diameters and dopant options	EPD, flatness and capacity allocation
AXT	USA / global manufacturing	Multiple wafer sizes including large-diameter InP	Origin, qualification and availability
Freiberger Compound Materials	Germany	Semiconducting and semi-insulating InP	EPD grade, polish and orientation
IQE / Wafer Technology	UK / USA	InP substrate and epi-ready wafer capability	Bare substrate vs epitaxial scope

This is not a ranking.

A well-known company may still be unsuitable for a specific program if it cannot support the required diameter, dopant, EPD, surface condition, monthly volume, or qualification history.

Buyers should also establish what the company actually controls:

Bulk crystal growth
Wafer slicing
Grinding and polishing
Epi-ready surface preparation
Epitaxial growth
Distribution only

That distinction becomes important when investigating yield problems or controlling future process changes.

How Should You Choose an InP Substrate Supplier?

Start with the released wafer specification rather than the supplier’s standard product catalog.

Checklist for choosing an InP substrate supplier based on diameter, dopant, resistivity, EPD, surface condition, and lead time

A useful RFQ should include three groups of information.

Material requirements

Diameter and thickness
Crystal orientation
Off-cut, if required
Conductivity type
Dopant
Carrier concentration or resistivity
Maximum EPD

Geometry and surface requirements

TTV
Bow
Warp
SSP or DSP
Surface roughness
Epi-ready requirement
Flat or notch
Particle and contamination limits

Quality and supply requirements

Certificate of analysis
Lot traceability
Electrical test data
EPD data
Packaging method
Standard lead time
Monthly capacity
MOQ
Change-notification policy

For production programs, also confirm how the supplier handles changes to crystal-growth equipment, polishing processes, raw materials, manufacturing locations, or inspection methods.

The lowest wafer price is not always the lowest program cost. Stable epitaxy yield, lot-to-lot consistency, controlled changes, and predictable delivery can be more valuable than a small difference in substrate price.

InP Substrate FAQs

1. What does semi-insulating InP mean?

Semi-insulating InP is engineered to have very high electrical resistivity rather than behaving like a normal conductive n-type or p-type semiconductor substrate. Fe compensation is commonly used. The high-resistivity substrate helps isolate active device regions and reduce parasitic electrical paths, making it useful for HBTs, HEMTs, RF devices, and selected integrated circuits.

2. What dopants are commonly used in InP substrates?

Common InP dopants include sulfur and tin for n-type material, zinc for p-type material, and iron for semi-insulating material. Undoped material is also available. The exact dopant should be specified together with the required carrier concentration or resistivity rather than by dopant name alone.

3. What is an epi-ready InP substrate?

An epi-ready InP substrate has been polished, cleaned, inspected, and packaged so its surface is suitable for epitaxial growth. Important controls may include surface roughness, particles, haze, contamination, orientation, and flatness. Epi-ready should still be defined against the supplier’s specification because the term does not establish one universal surface limit.

4. Why is InP more expensive than silicon?

InP is more expensive because crystal growth is more difficult, usable crystal diameter is smaller, material volume is much lower, defect control is more demanding, and the manufacturing ecosystem is far less scaled than silicon. Silicon benefits from enormous 200 mm and 300 mm production infrastructure that InP does not have.

5. How is InP substrate quality measured?

No single measurement defines InP quality. Typical controls include EPD, resistivity or carrier concentration, mobility, crystal orientation, TTV, bow, warp, surface roughness, particle count, contamination, and visual defects. Which parameter deserves the tightest limit depends on the intended epitaxial structure and device process.

6. Can InP substrates be replaced by GaAs?

Sometimes, but not as a direct drop-in replacement. GaAs can replace InP only when the required device structure, wavelength, lattice-matched epitaxial system, and electrical performance can be redesigned around GaAs. For many 1310/1550 nm lasers, InGaAs detectors, and InP-based high-speed photonic devices, changing to GaAs would require a different epitaxial and device architecture rather than simply changing the substrate.

InP substrates provide capabilities that are difficult to reproduce with silicon or GaAs in specific high-speed photonic and electronic applications, but those advantages come with higher material cost, tighter supplier capacity and more demanding qualification requirements. Before purchasing, define the substrate by its diameter, conductivity, dopant, electrical range, EPD, orientation and surface condition, then compare suppliers on both technical consistency and supply continuity.

If your InP-based optical, RF, or semiconductor device is moving into PCB or PCBA integration, EBest Circuit can review the board-level manufacturing requirements, controlled-impedance interfaces, assembly constraints, and production data. Send your Gerber files, BOM, drawings, and project requirements to sales@bestpcbs.com for engineering review and quotation.

Electronic Glass Cloth Price Increase 2026: PCB Cost and Lead-Time Impact

September 2nd, 2026

electronic glass cloth moved from a background laminate input to a visible PCB supply-chain issue in 2026. A June supplier notice reported increases of 30% for E-glass cloth and 15% for FLD2 cloth, while an August 28 notice reproduced by industry media reported a 20% adjustment for thin-cloth prepreg below 7628, versus 10% for FR-4 and the notice’s 7628-and-above prepreg group.

These figures do not mean every PCB quotation rises by the same percentage. They show where material pressure is building. The effect on a finished board depends on the laminate system, glass style, resin content, layer count, panel utilization, supplier stock, yield, order quantity, and required delivery date.

Electronic glass cloth used in FR-4 laminate, prepreg, and multilayer PCB manufacturing

What Is Electronic Glass Cloth in a PCB?

Electronic-grade woven glass fiber fabric is made from fine glass yarn woven into a controlled cloth. Laminate manufacturers combine it with epoxy, polyimide, or another resin system to make rigid cores and prepreg. In an FR-4 construction, the woven reinforcement contributes electrical insulation, dimensional stability, heat resistance, and mechanical strength.

Several terms appear in specifications and searches. They overlap, but they are not always interchangeable:

Electronic glass cloth and electronic-grade glass fiber cloth identify the electronic-material application.
Woven glass fabric and glass fiber cloth describe the textile form more broadly.
Electronic glass fabric is a natural industry variation of the same product category.
The search phrase e glass cloth normally refers to E-glass composition, not every electronic glass material. Low-Dk or low-CTE specialty glass may use a different composition.

Searches such as glass cloth pcb, glass fabric pcb, and fiberglass cloth pcb usually point to this same reinforcement layer inside a copper-clad laminate or prepreg construction. For a broader material overview, see what copper-clad laminate is in a PCB.

Copper foil, prepreg, FR-4 core, and woven glass cloth used in PCB materials

Why Did Electronic Glass Cloth Prices Rise in 2026?

The reported increases were not caused by one isolated factor. Supplier and industry reports point to a combination of glass-yarn cost, energy, transportation, specialized capacity, and demand from AI servers, high-speed switches, semiconductor packages, and other advanced electronics.

The market is also segmented. Standard E-glass, low-Dk glass, low-CTE glass, spread glass, and ultra-thin glass cloth do not share the same production route or availability. A price change for one family must not be presented as a universal increase for every electronic glass product.

What Do the 2026 Supplier Notices Say?

Date	Material Scope	Reported Adjustment	Application Basis
July 1, 2026	FULLTECH E-glass glass fiber cloth	+30%	New orders placed on or after the effective date
July 1, 2026	FULLTECH FLD2 glass fiber cloth	+15%	New orders placed on or after the effective date
August 28, 2026	FR-4, all thicknesses in the reproduced notice	+10%	New orders accepted under the notice
August 28, 2026	PP, 7628 and the notice’s thicker-cloth group	+10%	New orders accepted under the notice
August 28, 2026	PP, the notice’s thin-cloth group below 7628	+20%	New orders accepted under the notice

The August data comes from a supplier letter reproduced by financial and metals-industry media. Buyers should confirm the exact brand, grade, region, currency, order date, and open-PO treatment with their material source. Our separate Kingboard FR-4 and prepreg update explains that notice in more detail.

Reported August 2026 prepreg price adjustments for glass cloth below 7628 and 7628 or above

How Does Glass Cloth Cost Move Through the PCB Supply Chain?

The price signal passes through several commercial and manufacturing stages before it reaches a finished PCB. A glass-yarn producer supplies yarn to a weaving and treatment operation. The resulting electronic cloth is sold to a laminate manufacturer, which impregnates it with resin to make prepreg or combines it with copper foil to make CCL. A PCB factory then consumes specific core and prepreg constructions during lamination.

Pressure can change at each stage:

Glass yarn and weaving: fine-yarn availability, energy, yield, and specialist capacity affect cloth supply.
Laminate production: cloth, resin, copper foil, treatment, and coating costs are combined into a material grade.
PCB fabrication: the board’s panel area, layer count, bond plies, lamination cycles, and scrap allowance determine how much material is consumed.
Customer quotation: stock position, volume, quote validity, test scope, and delivery priority determine the final commercial effect.

This chain also explains why two suppliers may quote different changes for the same Gerber package. One may hold qualified inventory bought before the notice, while another may need to purchase new material immediately. Freight, minimum-order quantities, allocation rules, and the remaining shelf life of prepreg can also change the usable cost basis. The comparison is meaningful only when both quotations use the same stack-up, laminate series, glass construction, copper weights, acceptance criteria, quantity, and delivery basis.

Why Is Thin Glass Cloth Under More Pressure?

Thin glass cloth is not merely a lighter version of 7628. Fine yarn, weaving control, fiber opening or spreading, surface treatment, uniform resin impregnation, and thickness tolerance all influence its suitability for electronic laminates. These requirements can limit interchangeable supply.

IPC glass-style numbers such as 106, 1080, 2116, and 7628 identify different constructions. In general, thinner styles support thinner dielectric openings, while 7628 is a heavier cloth. However, the final pressed thickness and electrical behavior still depend on resin content, ply count, resin system, and the laminate manufacturer’s construction. The August notice’s “below 7628” classification is a commercial grouping in that notice, not a complete engineering rule for every supplier.

Which PCB Types May Feel the Impact First?

Boards that use more specialized, thinner, or tightly controlled dielectric constructions are more exposed to availability and substitution risk:

HDI PCB: thin dielectric build-up layers and microvia reliability depend on a controlled material system.
High-layer-count PCB: many bond plies amplify the effect of prepreg availability, press planning, and material qualification.
Thin PCB: the overall thickness budget leaves less room to replace one glass style with a thicker construction.
High-speed PCB: Dk, Df, resin content, glass weave, and trace geometry must remain aligned with the impedance and loss model.

Not every board in these categories uses the same cloth. For example, a high-speed design may require low-Dk glass rather than standard E-glass. A high-speed PCB design therefore needs material review before any cost-driven stack-up change.

HDI, high-layer-count, thin, and high-speed PCB types affected by glass cloth availability

Does a 20% PP Increase Mean a 20% PCB Price Increase?

No. The reported percentage applies to a material category under a supplier notice. A finished PCB quotation includes many other inputs and operations. The actual effect varies with:

board area, panel utilization, layer count, and bond-ply count;
laminate brand, material family, glass style, resin content, and copper weight;
drilling, lamination cycles, plating, surface finish, testing, and expected yield;
supplier inventory, order quantity, quote validity, and requested lead time.

A small standard double-sided FR-4 board and a 24-layer controlled-impedance board will not absorb the same material-cost change. The more useful question is which line items and stack-up layers changed, not whether one headline percentage can be copied into the finished-board price.

Can a Cheaper Glass Style Be Substituted Safely?

Only after engineering review. Two constructions with similar nominal thickness can have different resin content, Dk, Df, local weave behavior, copper geometry, and lamination performance. A substitution can change impedance, insertion loss, skew, CAF risk, drill behavior, and reliability.

Before approving an alternative, compare at least:

laminate and prepreg manufacturer, series, and approved glass style;
nominal and pressed dielectric thickness, resin content, and ply count;
Dk and Df at the relevant frequency and test method;
Tg, Td, CTE, moisture performance, and CAF requirements;
controlled-impedance geometry and simulation or coupon acceptance criteria.

This is especially important for fine-feature designs. Our UHDI printed circuit board guide shows why material and stack-up decisions must follow the actual geometry and reliability target.

How Can PCB Buyers Reduce Cost and Lead-Time Risk?

Procurement and engineering teams can act before a shortage becomes a schedule problem:

Freeze the electrical and mechanical stack-up early enough for material confirmation.
Separate mandatory material properties from brand preferences that may allow an approved equivalent.
Share realistic prototype and production forecasts so uncommon glass styles can be planned.
Ask whether the quotation is based on current inventory, a new material purchase, or an allocation.
Keep quote validity, open-PO treatment, and delivery assumptions in writing.
Never approve a high-speed or HDI substitution from a price table alone.

FAQ About Electronic Glass Cloth

Is electronic glass cloth the same as fiberglass?

It is a fiberglass textile made for electronic-material use, but the electronic-grade designation adds controls for yarn, weave, thickness, treatment, and performance. General-purpose fiberglass fabric should not be treated as PCB laminate reinforcement.

Is all PCB glass cloth E-glass?

No. E-glass is common, but low-Dk, low-CTE, and other specialty glass compositions are also used. The required material depends on the laminate family and electrical or mechanical target.

Why does glass style matter to impedance?

Glass style changes the resin-to-glass ratio and local dielectric distribution. Together with pressed thickness and copper geometry, those changes affect the impedance and loss model.

Should buyers reserve thin prepreg earlier?

For HDI, high-layer-count, thin, or high-speed designs, early confirmation is sensible when the stack-up relies on a specific glass style or laminate series. The need depends on actual supplier stock and order timing.

How Can EBest Circuit Support Your PCB Material Review?

At EBest Circuit, we review PCB fabrication requirements together with the stack-up, material system, copper weights, impedance targets, quantity, and delivery plan. If a preferred material is under price or supply pressure, we can identify which requirements are fixed and which alternatives still need technical approval.

For a project affected by electronic glass cloth availability, send your Gerber files, stack-up, material brand or grade, board thickness, copper weights, impedance requirements, order quantity, and target delivery date to sales@bestpcbs.com. We will review the material basis before confirming a quotation or proposing a substitution.

Kingboard Price Increase: FR-4 and Prepreg Costs Rise in August 2026

August 31st, 2026

The latest Kingboard price increase concerns the materials used to manufacture PCBs, not an automatic increase in every finished-board quotation. An August 28, 2026 notice reproduced by financial media reports higher FR-4 and prepreg prices for newly accepted orders. For purchasing teams, the next step is to identify the material used in each board and confirm which commercial terms apply.

At EBest Circuit, we help customers review PCB material requirements alongside fabrication needs. This update explains the reported changes, where they enter a multilayer board’s material bill, and what to clarify when a supplier sends a revised quotation.

Kingboard price increase illustrated with copper-clad laminate and prepreg materials

What Changed in the August 28 Notice?

Gelonghui’s August 28 report, carried by Sina Finance, reproduces a notice from Guangdong Kingboard Laminates Trading Co., Ltd. The stated adjustments are:

Material category in the notice	Reported increase
FR-4, all thicknesses	10%
Prepreg: 7628 and the notice’s thicker-cloth category	10%
Prepreg: the notice’s thin-cloth category below 7628	20%

The reproduced letter is dated August 28. We checked its wording against the report, but it was obtained through a media publication, not a direct supplier communication. Confirm the applicable grade and price with your material supplier before changing a purchase order.

When Does the New Pricing Apply?

The notice refers to new orders accepted from its issue date. It does not establish how every distributor will handle existing inventory, previously accepted orders, or an earlier quotation that remains valid.

Before approving a revised board price, ask for three specific confirmations:

Order status: Was the material order already accepted, or does the job still require a new purchase?
Quotation basis: Which material grade, copper weight, sheet size, quantity, currency, and tax basis are being compared?
Validity: How long does the revised quotation remain open, and what event fixes the price?

A finished-PCB purchase order and a laminate manufacturer’s order are different transactions. Do not assume that sending a board PO earlier automatically secures an earlier material price; obtain written confirmation from the party supplying your boards.

Why Are Glass Cloth and Copper Foil Important?

The letter cites rising prices and tighter supply of glass cloth and copper foil. Both are inputs to PCB laminate production; neither is simply an optional accessory that can be removed from a drawing.

A copper-clad laminate combines a dielectric base with copper foil. Prepreg supplies resin-bearing reinforcement between layers during lamination. Their costs enter the material bill through different purchased items and constructions.

The notice alone does not tell us how much either input has risen across the entire market, how long supply pressure will last, or which next adjustment will follow. Those would require separate dated evidence. For a current order, the relevant information is the supplier’s quotation for the exact material being purchased.

PCB Prepreg vs Core: Which Material Is Affected?

The distinction in PCB prepreg vs core matters because a multilayer stackup uses cured laminate and bonding sheets differently. A core is already cured; prepreg starts as resin-impregnated reinforcement that bonds the assembly during pressing.

Cured copper-clad core compared with uncoppered prepreg bonding material

For background on the bonding stage, see our explanation of prepreg in PCB manufacturing. For this price review, identify the actual core and prepreg entries in the approved stackup rather than treating the entire board as a single sheet of FR-4.

When comparing prepreg PCB material, retain the manufacturer’s grade, resin system, glass style, resin content, and number of plies. Two options described simply as “FR-4 prepreg” may not have the same electrical properties or processing behavior. A purchasing description that omits these details can hide a construction change inside an apparently cheaper quotation.

Why Does Prepreg PCB Thickness Need a Construction Check?

Prepreg PCB thickness is not determined by a glass-style number alone. Resin content, the selected construction, and the pressed assembly all matter. Manufacturer data can list more than one thickness or resin-content option for the same glass style.

The notice’s wording around 7628 is a supplier pricing category. It should not be converted into a universal rule that every glass-style code with a smaller numerical value is physically thinner. Match each ordered prepreg item to the supplier’s classification.

Construction also affects PCB prepreg dielectric constant. Isola’s laminate-manufacturing guide explains that glass construction and retained resin content influence dielectric properties. Its material data illustrate why an apparently similar glass designation is not enough to prove equivalence; those Isola values should not be copied into a Kingboard design.

For an impedance-controlled board, changing dielectric spacing or material properties can require a new impedance calculation and an approved stackup revision. Keep the electrical requirement fixed while evaluating the material choice.

Does a 20% Prepreg Increase Mean a 20% PCB Price Increase?

No. A percentage applied to one purchased material does not automatically apply to the total selling price of a finished PCB. The board also includes other materials, fabrication operations, inspection, testing, handling, and commercial terms.

PCB cost categories showing materials, fabrication, testing, and handling without assigning cost shares

A useful calculation starts with the affected material lines, not the total board invoice: multiply each old material-line cost by its applicable adjustment, then add the differences. That estimates the change in those lines only, assuming the same specification, quantity, and purchasing basis.

It still does not determine the final commercial quotation. Inventory purchased at an earlier price, panel utilization, production volume, and other cost changes may affect the outcome. Our copper-clad laminate price guide provides broader background on material-price factors.

If a revised quotation cites the Kingboard price increase, ask which material lines changed and whether the board specification stayed the same. A traceable explanation is more useful than applying a headline percentage to every item.

Which Cost-Saving Changes Need Engineering Approval?

Start with options that preserve the approved design, such as reviewing order quantities or panel utilization with the fabricator. Material substitutions require a separate technical decision; a lower material price does not establish that the replacement will work.

Engineering review of material grade, layer stackup, and copper weight before a PCB substitution

Changing prepreg construction: Review finished dielectric spacing, resin availability around copper features, and electrical requirements.
Changing laminate grade: Compare the relevant thermal and electrical properties and any material restrictions on the drawing.
Reducing copper: Recheck current handling, thermal behavior, and fabrication requirements rather than treating copper weight as a purchasing-only choice.
Changing a qualified build: Agree on required samples, inspection, and customer approval before production release.

Keep the existing approved construction if equivalence has not been demonstrated or the customer does not permit substitutions. Requalification time and scrap risk can outweigh a small purchase-price saving.

How Can We Help You Review a Material-Cost Change?

At EBest Circuit, we provide PCB fabrication and PCBA services with technical support for material and build requirements. We can review your approved stackup and discuss which material choices are fixed, which alternatives may be evaluated, and what information is needed for a current quotation.

Send your Gerber files, stackup, specified laminate grade, copper weight, order quantity, and required delivery date to sales@bestpcbs.com. If you are comparing a revised quote, include the earlier specification and quote date so we can compare the same build. Any proposed material change should be documented and approved before manufacturing.

Panasonic Laminate Price Increase: What PCB Buyers Should Check Before September Shipments

August 31st, 2026

The Panasonic laminate price increase announced on August 6, 2026 takes effect for September 1 shipments on an ex-factory basis. This August 31 update is an execution reminder, not a new price announcement. The change covers several circuit-board material categories, with different rates for general glass-epoxy and low-loss products.

For PCB buyers, the practical questions are which material their approved build uses, when that material ships, and whether a revised quotation still describes the same board. At EBest Circuit, we can review those technical requirements with you before a proposed substitution changes the build.

Panasonic laminate price increase news illustration with PCB laminate and prepreg materials

Which Panasonic PCB Materials Are Included?

Panasonic Industry’s official notice lists the following changes from current material prices:

Material group	Affected products	Increase
General multilayer glass epoxy	Laminate and prepreg	30%
MEGTRON / XPEDION	Laminate and prepreg	15%
LEXCM GX substrate materials	Laminate and prepreg	30%
CEM-3	Glass-composite materials	30%
FCCL	Flexible circuit-board materials	15%

These are Panasonic PCB materials, not replacement control boards for air conditioners or other appliances. Package-substrate materials, flexible materials, and ordinary rigid-board materials should also remain separate entries in a purchasing review. A rate for one category should not be applied to another simply because both are used somewhere in electronics manufacturing.

When Does the September Revision Take Effect?

The stated trigger is shipment from the factory from September 1, 2026. It is not described as a deadline based only on when a customer submits a purchase order.

Timeline separating the August 6 announcement, August 31 order review, and September 1 ex-factory shipments

For a board buyer, the laminate shipment date, PCB production start, and finished-board delivery date are three different milestones. Ask the fabricator which material transaction applies to your order rather than inferring it from your requested PCB delivery date.

Material already allocated: Confirm the allocation, quantity, and applicable quotation in writing.
Material still to be purchased: Obtain a current quote and an expected material shipment date.
Repeat orders or scheduled releases: Check whether each release has its own purchasing and pricing conditions.

A quotation’s validity period is not the same as a stock reservation. If the supplier cannot confirm allocation, do not treat material availability or an earlier price as secured.

Why Is Panasonic Revising Material Prices?

Panasonic cites sustained increases in principal raw materials, together with elevated auxiliary-material, energy, logistics, and other costs. The notice presents the revision as necessary to support continued supply.

That explanation does not provide a PCB-fabricator cost breakdown. A board quotation includes more than the purchased laminate and bonding sheets. The affected material share, processing route, quantities, and contractual terms must be reviewed for the specific order; no finished-PCB price increase can be calculated from the announcement alone.

Nor does a price notice establish that every material grade is unavailable. Treat price, stock allocation, and lead time as separate questions. A higher price is not proof of an earlier delivery slot, and an available sample sheet is not proof of production-volume availability.

What Does This Mean for Panasonic MEGTRON 6 and 7?

Panasonic MEGTRON 6 and Panasonic MEGTRON 7 are material families used in high-performance multilayer boards. They should be identified by the exact laminate and prepreg grades on the approved stackup, not just the family name.

A common percentage adjustment does not make two grades equal in absolute price or technically interchangeable. Their earlier prices, constructions, and processing requirements can differ. A purchasing comparison must retain the grade suffix, copper foil, dielectric construction, panel requirements, and order volume.

For high-speed designs, changing the dielectric system is a signal-integrity decision as well as a cost decision. Channel loss and impedance depend on the board construction and routing, not on the material trade name alone. Our high-speed PCB design guidance explains why the full interconnect needs attention.

If the drawing explicitly specifies a manufacturer and grade, keep that requirement in the quote. Present any alternative as a separate option requiring approval, not as an equivalent silently substituted during purchasing.

What Should You Check in a Panasonic MEGTRON 6 Datasheet?

A Panasonic MEGTRON 6 datasheet is useful for confirming which product a quotation actually refers to. The manufacturer’s documentation distinguishes laminate variants such as R-5775(N), R-5775(K), and R-5775(G), with corresponding R-5670 prepregs. It also identifies typical values and the conditions used to measure them.

Material datasheet review focusing on exact grade, test conditions, and typical values

Exact product: Match the complete grade and suffix, including the associated prepreg.
Electrical data: Compare Dk and Df only with their frequency, method, and sample conditions stated.
Thermal data: Check that the property and test method match the assembly requirement being evaluated.
Copper and construction: Retain the specified foil and dielectric details when comparing transmission performance.

Do not take a typical datasheet result as a guaranteed acceptance limit for every finished board. Define the relevant build and inspection requirements separately. For the role of the bonding material, our PCB prepreg overview provides a useful starting point.

Can a Different Laminate Reduce Cost Without Changing Performance?

Possibly, but that requires evidence for the actual design. A material with a lower quoted sheet price can still require a stackup change, trace-width adjustment, process review, or additional qualification.

Material review followed by stackup review and validation before PCB production

Start by fixing the performance and customer requirements that cannot change. Then compare candidate materials against those requirements, estimate the work needed to approve the change, and obtain written customer acceptance before release.

Our stackup and impedance-control guidance is relevant when dielectric thickness or properties change. Price comparisons should not leave the stackup as an unspecified item to be decided after ordering.

Keeping the existing material may be the better choice when a product is already qualified, the delivery window cannot accommodate validation, or the expected saving is smaller than the change effort. The purpose of a review is to make that tradeoff visible, not to assume that a substitute is always available or worthwhile.

What Should Be Confirmed for September Deliveries?

Ask for a written order confirmation that connects the material, price, and schedule. “Material available” is too broad if the required grade, thickness, copper foil, or quantity is still unresolved.

Approved laminate and prepreg part numbers, plus any permitted alternatives.
The material allocation and expected factory shipment relevant to your job.
The quotation date, validity, and treatment of scheduled releases.
The expected PCB delivery date after material receipt and fabrication.
Who approves a material change and what validation is required.

When discussing the Panasonic laminate price increase internally, keep the supplier’s material notice separate from your project’s board quotation. That gives engineering and purchasing the same documented basis for approval.

How Can EBest Circuit Help With Your Material Review?

At EBest Circuit, we support PCB fabrication and PCBA projects, including multilayer and high-speed board requirements. We can review your specified materials and stackup, clarify which requirements must remain fixed, and discuss alternatives that may merit engineering evaluation.

Email sales@bestpcbs.com with your Gerber files, approved stackup, full laminate and prepreg grades, quantities, and target delivery date. Include any customer restrictions on substitution. We will use those requirements to discuss a current quotation and the review needed before changing the build, without treating a material-price headline as a finished-board price.

BT Substrate Guide: Material, Process, Applications and ABF Comparison

August 25th, 2026

A BT substrate is an organic semiconductor package substrate built with bismaleimide triazine resin laminate. It provides the fine copper interconnection layer between a silicon die and the larger system PCB, especially in BGA, CSP, memory, RF, and other compact packages.

The material name alone does not define performance. Resin grade, reinforcement, copper profile, layer structure, microvia design, finished thickness, surface finish, and package assembly all affect electrical behavior, warpage, and reliability. This guide separates those decisions so engineers and buyers can specify the substrate without treating BT as a universal recipe.

BT Substrate cutaway showing an IC die, copper routing layers, laminate core, microvias, solder balls, and system PCB

What Is a BT Substrate?

A BT substrate is a fabricated organic package substrate whose insulating structure uses bismaleimide triazine resin material.

It sits inside the semiconductor package. The die connects to fine copper features on the top side by wire bonds or flip-chip bumps, while pads or solder balls on the bottom side connect the package to the system board. In other words, the substrate redistributes a very fine die interface into a larger, manufacturable package interface.

Three terms are often mixed together. BT resin is the thermoset chemistry. BT laminate is the cured, reinforced material supplied in sheet or prepreg form. The finished BT resin substrate adds copper circuits, vias, solder mask, surface finish, and dimensional controls for a specific package. It is not simply another name for the motherboard beneath the package.

BT Substrate Material: Resin, Reinforcement, and Copper Structure

BT substrate material normally combines a thermoset BT resin system, reinforcement or fillers, and patterned copper conductors.

The exact formulation is supplier- and grade-specific. A datasheet may report glass-transition behavior, dielectric constant, dissipation factor, coefficient of thermal expansion, moisture absorption, peel strength, and dimensional change. Those values must be compared at the stated frequency, thickness, cure condition, and test method; numbers taken from different grades are not automatically interchangeable.

BT Substrate Material exploded view with copper routing, BT resin core, build-up dielectric, microvias, and solder mask

BT resin core or prepreg: provides insulation, structural support, and thermal stability.
Reinforcement and fillers: influence stiffness, dimensional control, drilling behavior, and thermal expansion.
Copper foil or plated copper: forms signal, power, ground, pads, and vertical interconnections.
Microvias and through connections: link routing layers according to the package architecture.
Solder mask and surface finish: protect conductors and prepare pads for wire bonding, bumps, or solder balls.

Do not approve a material only because the datasheet says “BT.” Approve the exact grade, construction, copper type, thickness, and qualification evidence used for the package.

Why Is BT Resin Used in IC Package Substrates?

BT resin is used because it combines useful thermal, electrical, and mechanical behavior with scalable organic-laminate processing.

Mitsubishi Gas Chemical identifies its BT laminate as a thermoset bismaleimide triazine material developed for chip packaging, with particular emphasis on thermal resistance, electrical properties, structural integrity, and low warpage. The IEEE IRDS packaging tutorial also identifies BT resin as an organic substrate material widely used for BGA and CSP packages.

These strengths matter because a package substrate experiences several stresses at once: fine copper features must stay registered, the package must remain flat through repeated heating and cooling, and the dielectric must preserve insulation and signal behavior. BT is therefore attractive when a conventional low-cost board laminate does not provide enough package-level control, but the design does not require the finest ABF build-up architecture.

BT Substrate vs ABF Substrate

BT and ABF are both organic package-substrate material systems, but they are usually selected for different layer functions and routing densities.

BT commonly appears as a reinforced laminate and is strongly associated with wire-bond BGA, CSP, memory, MEMS, RF, and other mainstream packages. ABF is an unreinforced build-up dielectric designed for fine laser microvias and dense redistribution in advanced flip-chip packages. A complex substrate may use a core material and separate build-up films, so the decision is not always a simple one-material-versus-the-other choice.

BT Substrate vs ABF Substrate comparison showing wire-bond BGA and high-density flip-chip package structures

Comparison	BT substrate	ABF substrate	FR-4 PCB
Primary role	Organic IC package substrate	High-density package build-up structure	System-level printed circuit board
Typical structure	Reinforced BT laminate with copper circuits and vias	Thin build-up dielectric layers with dense laser microvias	Glass-reinforced epoxy laminate with PCB-scale circuitry
Common fit	BGA, CSP, memory, RF, MEMS, and related packages	High-I/O flip-chip, CPU, GPU, ASIC, and advanced computing packages	Board-level interconnection for packaged components
Selection trigger	Package reliability and moderate-to-high routing density	Very fine routing, high I/O count, and multilayer build-up needs	Cost-effective board-level routing within PCB design rules

Choose from the package architecture outward. Die pad pitch, I/O count, escape routing, electrical model, substrate size, warpage target, assembly method, and reliability plan should drive the material system. A broad label such as “high performance” is not enough to select between BT and ABF.

How Does a BT Substrate Differ from an FR-4 PCB?

A BT substrate works at the semiconductor-package level, while an FR-4 PCB connects completed packages and other components at the system level.

The two products may share patterning, drilling, plating, lamination, and inspection concepts, yet the tolerances and interfaces are different. A package substrate must handle die attachment, wire bonding or flip-chip connections, fine redistribution, solder-ball interfaces, and package warpage. A conventional PCB is designed around component land patterns, board stackup, assembly, connectors, and system-level mechanical constraints.

When board-level density becomes difficult but a true package substrate is not required, a substrate-like PCB or advanced HDI PCB may be the correct middle ground. The functional boundary should be settled before requesting minimum line or via dimensions.

BT Substrate Process: How Is It Manufactured?

The BT substrate process builds a controlled multilayer interconnect through material preparation, circuit formation, via creation, copper deposition, lamination, finishing, and inspection.

The route changes with the layer count, conductor-formation method, via architecture, and package type. A representative sequence is:

Material preparation: condition and prepare the specified BT laminate, prepreg, copper, and build-up materials.
Inner circuit formation: coat, expose, develop, and etch or plate the required copper pattern.
Via formation: create mechanical holes or laser microvias, then desmear and prepare the walls.
Metallization: deposit and plate copper to connect the layers and form the conductor thickness.
Layer build-up: align and laminate the multilayer construction; repeat build-up cycles when required.
Outer-layer definition: complete fine routing, pad structures, solder mask, and the specified surface finish.
Profiling and inspection: route or punch the unit and verify electrical, optical, dimensional, and structural requirements.

BT Substrate Process from material preparation and circuit patterning through microvias, copper plating, layer build-up, inspection and test

Process capability cannot be inferred from the resin name. Fine-line geometry, copper adhesion, microvia aspect ratio, layer registration, panel handling, and yield must be reviewed as one construction. The manufacturing data should therefore identify the exact stackup and finished geometry, not only “BT material.”

Which Package Types and Applications Use BT Substrates?

BT substrates are widely used where an organic package needs stable fine routing, compact form, and dependable thermal-cycle behavior.

Wire-bond BGA and CSP: redistributes die connections to an area-array package interface.
Memory packages: supports compact routing and thin package structures.
MEMS and sensor packages: provides controlled mechanical and electrical interconnection around sensitive devices.
RF and communication packages: uses grade-specific dielectric behavior and controlled geometry for signal paths.
LED and optoelectronic packages: supports compact package routing, although thermal architecture must be assessed separately.
Multi-chip and system-in-package designs: can connect several dies or functions when the selected substrate architecture supports the required density.

These are application families, not automatic material approvals. High-power, very-high-frequency, large-body, or ultra-fine-pitch packages may require ABF, ceramic, glass, metal, or another specialized substrate. Use package simulation and reliability targets to confirm the choice.

Which Design Inputs Matter Most for a BT Substrate?

The most important inputs are the complete package interconnect, stackup, material, mechanical, assembly, and test requirements.

Die size, pad map, pad metallurgy, and wire-bond or flip-chip interface.
Package outline, substrate thickness, cavity or stiffener needs, and flatness or warpage limits.
Layer count, copper thickness, line/space, impedance targets, reference planes, and current paths.
Via type, drill or laser diameter, capture pad, filling requirement, stacking rule, and reliability target.
Exact BT material grade, copper type, solder mask, surface finish, and approved alternatives.
Bottom-side pad or solder-ball layout, pitch, coplanarity, and downstream assembly profile.
Panel format, unit orientation, fiducials, coupons, inspection criteria, quantity, and qualification lot plan.

Start with a package drawing and netlist, then align the design database and fabrication notes. If the request only includes a PDF picture and the phrase “BT substrate,” the supplier cannot reliably price or validate the construction.

What Reliability Risks Need Control?

The main risks are warpage, dimensional shift, layer misregistration, via failure, copper adhesion loss, moisture-related damage, and incompatible assembly interfaces.

Risk	Why it matters	Control focus
Warpage	Disturbs die attach, wire bonding, bump contact, or solder-ball coplanarity	Balanced construction, material behavior, copper distribution, cure and thickness control
Registration error	Reduces pad capture and may create opens or shorts	Artwork compensation, alignment strategy, tooling and in-process measurement
Microvia or plated-via failure	Breaks vertical interconnection during assembly or thermal cycling	Geometry, cleaning, plating quality, fill condition and structural inspection
Copper adhesion loss	Can produce lifted pads or delamination	Surface preparation, compatible materials, cure control and peel/reliability evidence
Moisture damage	Raises delamination and package-cracking risk during reflow	Material handling, bake/dry controls, packaging and assembly exposure management

The risk list should become a control plan, not a generic warning. Define measurable acceptance criteria, sampling, coupons, and qualification conditions before production so the inspection method matches the failure mechanism.

How Should a BT Substrate Be Inspected and Qualified?

Qualification should combine electrical, optical, dimensional, structural, and package-level reliability evidence.

Typical checks include automated optical inspection of fine conductors, electrical continuity and isolation testing, dimensional and warpage measurement, copper-thickness verification, microsection analysis, surface-finish inspection, and X-ray or other structural methods where the construction requires them. The final plan depends on package risk and cannot be replaced by one certificate.

Before approving a supplier, compare the drawing revision, material certificate, stackup, process route, inspection report, coupon results, and change-control method. If the package will be wire bonded, flip chipped, molded, or soldered through a demanding reflow cycle, include assembly-side validation rather than accepting the bare substrate alone.

FAQ About BT Substrates

What does BT stand for in substrate material?: BT stands for bismaleimide triazine, the thermoset resin family used in the laminate. The finished substrate also contains copper conductors, vias, protective coatings, and a package-specific surface finish.
Is a BT substrate the same as an IC substrate?: BT substrate is one type of organic IC substrate. IC substrate is the broader product category and may use BT, ABF, epoxy, ceramic, glass, or other material systems depending on the package.
Can BT substrate material values be copied between suppliers?: No. Compare the exact grade and the stated test conditions. Frequency, specimen thickness, cure, copper treatment, reinforcement, and test method can change reported dielectric, thermal, and mechanical values.
Is BT always cheaper than ABF?: No universal price rule applies. Cost depends on material grade, layer structure, feature density, panel utilization, process yield, qualification, volume, and supply conditions. A simpler BT construction may be more economical, but it cannot replace ABF when the routing architecture requires fine build-up layers.
Can a BT substrate use microvias?: Yes, depending on the material construction and fabricator process. Microvia diameter, depth, capture pad, stacking, filling, and reliability requirements must be engineered together rather than copied from a conventional PCB rule set.
What files are needed for a BT substrate review?: Provide the package drawing, layer data or Gerber/ODB++ package, netlist, drill and microvia details, material grade, stackup, pad finish, mechanical tolerances, assembly interface, reliability requirements, quantity, and revision status.

How Can EBest Circuit Support Your BT Substrate and PCB Project?

At EBest Circuit, we support IC substrate, advanced PCB, component sourcing, and PCBA projects from engineering review through production planning.

For a BT package project, we first separate package-substrate requirements from system-board requirements, then review the material, stackup, conductor geometry, vias, finish, inspection plan, assembly interface, quantity, and qualification needs. Our broader IC substrate guide can help your team confirm the correct product category before quotation.

Send your package drawing, fabrication data, stackup, material grade, surface finish, quantity, and reliability requirements to sales@bestpcbs.com. We will review the data, identify items that need engineering confirmation, and help establish a practical substrate-to-PCB production route. You can also return to this BT substrate guide when aligning the package and system-board specifications.

Rogers RO4450F Prepreg: Multilayer PCB Stackup Guide

August 21st, 2026

Rogers RO4450F prepreg is a high-frequency thermoset bonding material, also known as bondply, used to bond dielectric cores, copper layers, and copper foil in multilayer RF and microwave PCBs. It is generally considered when a design uses RO4000-series laminates and requires predictable dielectric spacing, reliable resin filling, controlled impedance, or sequential lamination. It is not a copper-clad core and is usually unnecessary for a simple two-layer board built from a single Rogers core.

EBest Circuit supports Rogers and Rogers/FR-4 hybrid PCB fabrication, including stackup review, controlled impedance, prototypes, and volume production. For an engineering review, send the Gerber files, proposed stackup, Rogers material grade, dielectric thickness, copper weight, target impedance, operating frequency, and quantity to sales@bestpcbs.com.

This guide covers RO4450F thickness, RO4450F Dk, compatible Rogers materials, lamination controls, and the information needed to quote a multilayer RF PCB.

Rogers RO4450F prepreg for multilayer RF and microwave PCB stackups

What Is Rogers RO4450F Prepreg?

Rogers RO4450F is a glass-reinforced, hydrocarbon-ceramic thermoset bonding material in the RO4400 family. Before lamination, it is supplied as an uncured sheet without copper. During pressing, its resin softens, flows around etched copper features, and then cures to join the PCB layers.

After curing, RO4450F performs two functions:

It provides mechanical bonding between the layers.
It becomes part of the electrical dielectric structure.

This second function is especially important in stripline and other controlled-impedance structures. The bondply’s dielectric constant and final pressed thickness influence the distance between a signal trace and its reference plane.

RO4450F should not be described as a complete “RO4450F PCB laminate.” A laminate or core normally contains a cured dielectric with copper on one or both sides. RO4450F is the bonding layer placed between cores, inner layers, or copper foil.

It is appropriate for multilayer RF boards that need RO4000-compatible bonding. A two-layer RO4350B or RO4003C PCB made from one copper-clad core normally does not require bondply because no additional layers need to be laminated.

What Are the Key RO4450F Datasheet Values?

The following values come from the Rogers RO4450F and RO4460G2 bondply datasheet. They are typical material values rather than guaranteed finished-PCB results. Design teams should check the test method and obtain current material documentation before releasing a production stackup.

Property	RO4450F typical value	Design relevance
Material type	High-frequency thermoset bondply	Used between layers, not as a copper-clad core
Standard thickness	0.0040 in / 0.102 mm	Starting point for stackup planning
Thickness tolerance	±0.0006 in	Must be considered in dielectric-height analysis
Dielectric constant	3.52 ± 0.05 at 10 GHz	Influences impedance and signal velocity
Dissipation factor	0.004 at 10 GHz	Contributes to transmission loss
Glass style	1080	Influences resin distribution and local dielectric behavior
Resin content	80%	Supports filling around etched copper
Glass transition temperature	Above 280°C	Supports multiple lamination cycles after full cure
Decomposition temperature	390°C	Indicates thermal decomposition resistance
Thermal conductivity	0.65 W/m·K	Relevant to thermal modeling, but not a heat-spreading solution
CTE, X/Y/Z	19/17/50 ppm/°C	Relevant to dimensional and plated-hole reliability
Moisture absorption	0.04% under D24/23 conditions	Test conditions must be retained when comparing data
Flammability	UL 94 V-0	Suitable for applications requiring this material rating
Lead-free compatibility	Yes	Compatible with lead-free assembly processes

The Dk value of 3.52 should not be entered into every field solver without context. Rogers reports it using a defined IPC test method on raw material. Actual circuit behavior also depends on cured thickness, glass weave, copper roughness, trace geometry, frequency, and the measurement model used by the PCB manufacturer.

The official values and test conditions are available in the Rogers RO4450F bondply datasheet.

How Does RO4450F Work in a Multilayer PCB Stackup?

RO4450F is positioned between etched cores, inner-layer copper surfaces, or copper foil before the multilayer book is pressed. As the temperature rises, the resin reaches a low-viscosity range and flows into spaces around the copper pattern. Continued heat and pressure cure the resin and form a stable dielectric layer.

A typical multilayer construction may contain:

An RO4350B or RO4003C RF core
An etched inner copper layer
One or more plies of RO4450F
A reference plane or copper foil
Additional Rogers or FR-4 layers

The bondply quantity cannot be determined from layer count alone. The manufacturer must examine copper thickness, retained copper percentage, open areas, opposing plane layers, venting features, and the required final dielectric spacing.

RO4450F is most valuable when its improved lateral flow helps fill a challenging copper pattern. However, adding more plies simply to improve filling also increases dielectric thickness. That can change impedance and may require different trace widths, so resin fill and electrical geometry must be reviewed together.

RO4450F multilayer PCB stackup during fabrication layup

Which Rogers Laminates Are Compatible with RO4450F?

Rogers identifies RO4450F as compatible with multilayer constructions using RO4000-series materials, including RO4003C, RO4350B, RO4835, RO4360G2, and RO4000 LoPro laminates.

The most common pairings include:

RO4003C: Often selected for commercial RF and microwave boards where performance and material cost must be balanced.
RO4350B: Suitable for high-frequency multilayer designs that also require a UL 94 V-0-rated core material.
RO4835 and RO4360G2: Used when their specific electrical, thermal, or environmental properties match the application.
RO4000 LoPro: Useful when smoother copper is required to reduce conductor loss at higher frequencies.

Material compatibility does not mean that different cores can be exchanged without modifying the design. Each grade has its own Dk, Df, available thicknesses, copper options, thermal behavior, and processing requirements. Replacing RO4350B with RO4003C, for example, can change impedance and loss even if both can be bonded with RO4450F.

The exact core grade, copper foil type, dielectric thickness, and RO4450F ply count should therefore appear in the controlled stackup rather than being left to the manufacturer after quotation.

What Determines the Pressed Thickness of RO4450F?

Each RO4450F ply bonds to approximately 0.004 inch, or 0.101 mm, when pressed between opposing flat surfaces. In an actual PCB, the thickness contributed by that ply changes because some resin moves into the spaces between copper features.

The main factors are:

Inner-layer copper weight
Percentage of copper remaining after etching
Distribution of copper across the panel
Plane-to-plane or signal-to-plane construction
Number of RO4450F plies
Lamination pressure and thermal profile
Venting and flow patterns outside the functional circuit area

According to Rogers’ processing guidance, RO4450F can fill up to 0.0018 inch of total copper thickness under the stated design conditions. Additional bondply may be required when the filling requirement exceeds approximately 0.002 inch. This is particularly relevant to heavy inner copper and layers with large differences between dense and open copper areas.

A designer should not set controlled impedance from the nominal 4 mil value alone. The PCB manufacturer should calculate or estimate the finished dielectric thickness from the real copper pattern and validated press process. The resulting production stackup can then be returned to the designer for approval before fabrication.

How Does RO4450F Affect Controlled Impedance?

RO4450F affects controlled impedance whenever it forms part of the dielectric path between a signal trace and a reference plane. Both its Dk and its cured thickness influence the impedance result.

For an internal stripline, a thinner-than-expected RO4450F layer moves the trace closer to the reference plane and generally lowers impedance. A thicker layer generally raises impedance when the remaining geometry is unchanged. Trace width, copper thickness, trapezoidal etching, and copper roughness create additional variation.

The impedance review should include:

Target single-ended or differential impedance
Operating frequency or signal rise time
Trace width and spacing
Finished copper thickness
Dielectric height above and below the trace
Dk value and calculation method
Copper foil type and roughness
Manufacturing tolerance
Coupon and test requirements

For RF transmission lines, insertion loss and phase behavior may be just as important as nominal impedance. A prototype should therefore be verified electrically when the stackup is new, the frequency is high, or the acceptable tolerance is narrow.

The drawing should identify the required impedance but allow the fabricator to make controlled trace adjustments after calculating the approved production stackup. Locking the trace geometry while leaving the final material construction undefined creates avoidable quotation delays and engineering questions.

Controlled impedance and pressed dielectric thickness measurement

Can RO4450F Be Used in Rogers and FR-4 Hybrid Stackups?

RO4450F can be used in selected Rogers/FR-4 hybrid multilayer constructions. Rogers states that RO4400 bondply uses FR-4-compatible bonding temperatures and can be combined with low-flow FR-4 bondply in a non-homogeneous stackup using one bonding cycle.

Hybrid construction can reduce material cost by placing Rogers laminates only where RF or high-speed performance requires them. Power, control, or low-speed routing layers may remain on FR-4 if their electrical and thermal requirements permit it.

However, the stackup must account for differences in:

Dielectric constant and dissipation factor
Z-axis and in-plane expansion
Resin flow
Copper adhesion treatment
Glass transition behavior
Moisture response
Finished thickness and warpage
Drilling and desmear requirements

Standard FR-4 prepreg should not automatically replace RO4450F next to an impedance-controlled RF trace. Its dielectric properties and loss may be unsuitable for that transmission-line structure. A hybrid approach works best when the electrical role of every dielectric layer is clearly defined.

Hybrid construction is unnecessary when every layer carries performance-sensitive RF signals or when the savings from replacing a small amount of Rogers material do not justify the additional stackup and process complexity.

Rogers and FR-4 hybrid PCB stackup with RO4450F prepreg

How Does RO4450F Compare with RO4450B and RO4450T?

The correct choice depends primarily on approved legacy construction, resin-filling requirements, and the dielectric thickness options needed by the stackup.

Selection point	RO4450F	RO4450B	RO4450T
Current design role	RO4000-compatible bondply with improved lateral flow	Referenced in earlier RO4400 documentation and existing designs	Spread-glass bondply with more thickness choices
Nominal thickness options	Primarily 0.004 in	Depends on the applicable legacy specification	Approximately 0.0025 to 0.006 in, depending on grade
Dk	3.52 ± 0.05 at 10 GHz	Must be confirmed from the approved specification	Varies with thickness; not one universal value
Main advantage	Better filling for demanding copper patterns	May already be qualified in a legacy product	Greater dielectric-thickness flexibility
Best-fit decision	New designs or difficult fill conditions	Existing validated stackups	High-layer-count designs needing more thickness choices
Substitution approach	Review Dk, thickness, fill, and impedance	Do not replace based only on the family name	Recalculate the stackup for the selected thickness

RO4450F should not replace RO4450B solely because it has better lateral flow. A substitution can change dielectric thickness, Dk, resin volume, impedance, and an already qualified thermal history. For an established product, review the material declaration, approved vendor list, validation records, and change-control requirements first.

RO4450T is more appropriate when the design needs finer control over dielectric spacing. RO4450F remains attractive when a 4 mil bondply fits the electrical geometry and copper filling is the stronger concern.

What Should Fabricators Check During RO4450F Lamination?

RO4450F lamination requires controlled storage, clean handling, suitable inner-layer preparation, and a press profile matched to the actual copper pattern.

Rogers’ processing guide identifies several important controls:

Store the bondply at 10°C to 32°C and protect it from ultraviolet light.
Keep unused material in sealed packaging and follow first-in, first-out control.
Do not store it frozen, refrigerated, or under vacuum.
Keep slip sheets in place during handling and tooling to limit contamination.
Treat inner-layer copper with an appropriate oxide or oxide-alternative process.
Bake prepared inner layers for 15–20 minutes at 115°C to 125°C before layup.
Provide sufficient time in the 100°C to 120°C low-viscosity range for resin filling.
Use vacuum assistance where available and verify the thermal profile with thermocouples.
Maintain traceability for material lots, press cycles, and stackup records.

The published guide describes bonding pressures in the 400–750 psi range and a 175°C curing stage, but these numbers should not be copied into an uncontrolled press recipe. Board thickness, layer count, copper distribution, press equipment, book loading, and lagging materials influence the process window.

Special review is advisable for designs with more than six metal layers, copper of 35 µm or thicker, opposing plane layers, single bondply plies over demanding copper patterns, or bonding to FR-4 cores. The complete Rogers RO4400 processing guide should be used alongside the fabricator’s validated process.

RO4450F prepreg lamination preparation in a PCB factory

What Causes Voids, Delamination, or Impedance Deviation in RO4450F Boards?

Most RO4450F defects originate from a mismatch between the copper structure, available resin, surface condition, and lamination process.

Problem	Likely cause	Practical prevention
Resin voids	Insufficient resin, poor venting, contamination, or inadequate time in the flow window	Review copper topography, venting, ply count, cleanliness, and press profile
Delamination	Weak copper preparation, moisture, contamination, or incomplete cure	Control storage, inner-layer treatment, pre-bake, pressure, and curing records
Local thickness variation	Unbalanced copper or large open areas	Improve copper balance and calculate pressed thickness by layer
Impedance deviation	Incorrect Dk, dielectric height, trace width, or copper-thickness assumptions	Approve the production stackup and use impedance coupons
Registration error	Thin inner layers, unsuitable tooling, or excessive material movement	Match tooling and pinning strategy to the required registration tolerance
PTH reliability problems	Excessive thermal stress, unsuitable hole-wall preparation, or material mismatch	Inspect drilled holes and use a compatible desmear process
Surface discoloration or hardened sheets	Open-package exposure or poor inventory control	Reseal partial packs and discard visibly affected material

Traditional chemical desmear should also be reviewed carefully. Rogers notes that CF4/O2 plasma is preferred when desmear is necessary, while etchback of the core and prepreg layers is not recommended.

Failure prevention is cheaper at stackup approval than after fabrication. A cross-section, impedance report, material certificate, electrical test, and controlled process record provide more useful evidence than relying only on the material name printed on the purchase order.

Which PCB Applications Use RO4450F?

RO4450F is best suited to multilayer boards in which Rogers RO4000-series cores require a compatible bonding layer and the cured bondply affects electrical or mechanical performance.

Common applications include:

Backhaul radio equipment
RF power amplifiers
Small cells and distributed antenna systems
Microwave communication modules
RF filters and signal-distribution boards
Antenna feed networks
Test and measurement equipment
High-speed communication hardware
Mixed-material RF and digital multilayer PCBs

It is particularly useful when an RF design needs buried routing, internal reference planes, transitions between RF and digital sections, or multiple lamination cycles.

RO4450F may be unnecessary for a two-layer RF board, a low-frequency industrial controller, or a cost-sensitive design whose dielectric loss and impedance stability can be met with a suitable FR-4 system. Selecting it without a clear electrical or structural reason adds material cost and supply-chain constraints without creating a corresponding performance benefit.

RF and microwave PCB testing with a vector network analyzer

What Information Is Needed for an RO4450F PCB Quote?

A reliable quotation requires more than the Gerber files and board dimensions. The manufacturer must understand the intended electrical geometry and which parts of the material specification are fixed.

Provide the following information:

Gerber or ODB++ fabrication data
Layer count and proposed stackup
Exact Rogers core grades
RO4450F ply location and quantity, if already defined
Core and dielectric thicknesses
Finished board thickness and tolerance
Base and finished copper weights
Controlled-impedance targets and tolerances
Operating frequency or critical signal requirements
Via types, finished hole sizes, and aspect ratios
Surface finish
Solder mask requirements
Panel or individual board dimensions
Prototype and production quantities
Required inspection reports or impedance data
Applicable acceptance class or customer specification

If the pressed dielectric height is not finalized, identify the electrical constraints rather than inserting an assumed value. The manufacturer can then propose a producible stackup for approval.

EBest Circuit can review Rogers and Rogers/FR-4 hybrid stackups before quotation. Sending the material grade, copper weight, target impedance, operating frequency, and proposed layer arrangement at the beginning reduces engineering questions and helps keep the prototype consistent with later production.

FAQs About Rogers RO4450F Prepreg

Is RO4450F a core or a prepreg?

RO4450F is a prepreg or bondply, not a copper-clad core. It is placed between PCB layers during lamination and becomes a cured dielectric after pressing.

Can RO4450F be laminated with RO4350B or RO4003C?

Yes. Rogers identifies RO4450F as compatible with RO4350B, RO4003C, and several other RO4000-series laminates. The complete stackup still needs review for thickness, impedance, copper filling, and lamination conditions.

What is the standard thickness of RO4450F?

The standard sheet thickness is 0.0040 inch, or approximately 0.102 mm, with a published tolerance of ±0.0006 inch. Its actual contribution to a PCB stackup depends on the copper thickness and distribution surrounding the bondply.

Can RO4450F be used with 1 oz or thicker inner copper?

It can be used with 1 oz copper, but the retained copper pattern and total filling requirement must be reviewed. Rogers recommends additional technical review for copper layers of 35 µm or thicker because a single ply may not provide enough resin for every pattern.

Can RO4450F replace RO4450B directly?

Not without engineering approval. Even materials from the same family can differ in thickness, Dk, availability, flow behavior, and qualification status, so the controlled stackup and impedance calculation must be checked.

Is RO4450F suitable for sequential lamination?

Yes. Its high post-cure Tg allows fully cured RO4400 bondply to withstand additional lamination cycles. The complete thermal history, via structure, and inner-layer preparation still need to match the fabricator’s validated process.

Can standard FR-4 prepreg replace RO4450F?

Standard FR-4 prepreg may be acceptable in non-critical layers, but it is not a direct electrical substitute near an RF transmission line. Differences in Dk, Df, thickness, and thermal behavior can change impedance, loss, and reliability.

RO4450F is a practical bonding material for multilayer RF PCBs when a design uses RO4000-series cores, requires controlled dielectric spacing, or presents demanding copper-fill conditions. Its nominal datasheet values are only the starting point; the final decision should be based on pressed thickness, copper distribution, impedance requirements, layer construction, and a controlled lamination process.

If you are planning a Rogers RO4450F multilayer PCB, send your Gerber files, stackup, material grades, copper weights, impedance targets, operating frequency, and quantity to EBest Circuit at sales@bestpcbs.com for engineering review and quotation.

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