PCB Ground Bounce: Isolate the Glitch Before a Respin

November 9th, 2026

When a quiet FPGA output glitches as neighboring outputs switch, repeat the capture with a shorter probe loop and change the number of switching outputs before changing the board. Then compare three voltages: quiet pin to local ground, local ground to receiver ground, and supply to its own local ground. These readings answer different questions.

Consider a hypothetical 3.3 V FPGA interface where an otherwise low status line appears to cross the receiver’s low-level limit when eight outputs switch. The oscilloscope trace alone cannot tell whether the receiver sees ground motion, a rail dip, ringing on one net or a probe artifact. Here is how to separate those causes and prove the fix.

Oscilloscope probe beside an FPGA development board on a lab bench — Use a short probing connection for a first check at the device. Illustrative rendering, not a production or test record.

what is ground bounce

Ground bounce is a transient change in voltage between two points treated as ground. When several outputs switch, their current may share part of the package and board return path. The voltage across that path can move even though both ends are on the same schematic net. A receiver responds to the signal relative to its own reference, not the zero line printed on an oscilloscope.

For the FPGA example, define driver-side board ground and receiver-side board ground before measuring. The die ground inside the package usually is not accessible. A board-level capture cannot measure it directly. A quiet output can serve as an indicator of switching noise, but it is not a direct reading of the internal ground node.

what causes ground bounce

A first-order inductive estimate is V = L × di/dt. If, hypothetically, 0.75 nH of effective common inductance carries a 0.16 A change in 0.8 ns, the estimate is 0.15 V. At the same current change over 1.6 ns, it is 0.075 V. These are sensitivity estimates, not measured peaks; actual current waveform, distribution, package and interconnect response matter.

The example explains why a lower repetition rate may not fix the glitch. Switching less often does not necessarily slow each edge. Change the number of outputs, programmed slew or load in controlled steps and measure what actually changed. The TI simultaneous-switching application report explains quiet-output test methods and why package and test conditions matter.

simultaneous switching noise

Keep the observed status pin low and use a repeatable trigger. Run the same pattern with one, four and eight outputs changing together; record direction, slew, drive strength, load, I/O bank, test points and terminations. Use the actual receiver or a known equivalent load. Compare both switching directions and capture multiple repetitions, not just a favorable screenshot.

Parameter	Hypothetical comparison	Control
I/O rail	3.3 V nominal	Same receiver and rail setting
Aggressor count	1, 4 and 8	Same bank, load and switching edge
Quiet status pin	Held low	Same pin, node pair and trigger
Programmed slew	Default then one approved slower setting	Keep other settings fixed
Release limit	Receiver input and system timing limits	Evaluate measured waveform and functional errors

oscilloscope probe ground spring

A long ground clip can add loop inductance and pick up a nearby edge. Compare it with a ground spring on a suitable local return point, using the same probe, scope bandwidth and signal node where practical. A repeatable change with the probe arrangement is evidence of measurement sensitivity, not proof that the board has no problem. Document the geometry for any comparison.

Standard bench-scope ground clips are usually connected to protective earth and to one another. Do not clip them to nodes that must remain isolated, and do not defeat protective earth. For a ground-to-ground difference or a small differential voltage on a noisy common-mode level, use a suitable rated differential arrangement within its voltage, bandwidth and common-mode limits.

ground bounce measurements

Start with the status pin against the local return. Then use a differential measurement for the two ground points where practical, and measure the rail directly across nearby power and ground pads. If the issue is receiver behavior, also capture the signal at the receiver relative to receiver ground. Use comparable loading and bandwidth, then correlate the captures against the same switching event.

Node pair	What it measures	What it cannot establish alone
Status pin to driver-side ground	Quiet output deviation near the driver	Actual input waveform at the receiver
Driver ground to receiver ground	Local board-reference movement	Internal package ground motion
I/O supply to its local ground	Local supply excursion	Noise between two board ground points
Receiver pin to receiver ground	Actual receiver input margin	Which source created the excursion

Populated FPGA evaluation PCB with bench test leads near the logic device — Record the physical location and reference node for every capture. Illustrative rendering, not a production or test record.

simultaneous switching noise analysis

If the anomaly shrinks mainly when the probe loop changes, fix the setup and retest. If reference movement grows with output count and the receiver trace moves with it, investigate shared return and package/I/O choices. If the rail falls relative to its own return and the timing follows the rail disturbance, investigate the power delivery path. If one net rings while other measurements stay quiet, evaluate that net’s termination and discontinuities.

These are competing hypotheses, not mutually exclusive labels. Compare a known-good capture and change one variable at a time. Use the PCB power integrity guide when rail measurements point to a supply problem rather than a moving signal reference.

decoupling capacitor placement

Move or revise decoupling when the power-to-local-ground capture supports a supply-loop issue. A long neck or remote via pair can make a nearby-looking capacitor electrically far away at fast edges. Check the loop through package power, board vias, capacitor and reference return. Adding more capacitance does not bypass a broken return path and can change the PDN response.

If the rail is in budget and the receiver reference moves, compare a slower supported output setting or bank redistribution before changing the capacitor count. The trade-off is timing or pin-planning effort. A layout change to repair a shared return costs a new build but may be needed if configuration changes do not provide enough margin.

pcb ground plane rules

Trace the return path near the offending I/O bank and at every layer transition. Check the reference plane for voids or splits, nearby return vias, connectors and narrow ground necks. A layout correction cannot remove every package-internal effect; follow the device documentation for bank assignments and permitted switching conditions. See the via stitching guide for board return transitions.

Release the fix only when the worst approved switching pattern stays inside the receiver’s guaranteed input and timing limits with the agreed margin across required corners and no functional errors in the agreed test. Save the setup photo, revision, test nodes, I/O configuration, waveform and error counts. A cleaner screenshot at one temperature is not a release criterion.

FAQ

Can a long scope ground lead create a false ground-bounce trace?

Yes. A long loop can pick up nearby fields and produce ringing with the probe input. Recheck at the same signal point using a short local reference and a suitable probe. If the shape changes materially, record that effect before interpreting amplitude or using the original capture to justify a layout change.

Is ground bounce the same as supply droop?

No. Ground bounce compares reference points; supply droop is a drop in a rail relative to its own local ground. Both can occur during the same switching event. Measure both quantities separately and then confirm the voltage actually presented to the receiver rather than trying to infer it from a remote rail test point.

Why does the low output move if it never toggles?

A quiet low output can show switching noise because its output structure references a return path used by active outputs. That response may also include coupling or measurement artifacts. Keep the quiet output loaded as intended and compare how the disturbance changes with switching count, direction, probe setup and chosen reference.

Does slowing the clock eliminate ground bounce?

Not necessarily. A lower clock can reduce how often the event occurs, but each edge may still be fast and the same outputs may switch together. If the device permits it, compare output slew or switching alignment while checking timing. Keep the receiver load and trigger fixed for a meaningful comparison.

Should I add a larger decoupling capacitor first?

Not without rail evidence. A larger capacitor may help a slower supply excursion yet do little for a high-inductance local loop or a shared ground path. Measure across local power and ground, then evaluate placement, via geometry and impedance. Verify that a changed capacitor does not create another problem in the measured band.

Is ground bounce always worse on a two-layer PCB?

No. Package behavior, edge rate, load, stackup, routing and return geometry all matter. A second layer with a continuous usable reference can be better than several badly interrupted planes. Inspect the actual signal and return paths and confirm with a controlled measurement; layer count alone cannot qualify the interface.

Can I use two passive probes to measure between grounds?

Only with a safe setup and understood bandwidth, probe matching and common-mode error. Ordinary bench-scope ground clips are generally connected together through earth, so placing them on different nodes can disturb or short the circuit. Prefer a suitable rated differential method when that connection or accuracy is a concern.

What waveform proves the fix worked?

Measure the receiver pin against its own reference during the agreed worst-case switching pattern. Use device-specific guaranteed input levels and timing requirements, including the project’s required margin. Repeat at the necessary operating conditions and record functional errors, not just peak voltage; keep the probe setup fixed between baseline and revised captures.

Technical References

Request a Fabrication Review

For a Best Technology PCB stackup or layout review, send the board revision, return-path layout, I/O bank and switching pattern, probe reference points, and a failing and known-good capture. Include the receiver limits and the exact verification condition.

Thermal Via Solder Wicking: Protect the QFN Pad Joint

November 9th, 2026

Thermal via solder wicking happens when molten solder enters a via opening connected to a package’s exposed land. On a power QFN, that can reduce solder remaining under the package or leave solder on the opposite side. Prevent it by deciding together which vias remain open, where paste is printed and what the assembly inspection must confirm.

Do not remove thermal vias just to make the solder process easier. Compare the via treatment and stencil pattern against the package guidance, electrical connection, thermal target and fabrication capability, then verify the assembled joint on representative hardware.

Unpopulated PCB land with several plated via openings — Via positions under a stencil aperture change how exposed openings interact with the paste. AI-generated illustration; not a production or test record.

thermal via solder wicking

An open, wettable via inside the pasted land creates a path for solder during reflow. The amount that enters depends on the opening, plating and wetting, available solder and process conditions. It is not enough to count vias or compute their empty volume. TI’s PowerPAD application report discusses controlling hole size and stencil placement for the packages it covers.

Check the actual joint for loss of solder and the reverse side for protrusion or deposits. Do not label every exposed-pad void as wicking; outgassing and paste or reflow behavior can also contribute.

thermal pad via design

Design the thermal and assembly paths as one set of requirements. The exposed pad may have an electrical connection as well as a thermal role; check its required net in the device datasheet. Draw the via array, finished hole openings, paste windows and mask openings on the same coordinate basis so both suppliers can review them.

Parameter	Specify or verify
Finished hole	Diameter and location
Via treatment	Open, tented or capped
Paste windows	Size and alignment
Thermal path	Net, planes and copper
Evidence	X-ray and thermal check

thermal vias size and spacing

Use the exact package recommendation and fabricator capability, not a universal hole diameter or pitch. Smaller openings may limit the solder available to flow into a barrel, but hole size, plating and pitch also affect the heat path and manufacturing yield. In a solder-risk review, ask where each opening lands relative to the stencil windows and what registration margin remains.

The thermal via design overview covers the separate heat-flow and resistance question. This article focuses on deciding which openings can safely remain beneath the soldered land.

should thermal vias be tented

Tenting is an option only if the selected side and mask process are suitable for the package and assembly route. A mask film spanning an opening is not a metal cap. Top-side tenting can affect the wettable pad area; reverse-side tenting leaves a top-side opening unless the stack or process specifies otherwise.

Ask whether the supplier can maintain the requested tent through fabrication and reflow at the finished hole size. Compare this with paste windows that avoid open vias, rather than treating tenting as a universal remedy.

thermal via filling

Specify what “filled” means before comparing quotes. A resin-filled via with a metal cap presents a different top surface from an open plated hole; a tented or merely plugged hole is not automatically planar or capped. A nonconductive fill does not remove the existing plated copper path, but it should not be modeled as a solid copper cylinder.

Option	Top surface	Check before release
Open plated via	Opening exposed	Paste clearance
Mask tent	Mask film, if intact	Side and coverage
Filled and capped	Plated surface	Flatness and cap integrity

QFN-style component underside and a power PCB sample — Use the exact package drawing when setting the land and stencil geometry. AI-generated illustration; not a production or test record.

via in pad plated over

Filled and plated-over via-in-pad can be useful when an uninterrupted solderable land is needed. Confirm the fill, cap plating, finished planarity and inspection evidence rather than approving a quote based only on “VIPPO.” See the via-in-pad plated-over process guide for manufacturing details.

Compare the extra process requirements with an open-hole approach that positions stencil windows away from the vias. Both options need assembly verification. Capping addresses the open-hole path but does not remove every possible cause of voiding.

qfn ground pad stencil design

Segmenting the paste area can help the assembler control deposit distribution and avoid some open holes. Use the package and assembly process recommendations; the stencil thickness and pattern must also suit the peripheral joints. TI’s QFN and SON attachment guidance discusses exposed-pad stencil options and X-ray evaluation.

For a drawing check only, four 1.2 mm square windows on a 3.0 mm square exposed land occupy 5.76 mm² of the 9.00 mm² land, or 64% area. With a 0.10 mm stencil, their theoretical aperture volume is 0.576 mm³. Neither value is a recommended target or a prediction of deposited solder; transfer efficiency and reflow change the result. Inspect the actual printed pattern before treating the layout as qualified.

qfn solder void

Look at the void pattern, remaining joint coverage and any solder on the reverse side together. A two-dimensional X-ray can help locate voids, but it does not by itself prove how a void formed or how much solder entered a specific via. Compare the image with the via locations, stencil layout and process records.

Before approving the design, agree the package-specific acceptance criteria with the assembly team. If the cause is still unclear, choose targeted cross-sections or another agreed inspection. Check the assembled board’s temperature under representative power and ambient conditions; a neat-looking X-ray is not a thermal qualification.

FAQ

Does every open thermal via wick solder?

No. The via and land must interact with molten solder under the actual process conditions. The risk depends on wetting, hole geometry, paste placement and reflow. Inspect both sides of representative assemblies and check the joint before treating a given arrangement as safe.

Is tenting on the bottom the same as a filled and capped via?

No. A mask tent can cover one opening but does not create a plated, planar top land. A filled and capped via uses a different fabrication sequence. Ask for the treatment and inspection details in the fabrication drawing instead of relying on an abbreviated label.

Can I simply reduce the amount of paste to stop wicking?

Reducing paste everywhere can leave an insufficient joint even if less solder travels down the hole. First review where paste overlaps the openings and what the package guidance calls for. Use measured paste deposits and assembled-joint evidence rather than adjusting total paste area alone.

Why are there solder deposits on the opposite side of the board?

An open via connected to the land can be a route for solder during reflow, but other solder processes can also leave deposits. Correlate their locations with the via map and record the assembly sequence. Inspect the top joint rather than assuming the reverse deposit is harmless.

Can a large void prove the exposed pad is not soldered?

A single X-ray view can show a projected void, not the full thickness or shape of a joint. Compare the image with the agreed criteria and inspect the location relative to the pad and vias. Use a suitable follow-up method if the diagnosis affects acceptance.

Will resin-filled vias provide the same thermal result as copper-filled vias?

Do not assume that they will. The barrel, fill, cap and connected planes contribute differently to heat flow. Use the actual cross-section and material properties in a thermal model, then confirm the assembled board when the temperature margin is small.

What must I tell the fabricator before selecting a via treatment?

Provide the package drawing, exposed land and via locations, finished hole sizes, affected sides and required surface condition. Also identify which features must be inspected and whether the assembler expects a flat solderable land. Get the treatment description accepted before releasing the files.

Should I compare a modified stencil using the same assembly process?

Yes, when practical. Keep the package, board, paste and reflow conditions comparable so changes are attributable to the stencil trial. Record print results, joint images and thermal checks together. If several inputs change at once, do not attribute the result to one adjustment alone.

Discuss Your Project

Send Best Technology the device drawing, pad and via layout, finished hole sizes and preferred treatment. Include the stencil and inspection requirements if they are already agreed. Contact sales@bestpcbs.com.

PCB Trace Delay

November 9th, 2026

PCB propagation delay is the one-way time a signal takes to travel along a trace. For an initial estimate, multiply each trace segment’s length by its delay per unit length. Do not use one FR-4 constant for every layer: an outer-layer microstrip and an inner-layer stripline can have different delay rates even when their physical lengths match.

Suppose two signals must reach a receiver within a tight timing window. Equal lengths can look good in the PCB editor while the actual paths have different electrical delays. The useful comparison is in picoseconds at agreed reference planes, not just millimeters.

Bare PCB coupon with straight copper test traces — Each routing structure needs its own delay estimate. AI-generated illustration; not a coupon design.

pcb propagation delay formula

For a uniform, low-dispersion transmission line, estimate the one-way delay as t ≈ L√ε_eff/c. Here L is trace length, ε_eff is dimensionless effective relative permittivity, and c is about 299.792 mm/ns. The formula returns nanoseconds when length is in millimeters. For a route with several uniform structures, estimate each segment separately and sum the delays.

Input	Unit	Use
L	mm	Length of each segment
ε_eff	None	Line model
Speed of light	mm/ns	299.792
Delay rate	ps/mm	Rate × L

Texas Instruments’ high-speed layout guide uses effective permittivity when comparing microstrip and stripline. Its example is a specific stackup, not an FR-4 rule. The approximation here also does not include connectors, package delay or a separate delay contribution from a via or launch.

pcb propagation delay per mm

In the simple model, the delay rate is about 3.336√ε_eff ps/mm. Multiply a ps/mm value by 25.4 to express it in ps/in. Compare the rates using the same units and without rounding too early, especially when converting a short timing budget into allowable length mismatch.

Model	ps/mm	ps/in
Microstrip (3.0)	5.78	146.75
Stripline (4.0)	6.67	169.45

At 80 mm, those two example lines take approximately 462.2 ps and 533.7 ps. Equal lengths leave about 71.5 ps difference before package and transition contributions. These are modeled values, not universal measurements or recommended limits. In a real board, use the stackup and trace model agreed for the applicable layer, not the example’s assumed values.

PCB test coupon and coax cables on a measurement bench — Define the measurement reference planes before comparing delay. AI-generated illustration; no measured results are shown.

fr4 pcb propagation delay

FR-4 is a material designation, not a single line velocity. A microstrip’s fields extend into more than one medium; laminate Dk, solder mask, trace width and height above the reference plane can all matter to the effective value. A homogeneous stripline approximation can use the surrounding dielectric value as a starting point, but mixed or asymmetric constructions still require a suitable model.

Microstrip vs. stripline for timing

When possible, route signals that must track each other through equivalent structures. If a layer change is unavoidable, ask for the relevant pressed thicknesses, material data and geometry so the solver can estimate delay by layer. Do not change to a different material solely to match the estimated velocity without also checking impedance, loss and manufacturing constraints.

pcb propagation delay calculator

Use a calculator only after choosing the units, reference planes and delay model. List every trace segment with its own delay rate; add a modeled or measured transition and package contribution if the timing budget includes those structures. Compare the complete path delays, not just their track-length totals.

Decide whether the budget is for the bare board or the complete path to the device pins.
Check the routing layers and divide mixed paths into uniform segments.
Calculate with full precision, sum, then round the result for reporting.
If the margin is small, confirm the model against a suitable coupon or measurement with agreed reference planes.

For a 50 mm outer segment at 5.7775 ps/mm and a 30 mm inner segment at 6.6713 ps/mm, the estimated trace-only delay is about 489.0 ps. Compare that with 462.2 ps for the 80 mm all-outer route: the same total length still leaves about 26.8 ps of difference. Add transition effects separately if the budget includes them.

A reflection on a TDR time axis includes travel out and back; that interval is not the one-way flight time used here. The TDR fault distance guide covers the separate round-trip conversion. Keep its time convention out of an end-to-end timing budget.

FAQ

Is propagation delay the same thing as impedance?

No. Impedance describes the voltage-to-current relationship of a traveling wave in the line; propagation delay describes travel time. A routing change can affect both, but matching nominal impedance alone does not guarantee equal delay. Evaluate each against its own requirement using the actual routing structure.

Should I use 150 ps/in for every FR-4 trace?

Use a rule of thumb for a quick feasibility screen, not as a final budget for every layer. A mask-covered outer trace and an inner trace can have different delay rates. Ask for a stackup-specific model when the difference matters to receiver timing or routing decisions.

Does equal PCB length guarantee that two signals arrive together?

Only if the paths have comparable delay per unit length and comparable contributions from transitions and packages. A board editor can report equal trace lengths for electrically different structures. Compare estimated time from the relevant launch to the relevant receiver plane before declaring the paths matched.

Do I include the device package delay in length tuning?

Include it when the timing requirement is defined at internal device reference points or when the component vendor specifies a package compensation model. If the budget is only for board connections, report package delay separately. Define the endpoint convention before adding package length or time to PCB results.

How does a via enter a propagation-delay budget?

Its effect is not always captured by adding the board thickness to the planar length. The transition includes a three-dimensional field and may add phase, loss and reflections. Use a suitable via model or measurement when the margin is small, and state whether the estimate includes that contribution.

Can a faster rise time change which delay estimate I should use?

A faster edge contains more high-frequency content. If the channel is dispersive, a single low-frequency delay may not describe the edge shape or timing of interest. Use an appropriate bandwidth and measurement definition rather than treating the simple low-dispersion model as exact at every frequency.

Should I measure a connector and trace together?

Measure them together if the requirement is for the complete interconnect. If you are trying to isolate the trace, use reference structures or agreed fixture removal to define the trace endpoints. Document which launch, cable or adapter contributions remain so another engineer can compare the results fairly.

How should I convert a skew budget into a length tolerance?

For two comparable uniform paths, divide the allowed time difference by the relevant delay per unit length. Do not use that shortcut across dissimilar structures without segment modeling. Apply package and transition allowances first if those contributions belong to the system’s budget.

Discuss Your Project

Send Best Technology the proposed stackup, routing layers, length or delay targets and timing reference points. Flag any planned layer changes or connector launches that need to be considered in the board review. Contact sales@bestpcbs.com.

TDR Resolution

November 9th, 2026

TDR spatial resolution describes whether two nearby impedance changes can be distinguished, not simply whether a reflection can be detected. Compare their echo separation with the effective step response at the device. A sharp instrument specification or a fine cursor readout does not guarantee two usable peaks on a real PCB.

Consider a coupon with two small discontinuities a few millimeters apart. The practical question is whether the setup can report two locations, one combined event, or only a difference from a known reference.

Bare impedance coupon with a coaxial launch connector — The launch belongs to the measurement path. AI-generated illustration, not a tested coupon.

Separate detection from resolution

A time-domain reflectometer sends a step and observes reflections from impedance changes. One visible bump can indicate that something changed without showing how many features contributed. Resolving two features is the stronger claim: the trace must contain enough evidence to distinguish the two responses under the actual measurement conditions.

Record the parameters that set the test

Record time intervals, edge definition, velocity and reference plane before comparing plots. Distinguish the instrument’s specified step from the response available through the cable and launch. The resolution section of Tektronix’s TDR application note explains how step rise time, settling and ringing can cause nearby events to merge.

Parameter	Record
Effective edge	Rise time and threshold convention
Echo gap	Interval on the reflection time axis
Velocity	Measured or modeled path basis
Reference	Calibration or fixture plane
Signal quality	Noise, ringing and repeatability

Compare three different measurement claims

Choose the strongest conclusion supported by the data, not by the instrument’s display precision. A one-feature reference and a controlled two-feature coupon can help separate a real resolution result from a convenient interpretation of a broad trace.

Claim	Evidence needed
An event exists	Repeatable difference from reference
Two events resolve	Distinct responses on matched setup
Feature sizes are known	Suitable model and validation

Convert spacing to an echo interval

For two features on the same uniform line with one-way spacing d and propagation velocity v, their first-return spacing is approximately Δt = 2d ÷ v. Use d in mm and v in mm/ns to obtain ns. The formula describes expected timing, not a resolution specification. For absolute location or an instrument distance display, see the TDR fault distance guide.

Test the two-feature teaching example

Assume 3.2 mm spacing and 160 mm/ns velocity. The calculated echo gap is 0.040 ns, or 40 ps. A hypothetical effective 100 ps edge makes overlap a serious concern; a 30 ps edge is a better candidate for separation. Neither example is a pass criterion: amplitudes, polarity, ringing, fixture quality and noise still affect the result.

Treat rise-time rules as screening only

Published heuristics describe when small, similar discontinuities may be separated. Check whether a rule’s timing refers to one-way electrical separation, displayed reflection interval or a specific instrument convention before converting it to length. A known two-feature reference tested with the actual setup is a better basis for making a product-specific resolution claim.

Account for the path before the device

Cables, adapters and a launch can broaden the incident edge or add their own reflections. Document where the test plane is and what fixture treatment was used. If the suspected features are near a strong launch response, compare a reference with the same launch before treating a second shoulder as a separate defect.

Check the effect of polarity and magnitude

Similar reflections can merge into a broader feature, and opposite-polarity contributions can partially cancel. A small event next to a large one can disappear into its tail even when the spacing looks promising. Compare changes relative to an approved reference rather than counting visible peaks as a complete map of the underlying structures.

Coaxial cable and calibration terminations beside a PCB test coupon — Use a documented reference before interpreting nearby echoes. AI-generated illustration, not a calibration result.

Avoid confusing oversampling with bandwidth

A small sample interval can produce a smooth plot without recovering detail removed by a slow edge or bandwidth limit. Record acquisition settings, averaging and any filtering. Look for a stable conclusion when settings change within a controlled comparison; do not treat a software zoom or extra digits as a physical improvement.

Use an edge sweep as a diagnostic comparison

If the equipment supports controlled changes in effective edge, compare the same reference plane and coupon at two settings. A shoulder that becomes reproducible as the response improves deserves investigation. Changing the edge also changes how strongly some features appear, so use a reference and do not label the outcome as a universal acceptance threshold.

Validate a coupon against the intended question

For a fabrication test, confirm whether the deliverable is nominal impedance, a controlled discontinuity comparison or a resolution study. A routine coupon designed to measure a long uniform line may not answer the last question. Agree on feature spacing, construction, reference data and criteria before ordering a special verification coupon.

Report uncertainty instead of inventing a second location

State the feature geometry, timing basis, observed edge and what the trace supports. If two returns cannot be distinguished reliably, report a combined or unresolved event and identify the next check. The test can still narrow an investigation without claiming a defect count or location precision beyond the evidence.

FAQ

Does seeing one bump mean there is one defect?

No. A broad response can include multiple nearby discontinuities or a fixture contribution. Compare the expected physical features and a known reference before deciding what the event represents. If the setup cannot reliably distinguish candidates, report the observation as unresolved rather than assigning an exact count.

Can a TDR see a feature smaller than its quoted resolution?

A small feature may change the measured response relative to a suitable reference even when its two boundaries are not separately identifiable. Detection, separation and dimension extraction are different claims. State which one is supported by the evidence and avoid treating a visible difference as a calibrated feature size.

Does averaging make two reflections easier to separate?

Averaging can help with repeatability when noise is the limiting factor. It does not restore bandwidth or remove systematic ringing. Compare the same setup and keep the acquisition settings with the result. If two responses are still inseparable after noise improves, changing the edge or reference may be more useful.

Should I test at the fastest available edge?

Use an edge suited to the question. A fast setting can help identify nearby features, while a slower setting can help assess the response under a different relevant excitation. Record which setting supports each conclusion, and do not use one trace to imply performance at every system edge rate.

Can a VNA time-domain plot answer the same question?

It can support a related investigation if the frequency span, window, calibration and transform are appropriate. Its effective time response is not automatically identical to a direct-step TDR. Compare validated reference structures and report the settings and observable result rather than assuming the two displays are interchangeable.

Is a launch artifact always removed by calibration?

Not if the launch is outside the calibrated plane and remains part of the measured network. A suitable fixture treatment or a matched comparison may be needed. Record the physical plane and which structures remain included, then verify that a changed feature is not simply a different launch response.

Can the impedance coupon prove an assembled channel will pass?

No. The coupon can document behavior of its defined geometry under the measured conditions. An assembled channel includes connectors, components and other transitions, and can have different acceptance criteria. Use coupon evidence for the property it represents and perform appropriate channel verification separately.

What should a report say when separation is borderline?

Include the expected echo gap, effective response, test reference and comparison result. State whether the trace supports detection only or separation under specific conditions. If a decision depends on distinguishing the features, define the next controlled measurement instead of rounding the reported distance to imply greater certainty.

References and Question Research

Controlled-impedance inspection discussion informed the coupon and reference-plane questions; instrument guidance and the stated model support the technical explanation.

Discuss Your Project

For a fabrication or coupon review, send Best Technology the stackup, relevant geometry, test purpose and required evidence at sales@bestpcbs.com. Specify whether the request concerns nominal impedance or a separate two-feature measurement study.

Ceramic Mounting

November 7th, 2026

Ceramic substrate mounting needs a defined load path, suitable support and a controlled thermal interface. Do not pull a bare ceramic circuit flat with screws or copy a packaged power module’s mounting torque onto an unqualified ceramic plate. A module housing or pressure system can distribute load in ways that a bare substrate does not.

Consider a hypothetical copper-patterned ceramic circuit intended to sit on an aluminum heat spreader. Its underside must make useful thermal contact without being forced to bridge an unsupported gap. This guide shows how to review that mechanical interface; it does not provide a universal torque, clamping pressure or installation recipe.

Copper-patterned white ceramic circuit substrate supported on a flat aluminum plate — AI-generated physical illustration; not an approved mounting arrangement or a tested Best Technology product.

Identify the Product Being Mounted

A bare ceramic circuit, a ceramic-based power module and a baseplate-equipped package are different mechanical objects. Start with the exact part drawing and assembly construction. The word ceramic alone does not identify the surface to clamp or the component designed to carry fastening load.

A bare substrate exposes the circuit carrier directly. A packaged module may include a housing, spring elements, terminals and specified fastening points. A metal baseplate adds another structural and thermal interface. Treat these as different designs rather than three versions of the same screw-mounting problem.

Collect Detailed Mounting Parameters

The review needs dimensions and limits for the actual assembly. Record where each requirement comes from and what surface it applies to. Missing force, support or flatness limits should remain engineering questions, not numbers copied from an unrelated module.

Input	Identify
Substrate	Material, thickness, outline, copper pattern
Support	Contact region and unsupported span
Mating surface	Flatness, roughness, steps, cleanliness
Retention	Load points and approved force basis
Thermal interface	Material, coverage and thickness basis
Environment	Temperature range, cycling, vibration

For a product-specific numerical example, SEMIKRON’s SKiM4/5 mounting instruction, revision 4.0, May 2017 specifies heatsink unevenness no greater than 50 µm per 100 mm and Rz no greater than 6.3 µm. Those are source-specific examples, not universal bare-ceramic limits.

Compare Bare Ceramic, Baseplate-Less and Baseplate Designs

The structure determines how fastening force reaches the thermal interface. Do not assume that a screw visible on a module presses directly on its ceramic in a way that can be copied safely.

Construction	Review focus	Do not assume
Bare ceramic	Designed support and retention	Generic screw torque
Baseplate-less module	Housing or pressure system	Bare plate equivalence
Baseplate module	Specified fastening and interface	Unlimited bending tolerance

SEMIKRON’s SEMITOP Classic technical explanation, revision 06, July 2021 describes a baseplate-less module whose housing distributes mounting pressure. That architecture-specific explanation does not qualify an arbitrary clamp placed across an exposed ceramic circuit.

Draw the Mechanical Load Path

The load path is the route through which fastening force reaches the support. Sketch the screw or clamp, load-spreading features, substrate, interface and supporting plate. Include terminals or cables that could apply unintended leverage.

In the hypothetical circuit, ask whether a clamp force reaches a supported region or pushes the ceramic across a gap. If the design cannot explain where force enters and leaves the assembly, stop before selecting a torque. A clearer drawing is more valuable than a precise tightening number with no mechanical basis.

Separate Flatness from Surface Roughness

Flatness describes shape over a region; roughness describes smaller-scale surface texture under a defined measurement. A surface can have low roughness and still be bowed. Cleaning it does not remove a geometric step or correct a distorted mating plate.

Specify the measurement area, reference and method before comparing reports. For the aluminum spreader, inspect burrs, steps and particles as well as the overall shape. Do not treat a single finish designation as evidence that the complete contact region meets the assembly drawing.

Do Not Force a Gap Closed

A visible gap is a reason to investigate the interface, not automatically a reason to tighten harder. Determine whether its cause is substrate shape, mating-surface geometry, contamination or the specified interface material. Use the approved inspection and disposition process.

For example, a particle beneath one corner can create a local support problem. A small apparent contact area can then carry a concentrated load. Remove the cause through an authorized process and recheck the assembly; do not deliberately bend the ceramic as a substitute for establishing the correct support.

Treat the Thermal Interface as a Controlled Layer

The interface must suit both the thermal objective and mechanical construction. A thermal grease, pad, phase-change layer or adhesive is not interchangeable merely because each is described as thermally conductive. Their behavior under load and temperature differs.

The SKiM instruction provides a named-paste and application-specific example; use the actual product’s current instructions rather than generalizing its thickness. An unqualified thick layer should not be used to compensate for an unexplained mechanical mismatch. Agree the material, coverage, application control and inspection basis together.

Unpowered ceramic-based module and aluminum heat sink arranged for interface review — AI-generated interface-review scene, not a verified package design or an interchangeable thermal-material recommendation.

Understand Why Torque Is Not Clamping Pressure

Torque is a turning moment applied to a fastener; clamping pressure is force divided by the relevant contact area. The relationship depends on the joint, friction, fastener and load path. A torque number cannot be converted into ceramic stress without that information.

For a simple teaching example, a uniformly distributed 100 N force over 100 mm² would give 1 N/mm², or 1 MPa. Real contact need not be uniform, and this arithmetic is not an allowable load. It illustrates why effective area and local stress matter as well as total force.

Review Thermal Expansion and External Constraints

The substrate, copper, support and attached hardware can change dimensions differently with temperature. The mounting design must account for the resulting constraints, rather than treating room-temperature fit as the entire requirement.

Identify the operating range and cycling conditions, then review how the assembly accommodates movement. Avoid letting a rigid cable or busbar become an unintended structural brace. The related ceramic substrate CTE discussion explains why material interactions need their own assessment.

Inspect Edges Before and After Assembly

Keep an inspection baseline so that new damage can be distinguished from incoming condition. Record chipped edges, cracks and disputed surface features with the part identity and drawing requirements. Do not invent an allowable defect size from a photograph.

If damage is found after mounting, preserve the assembly state and process history before disassembly where safe and appropriate. Compare the evidence with the approved criteria and seek engineering disposition. See the ceramic edge-chipping guide for the distinction between observation and acceptance.

Validate the Assembly, Not Only the Fastener Setting

A correctly recorded fastener setting does not establish every thermal, electrical or mechanical requirement. The validation plan must address the actual construction and intended environment. Include the properties that matter to the product rather than relying on a single installation record.

For the hypothetical circuit, appropriate engineering review would define contact inspection, temperature assessment and relevant environmental or insulation validation. Do not energize a cracked or uncertain power assembly as an informal test. High-energy work requires trained personnel, safe isolation and an approved plan.

Use a Mounting Release Checklist

Identify the exact substrate or module construction.
Obtain the applicable drawing and mounting instructions.
Draw support regions and the complete load path.
Verify the mating surface and interface material.
Confirm retention requirements without borrowing unrelated limits.
Review thermal movement and external loads.
Record inspection, validation and engineering approval.

The release should explain why the ceramic is supported and why the applied loads are acceptable. If those explanations are missing, more tightening precision cannot fill the gap.

FAQ

Can I use a power-module torque on a bare ceramic circuit?

No generic transfer is justified. A module may distribute force through a housing or engineered pressure system that the bare ceramic lacks. Obtain a mounting design and approved limits for the actual substrate. Matching the material name or overall dimensions does not make the mechanical load paths equivalent.

Will a softer thermal pad automatically protect the ceramic?

Not automatically. The result depends on the pad’s properties, thickness, compression behavior, contact area and the complete mounting design. A compliant layer can also change the support condition. Review it as part of the assembly rather than assuming that softness alone establishes a safe load or good thermal contact.

Can grease fill a large gap caused by a bent support?

Do not use an unqualified interface layer to hide a geometry problem. Establish whether the support and substrate meet their drawings first, then select the approved interface process. Thermal contact, retention and stress must be evaluated together. A filled-looking gap is not proof that the resulting assembly is acceptable.

Does a smooth-looking heat spreader prove it is flat enough?

No. Appearance and surface texture do not establish shape over the required region. Use the specified measurement basis and inspect the actual contact area. A surface may look polished while still containing a step, bow or local feature that matters to the mounting design. Keep flatness and roughness records separate.

Can washers alone prevent mounting damage?

A washer may change how a load is distributed, but it does not validate the entire joint or eliminate bending. The substrate support, hole geometry, fastener and interface still require review. Do not add hardware by analogy to an FR-4 board and assume it creates an approved ceramic mounting arrangement.

Is an edge chip automatically harmless if the circuit conducts?

No. Continuity does not determine the structural or insulation significance of the damage. Record the feature and assess it against the drawing and product requirements. Obtain engineering disposition when the effect is uncertain. Do not enlarge, grind or cover the defect merely to make the part look acceptable.

Can a used module be remounted with the old interface layer?

Follow the actual product and interface-material instructions for reuse, cleaning and reapplication. Do not assume that a previously compressed layer will reproduce its original condition. Preserve evidence if the unit is under investigation, and use an approved remounting process rather than treating the first installation record as continuing qualification.

What information should accompany a ceramic mounting drawing?

Include the exact substrate or module identity, support and contact regions, mating-surface requirements, retention basis, interface material and relevant operating conditions. Identify the controlling instructions and validation requirements. This gives the reviewer a complete assembly question rather than an isolated request for a generic screw size or torque.

References and Question Research

Technical examples come from the SEMIKRON documents linked above, with their dates and product scope retained. Community discovery included thermal interface versus electrical insulation confusion and heatsink-mounted component replacement. These adjacent questions informed the FAQ; neither is a ceramic-substrate mounting qualification.

Discuss the Ceramic Circuit Construction

Send Best Technology the substrate drawing, copper pattern, support concept, thermal interface and operating conditions at sales@bestpcbs.com. Ask for clarification of the fabrication requirements. Final mounting loads and product qualification require approval for the actual assembly.

PCB Pulse Current

November 7th, 2026

For a PCB conductor modeled as a constant resistance, average resistive heating follows I_RMS²R—not I_average²R. A repeating rectangular current that switches between zero and a positive peak has I_average = I_peakD and I_RMS = I_peak√D, where D is the duty cycle expressed as a fraction.

That difference matters in switched loads, motor-drive paths and pulsed actuators. It does not mean RMS alone determines a safe trace width. Peak current, pulse duration, repetition, copper geometry, connections and temperature still need review. Start with the actual current waveform in the specific conductor—not the controller’s PWM setting.

Low-voltage power PCB with broad copper paths and screw terminals — AI-generated power-board illustration; not a validated current rating or a tested circuit design.

Understand Peak, Average and RMS Current

Peak current is the largest instantaneous current magnitude of interest. Average current is the signed mean over the chosen observation interval. RMS means root mean square: square each current value, average those squares, then take the square root. Squaring makes both current directions contribute positively to resistive heating.

For an ideal resistor, a waveform’s RMS value corresponds to the direct current that produces the same average heating. Fluke explains the heating-value basis of RMS measurement. Average current remains useful for other questions, but it is not interchangeable with RMS when evaluating copper loss.

Record the Detailed Waveform Parameters

Duty cycle is on-time divided by period. A 25% duty cycle is D = 0.25, not 25, in the formulas. The off-state current must actually be zero for the simple zero-to-peak equations below; freewheeling and ripple can make that assumption wrong.

Parameter	Record	Why it matters
Peak current	Magnitude and polarity	Instantaneous stress
On-time	Seconds or subunits	Pulse energy
Period	Full repeating interval	Repetition and RMS
Off current	Zero or measured value	Formula validity
Burst pattern	Active and idle intervals	Thermal history
Path resistance	Temperature and geometry	Loss and voltage drop

Also record ambient temperature, enclosure airflow, copper construction and the allowable temperature rise. These are project inputs, not fixed universal values or a Best Technology capability table.

Calculate a Zero-to-Peak Rectangular Pulse

Consider a hypothetical conductor carrying 8 A for one quarter of each period and zero for the rest. Its average current is 8 × 0.25 = 2 A. Its RMS current is 8 × √0.25 = 4 A.

Why are the results different? The average calculation weights current directly, whereas heating weights its square. The on-state contributes 8² × 0.25 = 16 A² to the mean square. Taking the square root gives 4 A. The example assumes ideal rectangular pulses and constant resistance; it is not a qualified operating point for any particular PCB.

Compare Equal-Average Waveforms

Three waveforms can deliver the same average current but produce different conductor losses. The following teaching comparison assumes identical constant resistance and sufficient repetition to discuss average electrical loss. It does not predict a temperature rise or approve a peak current.

Waveform	Mean	RMS	Loss vs 2 A DC
2 A DC	2 A	2 A	1×
4 A, 50% on	2 A	2.83 A	2×
8 A, 25% on	2 A	4 A	4×

The practical lesson is simple: reducing duty cycle does not make peak current harmless. Compare the full waveform and resulting loss, then investigate transient temperature and the weakest part of the path.

Translate RMS into Copper Loss

If the hypothetical path resistance is 10 mΩ, the 4 A RMS case produces 4² × 0.010 = 0.16 W average resistive loss. Using its 2 A mean would incorrectly predict 0.04 W. The arithmetic explains a fourfold loss difference without claiming the board becomes four times hotter.

Temperature rise depends on heat spreading and cooling, and resistance changes as copper heats. At higher frequencies, current distribution can also make a simple DC-resistance model incomplete. Treat I_RMS²R as the defined model here, not as a substitute for the actual electrical and thermal assessment.

Distinguish Repeating Heating from Single-Pulse Stress

A repeating low-duty waveform and one isolated pulse are not the same thermal problem. A long pulse can create a significant local temperature excursion even if an average over a very long idle interval looks small. A short repeating pulse train can accumulate heat if cooling between pulses is limited.

State pulse width, repetition and burst duration together. For an isolated event, evaluate energy and transient response as appropriate. Do not choose a long averaging interval merely to make the reported RMS lower. The observation interval must represent the operating question being answered.

Measure the Current in the Correct Branch

A PWM control signal describes switching commands, not necessarily the current in every copper path. An inductive load can continue carrying current during a switch’s off interval through another route. Capacitors may supply a pulse locally while the input connector sees a smoother waveform.

Draw the current loop for each switching state and identify the exact trace, via or connector under review. Measure or calculate that branch current. Applying the controller’s duty cycle to the input current, load current and switch current indiscriminately can give three plausible-looking but incorrect heating estimates.

Handle Nonzero Off-State Current and Ripple

For a two-level waveform, use I_RMS = √[D I_on² + (1 − D) I_off²]. The simple peak-times-square-root formula is its special case when the off current is zero. Average current is D I_on + (1 − D) I_off.

For arbitrary measured samples, square the current samples, average over a representative interval and take the square root, with appropriate sampling and time weighting. A waveform with ramps or spikes needs its actual shape represented. Do not force it into a rectangular model solely because the switching command is rectangular.

Current probe and measurement leads arranged around a low-voltage power PCB — AI-generated bench illustration; not a verified probe connection, live measurement or safety procedure.

Check Meter Coupling, Bandwidth and Crest Factor

A true-RMS label alone does not guarantee that a meter captures the desired waveform. Determine whether the selected function measures the AC component only or total AC-plus-DC RMS. For a unipolar pulse train, removing the DC component changes the reported result.

Check bandwidth, crest-factor limits, range, probe saturation and sampling interval. Consult the actual instrument manual; the Fluke 287/289 manual, for example, separates functions and frequency-dependent specifications. Use suitable low-voltage test arrangements and qualified personnel. Never put a current-mode meter directly across a voltage source.

Review Neckdowns, Vias and Connections

A wide copper pour can feed through a narrow neck, small thermal-relief spokes, a via group or a connector pin. Those local features can govern loss and temperature. Parallel conductors do not necessarily share current equally if their electrical and thermal paths differ.

Review the complete route rather than calculating only its widest section. Record copper thickness, minimum finished width, path length and connection details. The high-current PCB overview provides related construction context; no generic article replaces validation of the actual board and operating cycle.

Do Not Borrow a MOSFET Pulse Rating for a PCB Trace

A component’s pulsed-current rating belongs to that component and its stated conditions. It does not qualify the board, connector or solder joint around it. TI’s discussion of MOSFET pulse-current ratings emphasizes pulse-duration and duty-cycle conditions.

Check each element independently, including component operating limits and the complete current path. A trace that survives a few demonstrations has not thereby established its production margin, lifetime or fault behavior. Separate normal repeated operation, startup surge and fault events in the design review.

Validate the Board with a Repeatable Checklist

Identify the branch and actual waveform.
Record peak, RMS, mean, timing and burst conditions.
Check the formula’s zero-current and constant-resistance assumptions.
Review every neckdown, via and connection.
Measure temperature at representative worst-case operation.
Include enclosure, ambient and startup conditions.
Record limits, uncertainty and the approved configuration.

Use controlled measurements to connect electrical loss to real temperature. If using infrared inspection, account for surface measurement limitations; see the PCB infrared temperature guide. RMS is a powerful starting point because it addresses the right heating quantity—not because it removes the need for validation.

FAQ

Can I size a pulsed-current trace from average current?

Not as a general heating calculation. For a constant-resistance conductor, average loss depends on mean-square current. Use the actual waveform’s RMS value, then check transient and peak limits separately. Average current can describe charge delivery, but it can substantially understate heating when substituted into the squared-current loss equation.

Does a 25% duty cycle mean one quarter of the heating?

Only under clearly stated comparisons. With the same peak current and constant resistance, a zero-to-peak rectangular waveform has one quarter of the continuous-peak average loss at 25% duty. It does not have the same loss as DC at one quarter of that peak current. Keep the reference case explicit.

Can RMS current alone prove a PCB trace is safe?

No. It estimates resistive heating within a defined model but does not establish allowable temperature, transient stress, connection ratings or failure margin. Evaluate the real geometry, copper construction, cooling and operating history. Peak events and fault conditions need their own review even when the normal RMS value looks modest.

Why does my current meter disagree with the calculation?

Check whether the meter measures mean DC, AC-only RMS or total AC-plus-DC RMS. Also check bandwidth, crest factor, range and probe behavior. Then verify the waveform and measurement interval. A meter and calculation can both be internally correct while describing different components or time windows of the same signal.

Does the PWM duty cycle equal the load-current duty cycle?

Not necessarily. Inductance, freewheeling paths and local capacitors can keep current flowing or move pulse current between branches. Determine the waveform in the actual conductor under review. A controller’s on-time is not sufficient evidence that the trace current switches instantly between zero and a fixed peak.

What if current continues during the off interval?

Include that current instead of using the zero-off shortcut. For two constant levels, average their squared values with their time fractions and take the square root. If the current ramps or rings, integrate or sample the real waveform appropriately. The model should follow the current, not only the switch command.

Can I use a component’s pulse rating as the board limit?

No. The rating applies to that component under its documented conditions. Copper, vias, terminals, solder joints and other parts have separate constraints. Review the entire path and verify the actual pulse timing and thermal environment. One part’s large pulsed-current headline does not qualify the surrounding assembly.

How should I validate a burst that occurs only occasionally?

Record the pulse shape inside the burst, burst duration, repetition interval and initial temperature. Evaluate both local temperature excursion and longer-term heating under the real operating sequence. Do not dilute the event with an arbitrary idle interval. Include plausible repeated commands and startup conditions in the approved validation plan.

References and Question Research

Technical references are the instrument-manufacturer and semiconductor-manufacturer sources linked above. Community discovery included questions about pulsed trace width and pulse current and trace limits. Their anecdotes are not current ratings; the FAQ answers use the stated electrical model and source limitations.

Discuss a High-Current Fabrication Requirement

Send Best Technology the stackup, copper geometry, current waveform, temperature limits and validation requirements at sales@bestpcbs.com. Request a project-specific fabrication review. Any current or thermal performance commitment must be supported by the actual design, agreed construction and validation evidence.

PCB Infrared Guide: Read Copper

November 7th, 2026

PCB infrared temperature measurement needs a defined surface and measurement setup, not just a thermal camera pointed at the board. Shiny copper can emit little infrared radiation while reflecting its surroundings. A cool-looking copper path may therefore be hotter than it appears, and a bright patch may be a reflection rather than a local heat source.

Consider a hypothetical high-current prototype with exposed copper beside green solder mask. An engineer wants to check its conductor temperature under the approved load. This guide follows the measurement review before any layout decision; it does not provide permission to energize, probe or modify an unsafe circuit.

Infrared camera on a laboratory stand aimed at a power PCB in an insulating fixture — AI-generated measurement-context illustration. No camera display or image here is a measured temperature result.

What the Camera Measures at a Copper Surface

The camera detects radiation reaching its sensor and uses a model to estimate surface temperature. For an opaque surface, emitted and reflected contributions both matter; the reading is not a direct electrical measurement of the copper.

On the teaching board, exposed copper and adjacent solder mask can have different radiative behavior even where their actual temperatures are close. First identify exactly which visible surface the measurement region covers. A number taken across copper, mask and a component body is not automatically the temperature of any one of those objects.

Record the Parameters Behind a Temperature Reading

A credible result preserves the camera, surface, optical setup and operating condition together. A cropped color screenshot without these inputs is incomplete.

Parameter	Unit or record	Why it matters
Emissivity	Dimensionless, 0–1 model scale	Relates radiation to the surface
Reflected apparent temperature	°C, method stated	Accounts for reflected surroundings
Camera and lens	Model, calibration, spectral band	Defines measurement capability
Geometry	Distance, angle, target size	Defines what is resolved
Operating state	A, V, duration and airflow	Defines the heat-producing condition
Target	Surface, location and board revision	Prevents comparing different objects

The table specifies reporting fields, not universal settings. Use the actual camera’s instructions and a qualified test plan to establish values. Do not insert a guessed emissivity simply because another board had the same color.

Compare Bare Copper, Solder Mask and a Reference Patch

These surfaces cannot be compared as if one camera setting makes all of them equally reliable. Their finish, optical properties and thermal relationship to the conductor differ.

Surface	Main concern	Useful check
Shiny copper	Low emission, strong reflection	Validate the surface method
Solder mask	Different surface from copper	Identify coating and target
Known reference patch	Compatibility and equilibration	Verify material and thermal contact
Component package	Surface is not the junction	Use component-specific limits

FLIR’s emissivity explanation notes that highly polished copper or aluminum commonly has emissivity below 0.10. That is a warning about reflective surfaces, not a calibrated value for this prototype. Plating, oxidation, roughness and wavelength can change the appropriate value.

Distinguish Emissivity from Thermal Conductivity

Emissivity concerns radiation from a surface; thermal conductivity concerns heat transfer through a material. Copper can conduct heat well while remaining difficult to measure by infrared imaging.

For the high-current path, do not conclude that a cool-colored area has low electrical loss or strong cooling simply because it is copper. Conversely, a dark high-emissivity patch does not make the underlying material a better heat conductor. Keep the thermal model, electrical loss estimate and radiometric measurement as related but separate pieces of evidence.

Check Reflections Before Calling a Bright Patch a Hotspot

A reflective surface can redirect radiation from nearby people, equipment or other warm objects into the camera. Its apparent temperature can then differ from its actual surface temperature.

Record the surroundings and viewing geometry. A feature that changes strongly with the viewing arrangement warrants investigation before it is labeled a fault; changing the view alone does not quantify the correct temperature. In the teaching review, keep people and movable heat sources from changing the scene during the comparison. Do not reach into an energized assembly to test a reflection hypothesis.

Use a Reference Patch Only Under an Approved Method

A known high-emissivity patch can make a difficult surface easier to observe, but only when its optical behavior, temperature suitability and thermal relationship are understood. Any preparation must occur under the appropriate safe, de-energized procedure.

FLIR’s reference-material guidance warns that tape can transmit infrared radiation and that emissivity depends on wavelength and surface condition. Not every black tape is a characterized reference. Do not apply coatings indiscriminately to live conductors, fine-pitch contacts, optical parts or contamination-sensitive areas.

Matte black reference patch on a flat copper region of an unpowered PCB coupon — AI-generated preparation illustration. Actual patch selection, placement and electrical safety require an approved procedure.

Verify the Patch Follows the Target Temperature

The patch must be in adequate thermal contact and allowed to reach the relevant condition; otherwise the camera is accurately reading the wrong surface temperature. A patch also changes the surface being tested.

FLIR’s Extech infrared-measurement FAQ instructs users to let the reference material adjust to the surface temperature. For the prototype, consider whether a large or thick patch changes local heat transfer, bridges distinct areas or lags a short pulse. Keep any modified test specimen identifiable and avoid presenting it as an untouched production assembly.

Check Focus and the Smallest Target Size

A visible feature is not necessarily large enough for a trustworthy temperature measurement. The lens, working distance and optical blur determine how much surrounding material contributes to the reported point.

FLIR’s electronics macro-imaging discussion illustrates why a measurement target needs adequate pixel coverage and suitable optics. Use the actual camera’s measurement specification rather than assuming one illuminated pixel is sufficient. On our board, a narrow copper neck can be blended with cooler surroundings even when its location is apparent on screen.

Keep Load, Airflow and Timing Comparable

Temperature comparisons need the same defined operating condition. Different current, elapsed time, enclosure state or airflow can change the result independently of the copper geometry.

For the hypothetical prototype, record the approved load and whether the objective is a steady condition or a transient event. Opening an enclosure for the camera can alter cooling; document that boundary instead of treating the exposed bench result as a closed-product result. Do not improvise overload tests or infer a safe current rating from a single cool-looking frame.

Use Contact Measurements as an Independent Check

An appropriate contact sensor can help investigate a disputed infrared reading, but it has its own attachment, heat-flow and electrical-safety limitations. It is a cross-check, not an automatic truth source regardless of installation.

The two methods must address the same physical location and comparable time state. A sensor on a package top cannot validate a camera reading on a distant copper region, and neither directly measures an inaccessible semiconductor junction. If the methods disagree, review both setups before averaging the values or choosing the more convenient result.

Do Not Confuse Palette Contrast with Thermal Severity

Color maps depend on the selected range and palette; the brightest spot is not necessarily an unacceptable temperature. A different scale can make the same dataset look more or less dramatic.

Compare actual validated values, uncertainty and applicable limits, not color alone. Save the original radiometric data where the instrument supports it, together with the settings and visible-light context. A compressed screenshot may preserve the appearance while losing the ability to inspect measurement regions or revise justified analysis parameters.

Make a Layout Decision Only After the Measurement Is Defensible

A thermal image can direct the investigation, but it does not by itself identify electrical resistance, current distribution or the failure cause. Link the observation to the circuit and independent evidence.

Identify the surface and the exact test point.
Confirm optics, focus and target coverage.
Establish emissivity and reflection treatment.
Record load, airflow and timing.
Cross-check critical temperatures with a suitable method.
Compare against the correct component or conductor requirement.

The related high-current PCB neck-down guide explains one possible electrical heating mechanism. Investigate it when the geometry and loss evidence support that explanation, not merely because a thermal palette highlights the area.

FAQ

Can I use 0.95 for every part on a PCB?

No. A single convenient setting does not characterize shiny metal, coatings and package materials equally. Use a verified surface method and the camera’s relevant instructions. A general material table can help identify a concern, but it is not calibration evidence for every finish, wavelength band, temperature and observation angle on the board.

Does a higher-resolution camera eliminate emissivity error?

No. More pixels can improve spatial detail, but they do not identify how the surface emits and reflects radiation. Focus, optics and target size still matter as well. Treat spatial resolution and radiometric interpretation as separate requirements; an exceptionally sharp picture of reflective copper can still carry a misleading temperature estimate.

Can the camera see a hot inner-layer trace through the board?

Ordinary PCB thermal imaging shows the observed surface response, not a direct view through an opaque stackup to each internal conductor. Internal heating can influence surface temperature, but that does not uniquely identify its source. Use construction information, electrical evidence and an appropriate thermal model before attributing the surface pattern to one hidden trace.

Can digital zoom make a narrow conductor measurable?

Digital enlargement does not add optical information that the sensor never resolved. It can make an image easier to view while leaving the original target coverage unchanged. Check the camera and lens measurement capability, focus and working distance. Do not mistake a large on-screen pixel block for a newly resolved physical temperature feature.

Will a visible-light photo tell me the infrared emissivity?

No. Appearance in visible light does not establish optical behavior in the camera’s infrared band. A finish that looks dark or matte may still need characterization, and surface condition can vary. Use the appropriate material evidence or validated method rather than choosing a setting solely from a color photograph of the board.

Does a cool connector prove its contact resistance is acceptable?

No. The observed surface may be reflective, unresolved or thermally separated from the critical contact. Load and elapsed time also affect the result. Validate the temperature measurement and apply the relevant electrical and mechanical acceptance checks. A cool-looking connector image cannot replace contact-resistance evidence or establish the condition of a hidden joint.

Can I compare before-and-after boards using different automatic palettes?

Not by color intensity alone. Record comparable operating conditions and measurement settings, then compare validated temperatures at defined locations. An automatically rescaled image can exaggerate or conceal a difference. Preserve the underlying data and scale information so the comparison remains meaningful even if a presentation palette is later changed.

Does a checked surface temperature establish a semiconductor junction temperature?

Not automatically. The junction is inside the device, and the relationship to a measured surface depends on the package, heat paths and operating condition. Use the manufacturer’s appropriate characterization or validated thermal model. Do not compare a copper-surface reading directly with a junction-temperature limit and call the device qualified.

For a Best Technology high-current PCB enquiry, send the conductor construction, operating condition and defined temperature-validation scope to sales@bestpcbs.com. Distinguish calculated loss, observed surface temperature and verified assembly performance in the review package.

Touchstone File Guide: Read S2P Data

November 7th, 2026

A Touchstone file stores frequency-dependent network parameters in text form. An .s2p file normally describes a two-port network, with four complex S-parameters at each frequency. Before importing it into a PCB simulation, check the units, data representation, port map and reference impedance; a file that loads successfully can still describe a different setup from the one you intended.

This guide follows a hypothetical passive RF PCB coupon between two connectors. Numerical examples are teaching values, not measured performance. The reference specification is Touchstone 2.1, ratified January 26, 2024; importing software may support a narrower subset.

RF PCB coupon connected to coaxial cables on a laboratory bench — AI-generated RF measurement-context illustration, not a measured S-parameter result or factory test record.

What an S2P File Tells You—and What It Does Not

The data describes a network response at specified frequencies and reference conditions, not the complete physical design. For the coupon, S21 describes transmission toward port 2 from excitation at port 1, while S11 describes reflection at port 1 under the parameter definition.

The file may originate from a measurement or a simulation. That origin, the physical port locations and included fixtures need accompanying documentation. The filename alone does not establish temperature, calibration, geometry, manufacturing revision or validation quality. It also does not make a small-signal device model valid for every bias or large-signal operating condition.

Read the Option Line Before the Numbers

The option line explains how to interpret the data. For the example # GHz S MA R 50, read the fields separately rather than assuming a familiar instrument’s export defaults.

Field	Example	Meaning
Frequency unit	GHz	1 means 1 GHz
Parameter type	S	Scattering parameters
Pair format	MA	Linear magnitude and angle
Reference	R 50	50 Ω reference in this example
Angle unit	Degrees	Not radians

Version-specific keywords can affect the interpretation, including reference values and port ordering. Read the complete header and the applicable specification instead of treating this one example as a universal template.

Compare MA, DB and RI Using the Same Complex Value

All three formats can describe the same complex S-parameter, but the two stored numbers mean different things. Keysight’s S-parameter table documentation identifies these supported representations.

Format	Pair means	Teaching example
MA	Magnitude, angle	0.5, −90°
DB	dB value, angle	−6.0206, −90°
RI	Real, imaginary	0, −0.5

The example value is −j0.5. Its magnitude in dB is 20 log₁₀(0.5) ≈ −6.0206 dB. These are calculated representations, not three measurement results. Simply changing MA to DB in the header without converting the data changes the meaning of the file.

Check the Special Two-Port Data Order

Do not assume every two-port row is stored in the intuitive S11, S12, S21, S22 sequence. The legacy two-port convention is frequency followed by the S11, S21, S12 and S22 pairs. Versions 2.0 and 2.1 use the applicable [Two-Port Data Order] declaration to identify the permitted order.

For the teaching coupon, manually identify one frequency and its transmission pair, then compare that point with the imported plot. This spot check can catch an ordering mistake before the wrong column becomes a design conclusion. Preserve any original header instead of rearranging columns by visual intuition.

Map File Ports to Physical Connector Locations

A correct numeric matrix still needs a physical port map. Label the coupon ends in the review record, identify signal and reference conductors, and confirm the direction represented by S21. Do not assume the left side of a photograph is always port 1.

For a reciprocal uniform coupon, forward and reverse transmission can look similar, so a reversed connection may not be obvious from one magnitude plot. Connector launches or other asymmetric features can matter when the model is connected to the next network. Keep a simple physical connection sketch with the data, separate from the file’s numeric indexing.

Separate Reference Impedance from the Connected Load

The S-parameter reference defines the wave representation; it does not say that the actual trace has a constant 50 Ω impedance or that every future connected load must equal 50 Ω. The simulator must interpret the file with the correct reference before connecting other circuit elements.

When changing the S-parameter reference, use a valid renormalization operation rather than editing the R value alone. The scikit-rf renormalization example shows that the same physical load has a different reflection coefficient under a changed reference. More advanced complex-reference cases also require attention to wave definitions; do not improvise them from a simple real-resistance example.

Understand Why S4P Does Not Automatically Mean Differential Data

Four ports can represent two single-ended conductors at each end, but that physical arrangement must be established. A four-port file can also describe another network entirely. Even for a differential pair, single-ended data and mixed-mode data require the correct interpretation and pairing.

For a differential version of our coupon, identify the positive and negative conductors at both ends and check the file’s declared mode/order information. A mistaken pairing can produce misleading differential transmission or mode-conversion results. Do not rename .s4p to .s2p to make an import dialog accept it.

Four-port PCB coupon with SMA connectors and detached coaxial cable ends — AI-generated connection-planning illustration. Actual port numbering and differential pairing must come from the data provider.

Check the Frequency Band and Low-Frequency Treatment

The dataset supports its stated frequency range; behavior outside that range depends on the importing tool’s modeling assumptions. Record the first and last frequencies, point spacing and whether the intended analysis requires extrapolation or a DC estimate.

For the coupon, compare the planned simulation band with the data before running a time-domain analysis. Ask how the tool handles missing low-frequency data, interpolation and high-frequency truncation. A smooth-looking extrapolated curve is not an additional measurement. Keep any fitted or extended dataset distinguishable from the original supplied file.

Identify What the Measurement Reference Planes Include

The model boundary determines which physical effects are already in the data. A coupon file measured at coaxial reference planes may include launches that a trace-only electromagnetic model excludes. Cascading both without checking their boundaries can count the same transition twice.

Ask for the calibration or de-embedding description and a physical definition of each reference plane. For the teaching network, decide whether the connector bodies, launch pads and uniform line are included. This is different from the numerical impedance reference: both need to be correct, but they answer different questions.

Check Physical Plausibility for the Intended Network

Passing a syntax check does not demonstrate passivity, causality, reciprocity or measurement accuracy. A passive coupon and a biased amplifier are different model classes, so the applicable checks must match the object.

Use the simulator’s documented validation tools and investigate suspicious behavior against the original data and measurement setup. Do not judge full multiport passivity solely by looking at one S21 magnitude. Likewise, do not “repair” a model automatically without understanding how the correction changes its response. Save the original and document any authorized fitted or corrected version.

Diagnose an Import Failure Without Corrupting the File

Identify the reader’s supported version and the exact reported problem before altering the data. Common review areas include the option line, frequency units, port count, pair format and required version-specific keywords.

Keep an unchanged original, test the file with a suitable independent reader, and compare at least one known point. If a format conversion is required, use a tool that actually converts the data and preserves the intended network meaning. Deleting unfamiliar header lines until the error disappears can remove information the importer needed to interpret the file correctly.

Release the Dataset with a Short Model Record

A usable handoff includes enough context to connect the network correctly and understand its limits.

File identity, revision and measured or simulated origin.
Format version, parameter type and pair representation.
Frequency range and any fitting or extrapolation.
Physical port map, reference planes and impedance convention.
Relevant bias, temperature and construction conditions.
Import spot check and applicable model validation results.

For interpretation of reflected signals, see the related PCB return loss and S11 guide. Reading the file correctly is the starting point for that interpretation, not proof that the manufactured channel meets its requirement.

FAQ

Can a CSV export be renamed to .s2p?

No. The content must follow the supported Touchstone syntax and contain the required complex network data. A spreadsheet of frequency and one magnitude curve is not a complete two-port network. Use an appropriate export or conversion method, then verify units, ordering and a known data point in the receiving tool.

Why does a file open in one tool but not another?

The tools may support different versions or subsets of the format, or may handle nonconforming input differently. Compare their documented capabilities with the actual header and data. A tolerant reader accepting the file does not prove full conformance, and a rejected file should not be fixed by removing required information blindly.

Can the file contain Y or Z parameters instead of S parameters?

Yes, the declared parameter type matters. Do not interpret every pair in a file as an S-parameter just because the workflow uses the word Touchstone. Check the option line and the receiving tool’s support for that parameter type. A conversion to scattering parameters must use the appropriate definitions and reference conventions.

Does a negative S21 dB value mean negative power?

No. It is a logarithmic representation of the magnitude of a complex transmission parameter under the stated reference definition. In the teaching example, magnitude 0.5 corresponds to about −6.02 dB. Interpreting delivered power additionally requires the relevant network and termination conditions; the sign alone is not a power measurement.

Can I recover phase from a magnitude-only screenshot?

Not as a complete replacement for the original complex dataset. A plot of magnitude omits phase information and usually lacks the full numeric precision and context needed for a network model. Ask for the original file rather than reconstructing a production simulation from a screenshot and assuming the missing phase is zero.

Does an S2P file fully describe an operational amplifier?

Not across every operating condition. Device data depends on how the part was biased, connected and characterized, and a small-signal network description does not replace all nonlinear, stability or supply behavior. Check the manufacturer’s intended model use and conditions before applying a two-port representation to an amplifier circuit.

Should I delete comment lines to improve compatibility?

Only if a documented conversion or troubleshooting step justifies it and the original is preserved. Comments may carry essential human-readable context such as port names or measurement conditions, even when they do not alter numeric parsing. Keep that context in the handoff record rather than stripping it simply to make the file smaller.

Is a supplier’s simulated file equivalent to a measured production coupon?

No. Both can be useful, but they answer different evidence questions. A simulated file depends on the model assumptions; a measurement depends on the specimen and test setup. Label the origin clearly and compare the construction and conditions with the intended PCB. Do not present simulation output as a manufacturing test certificate.

For a Best Technology RF PCB enquiry, send the stackup, conductor requirements, model boundary and intended validation scope to sales@bestpcbs.com. Keep the supplied network file paired with its physical port map and construction revision.

Huray Roughness Model: Input Guide

November 7th, 2026

The Huray roughness model represents copper surface texture using an idealized nodule geometry to modify conductor surface impedance. In Ansys HFSS 3D Layout, its inputs include a nodule radius and a dimensionless Hall-Huray surface ratio. They are not interchangeable with a foil datasheet’s Rz roughness height.

This guide follows a hypothetical RF microstrip coupon from material selection to simulation review. Its useful output is a traceable input record: which copper face each value describes, where that value came from, which solver convention was used, and how the model was checked. It does not supply universal roughness settings for an unspecified PCB.

Matte and more reflective copper foil swatches on a laboratory tray — AI-generated physical-material illustration. Visible sheen does not measure micron-scale roughness or identify Huray parameters.

What the Huray Model Does to a PCB Simulation

The model accounts for electrical consequences of surface texture without requiring the mesh to reproduce every microscopic feature. A smooth-copper calculation and a roughness-enabled calculation can therefore differ even though the drawn trace geometry is unchanged.

Ansys documents a causal modification that also handles phase effects, rather than only a real-valued loss increase. See its Huray Surface Roughness Model documentation, 2025 R2. Record the actual implementation and version; the name “Huray” alone is not a complete description of a simulation setup.

Why Copper Texture Matters More as Frequency Rises

At increasing frequency, skin effect concentrates current nearer conductor surfaces, making the condition of those surfaces relevant to loss. Skin depth is the characteristic penetration distance, not the physical foil thickness. That is why a thick copper layer can still need a surface model.

For the RF coupon, first define the operating frequency range and acceptable channel behavior. Do not ask whether roughness matters in isolation from frequency, geometry and field distribution. The current in both the signal conductor and its return path matters. A visual inspection of a shiny top surface does not characterize the less visible copper-dielectric interface.

Key Huray Parameters and Their Units

Keep physical dimensions, dimensionless factors and software defaults in separate fields. This avoids a numerically plausible entry acquiring an unsupported physical meaning.

Input	Unit	Interpretation
Nodule radius	Length, e.g. µm	Radius in the idealized surface model
Hall-Huray ratio	None	Surface-area relationship under the model convention
Rz or Rq	Length	Measured profile statistic, not automatically either input above
Conductivity	S/m	Conductor property, separate from roughness
Frequency	Hz and stated sweep	Range over which the response is evaluated

The current PyEDB StackupLayer API reference shows default Huray inputs of 0.5 µm and 2.9. These are API defaults, not measured values for your copper. Explicitly supply reviewed inputs and record their source rather than accepting a default because the solver runs.

Why Rz Cannot Simply Be Pasted into Nodule Radius

Rz describes a surface-profile measurement, while nodule radius describes the geometry assumed by the model. A numerical conversion requires an identified method and assumptions; equal units do not make two quantities equivalent.

A Cannonball-Huray derivation is one published route for estimating model inputs from foil roughness information. It introduces a close-packed-sphere assumption rather than proving that a real copper surface consists of identical spheres. Use the method as a documented estimate within its limits, not as an exact measurement. Keep the original roughness metric, measurement convention and derived parameters together so another engineer can reproduce the choice.

Huray vs Groiss and a Smooth-Copper Baseline

Compare models as modeling choices, not as three interchangeable fields accepting the same number.

Choice	Role	Review caution
Smooth copper	Diagnostic baseline	Not a claim that the physical copper is smooth
Groiss in Ansys 2025 R2	Legacy roughness correction	Frequency-domain limitation documented by Ansys
Huray in Ansys 2025 R2	Causal roughness model	Requires radius and surface-ratio convention
Cannonball-derived inputs	Parameter-estimation approach	Not a separate measurement of the finished interface

These statements refer to the named Ansys implementation. The layer roughness settings documentation explains its available choices. Other solvers may use different names, conventions or corrections, so do not translate settings solely by matching menu labels.

Map Model Values to the Correct Copper Faces

Assign values by physical interface, not merely by a layer name such as “top copper.” A microstrip trace has a face toward the dielectric, a face away from it and etched sidewalls. Its reference plane also participates in the electromagnetic problem.

Draw a simple face map for the hypothetical coupon and identify which supplied value belongs to each interface. Ansys permits separate top, bottom and side settings. “Set all” is a convenience command, not evidence that the three physical surfaces are identical. If only one face is characterized, record the uncertainty rather than quietly copying it everywhere.

Ask for Data That Matches the Manufactured Interface

Request foil identity, side identity, roughness metric and processing context together. The laminate name alone may not identify the exact copper supplied or the state of the surface after subsequent fabrication.

For the coupon, distinguish incoming foil data from information representing the finished stackup. Ask what treatment or processing stage the value describes and whether the modeled face corresponds to it. Keep an input marked “supplier data” separate from one derived by an engineer or fitted to a coupon. Our related microstrip PCB guide provides the wider geometry and reference-plane context.

Build a Sensitivity Study Before Claiming a Prediction

A sensitivity study asks how much the result depends on uncertain inputs; it does not establish which input is true. For the hypothetical RF coupon, hold the verified trace geometry, dielectric model and ports fixed while comparing a smooth baseline with separately documented candidate roughness sets.

Save the baseline model and complete input record.
Change only the selected roughness parameters for each comparison.
Review insertion loss and phase across the same frequency sweep.
Mark which candidates are measured, supplied, derived or hypothetical.
Investigate whether the resulting spread changes the design decision.

No numerical outcome is implied here. If the acceptable design depends on one unverified roughness setting, the next action is better characterization, not a more confident caption on the plot.

RF microstrip test coupons with straight traces and edge connectors on a laboratory bench — AI-generated coupon illustration, not a measured comparison or evidence of factory test capability.

Use Coupon Measurements Without Hiding Other Errors

Measurement comparison must use a defined reference plane and a controlled geometry before it can usefully constrain a material model. A connector transition, calibration issue or incorrect trace width can otherwise be mistaken for roughness loss.

Two line lengths can support a suitable extraction method, but subtracting two arbitrary S21 magnitudes is not automatically a rigorous de-embedding procedure. Check the chosen method’s assumptions, matching, fixture repeatability and frequency behavior. Use independent geometry and dielectric information where possible. Save the measured data, extraction steps and model version so the apparent agreement can be reproduced.

Do Not Fit Roughness and Dielectric Loss Blindly

A good-looking total-loss fit does not prove that the separate loss mechanisms were identified correctly. If both dielectric loss and roughness are freely adjusted, different parameter combinations may explain similar attenuation over a limited band.

Constrain one mechanism with independent evidence before interpreting the other. Review phase as well as loss, and test against a different length or suitable validation structure not used for fitting. If changing geometry or reference-plane assumptions destroys the fit, investigate those assumptions first. Describe a fitted parameter set as a model effective for its validation conditions, not as a universal copper material certificate.

Check Plating, Vias and Return Surfaces Separately

Do not use a roughness factor as a catch-all correction for every conductor-related effect. Surface finishes, plated conductors, etched geometry, vias and reference planes need their own modeling decisions and appropriate evidence.

For the RF coupon, write down which metal stack and interfaces the solver actually represents. If a later design adds a different finish or via transition, revisit the model instead of copying the coupon’s fit unchanged. Applying a trace-surface setting to every conductor is not automatically conservative: it may misrepresent where the fields and currents are concentrated.

Release a Traceable Roughness Model, Not Just a Screenshot

The release record should let another engineer rebuild the same assumptions and identify what remains uncertain.

Solver, version, roughness model and unit convention.
Material and foil identity with source document revision.
Face-by-face assignment and treatment state.
Radius and ratio, labeled supplied, measured, derived or fitted.
Geometry, frequency range, dielectric model and port setup.
Validation data, limits and triggers for rechecking substitutions.

The practical decision is whether that evidence supports the design margin. A completed simulation proves that a model was solved, not that the finished PCB has been validated.

FAQ

Can I use the same Huray values in two different solvers?

Only after checking each solver’s parameter definitions, units, causal treatment and surface assignments. Similar field names do not establish equivalent implementations. Reproduce a simple controlled structure and compare the expected behavior before transferring a production model. Keep the original source and conversion assumptions with both projects rather than copying two unexplained numbers.

Does a lower foil Rz guarantee lower finished channel loss?

No. It is one potentially relevant input, not a channel-level guarantee. Dielectric loss, geometry, copper processing, finishes and transitions can also affect the measured response. Compare matched constructions and methods before attributing the difference to foil texture. Do not replace a complete channel requirement with one roughness statistic on a purchase order.

Should I increase mesh density until the microscopic texture appears?

Not as a substitute for understanding the selected surface model. A model-based correction represents effects that are not explicitly drawn as physical nodules. Follow the solver’s meshing and boundary guidance for the actual structure, then demonstrate convergence. Increasing computational effort does not repair unsupported material parameters or an incorrect face assignment.

Is a fitted roughness value valid for a different surface finish?

Not automatically. The fit may include effects that were not separately identified in the original coupon. A changed finish or metal stack can invalidate that interpretation. Review what the original model represented and repeat the relevant validation rather than treating the fitted value as an intrinsic property independent of manufacturing conditions.

Why can a model match loss but miss resonance frequency?

A loss match does not prove that phase delay and stored-energy behavior were modeled correctly. Geometry, dielectric dispersion, roughness implementation and transitions may need review. Use suitable phase or resonant measurements as additional constraints. Do not change dielectric constant solely to hide a mismatch before checking the physical construction and reference planes.

Can I use a single model for all fabrication lots?

Use it only within the construction and variation envelope that your evidence supports. A material substitution, changed foil treatment or altered fabrication process should trigger review. Define that envelope in the release record and ask how the relevant material identity is controlled. One successful coupon does not establish unlimited lot-to-lot equivalence.

Does the model predict DC resistance accurately from roughness alone?

No. DC resistance still depends on conductor dimensions, conductivity, temperature and the actual current path. A high-frequency surface correction is not a replacement for those inputs. Check the solver’s low-frequency treatment and compare against an appropriate baseline rather than interpreting a Huray radius as a standalone resistance specification.

What should I do when the supplier provides only Rz?

Ask which face and measurement method the value describes, then request a supported model parameter set if available. If you use a published derivation, record its assumptions and label the result as estimated. Carry the uncertainty into sensitivity and validation work; do not relabel the original Rz value as a measured sphere radius.

Technical References

Bert Simonovich: Practical Method for Modeling Conductor Surface Roughness Using Close Packing of Equal Spheres, original method discussion and validation context.
Altium OnTrack interview: Copper Roughness and Signal Integrity, discussion with the model-method developer.

For a Best Technology RF PCB enquiry, send the stackup, foil requirements, simulation assumptions and intended validation scope to sales@bestpcbs.com. Confirm the proposed construction before treating the analysis as representative of the manufactured board.

PCB Return Loss Guide: Read S11 Correctly

November 7th, 2026

For an ordinary passive PCB interconnect, S11 displayed as log magnitude is usually negative, while return loss is conventionally reported as the corresponding positive number. S11 of −20 dB means 20 dB return loss and 1% reflected power at that frequency and reference plane. It does not mean 20 dB of forward signal loss.

This guide follows a hypothetical RF coupon between two coaxial launches. An engineer receives a plot and needs to determine whether it meets a specified reflection limit. The task is to read the quantity, sign, frequency range, and measurement boundary correctly—not to judge a PCB from one attractive marker value.

Illustrative RF PCB coupon with opposing coaxial edge launches — AI-generated physical-product illustration. No measured impedance or RF performance is represented.

What Does S11 Describe on a PCB?

S11 describes the reflected wave at port 1 relative to the incident wave at port 1 under the defined network conditions. It is a complex quantity, carrying magnitude and phase. The familiar negative-dB curve shows a transformation of its magnitude, not the complete complex result.

Keysight’s measurement-parameter documentation distinguishes reflection parameters S11 and S22 from transmission parameters S21 and S12. The port labels matter: a curve cannot be interpreted reliably without knowing where excitation and measurement occur and how the other ports are terminated.

Detailed S11 and Return-Loss Parameters

Write down the parameter definition before comparing a plot with a requirement. For equal real reference impedances in the usual passive interconnect context, use the following relationships. Here Γ denotes the input reflection coefficient and log means base 10.

S11 log magnitude: 20 log(|Γ|), in dB.
Return loss: −20 log(|Γ|), in dB.
Reflected power fraction: |Γ|² = 10^−RL/10.
Record the reference impedance, frequency, calibration plane and termination conditions with every result.

S11 (dB)	RL (dB)	\|Γ\|	Power back
−6 dB	6 dB	0.5012	25.12%
−10 dB	10 dB	0.3162	10%
−20 dB	20 dB	0.1000	1%
−30 dB	30 dB	0.03162	0.1%

These are calculated conversions, not PCB acceptance limits or measured results. The Teledyne LeCroy explanation of S-parameter terminology discusses the sign convention and the distinction between reflection and transmission.

Why More Negative S11 Means Less Reflection

A smaller reflected-to-incident wave ratio has a more negative logarithm. Therefore −30 dB S11 indicates less reflected power than −10 dB S11 at the same measurement conditions. Under the positive return-loss convention, the same comparison becomes 30 dB versus 10 dB.

Avoid saying only “lower return loss is better” or “higher S11 is better.” Name the plotted quantity. For our coupon, a specification of RL ≥20 dB corresponds to S11 log magnitude ≤−20 dB. These are the same reflection requirement written in two conventions, not competing performance targets.

Return Loss vs Insertion Loss

Return loss concerns reflected signal; insertion loss concerns reduction in forward transmission under the stated reference conditions. Their desirable directions differ. A positive return-loss value should usually be large, while a positive insertion-loss value should usually be small for a transparent interconnect.

Quantity	Usual passive log-magnitude view	What a transparent path aims for
S11	Negative dB reflection trace	Small reflection magnitude
Return loss	Positive counterpart of S11 log magnitude	Larger positive value
S21	Forward transmission, often negative dB	Near 0 dB within the intended band
Insertion loss	Positive loss derived under stated conditions	Smaller positive value

For the broader forward-loss question, see the RF PCB insertion-loss guide. Do not substitute that quantity for the reflection criterion.

A Worked Power Example for an RF Coupon

Suppose a hypothetical passive two-port coupon has S11 = −20 dB and S21 = −3 dB at one frequency, with equal real reference impedances and a matched output. The calculated reflected fraction is 10^−20/10 = 0.01, or 1%. The forward transmitted fraction is 10^−3/10 ≈0.5012, or 50.12%.

About 48.88% remains outside those reflected and transmitted terms in this example. Do not automatically call all of it dielectric heating: losses, radiation, unmodelled paths and measurement limitations need consideration. The lesson is that little reflection does not guarantee nearly complete forward transmission. This is a teaching calculation, not a test report.

Judge the Whole Required Frequency Band

A reflection limit applies over the specified band unless the requirement says otherwise. One deep S11 minimum can coexist with poor matching elsewhere. A marker placed at the best point cannot demonstrate compliance across an operating range.

For the coupon, record the band endpoints and the worst result within that interval. Under the positive return-loss convention, the weakest point is the smallest RL. Under the negative S11 log-magnitude convention, it is the point closest to 0 dB. Check the same band when comparing two revisions or suppliers.

Keep the Reference Impedance Attached to the Result

S11 is referenced to a defined port impedance. A result normalized to one reference cannot be compared casually with a different reference. The relevant value should come from the measurement setup, model, or supplied network data rather than an assumption based on connector appearance.

A nominally 50-ohm test system does not prove that every part of the physical coupon is 50 ohms. It defines a reference for evaluating the structure. If data are renormalized, record that transformation and its basis. Do not describe a changed reference as a physical improvement to the board.

Know Whether the Launches Are Inside the Measurement

The calibration and de-embedding boundary determines which structures the reported network includes. A measurement can contain cable adapters, connectors, launches and PCB traces, or represent a narrower region after an appropriate correction.

In our example, decide whether the requirement applies to the entire connectorized coupon or the trace region alone. Do not blame laminate properties from a launch-inclusive reflection result without further evidence. The related PCB fixture de-embedding guide explains the separate boundary question. A correction must be validated; it is not merely a cosmetic plot adjustment.

Illustrative RF coupon, coaxial cable and calibration accessories on a lab bench — AI-generated laboratory illustration, not an actual calibration or measurement record.

Why S11 and S22 Can Tell Different Stories

S11 looks into port 1; S22 looks into port 2. A structure with different launches or asymmetric discontinuities can present different reflection behavior from its two ends. Label the physical ports clearly before comparing curves.

Do not assume that similar forward and reverse transmission establishes identical input and output matching. In the controller’s RF path, the installed orientation can make the relevant end especially important. Record both reflection parameters when the test plan requires them and use the specified termination conditions rather than an undocumented open connector.

Single-Ended S11 Is Not Differential Return Loss

A differential interconnect needs the appropriate mixed-mode parameter and port definition. An individual single-ended S11 trace does not by itself describe the differential pair’s reflection behavior. Confirm the pairing, polarity and normalization used in the model or measurement.

Do not relabel a single-ended curve as SDD11 to match a requirement. Request the correct data or a documented conversion from a complete suitable multiport dataset. Keep the scope of this guide clear: the earlier numeric example is an ordinary single-ended two-port example, not a differential-channel qualification.

Investigate a Poor Result Without Guessing the Cause

Check the measurement configuration and repeatability before assigning a PCB defect. Verify connections, calibration applicability, port labels, data format, band and reference plane. Then compare the structure with its released design and any validated model.

A reflection feature can be associated with launches, geometry changes, vias, termination or other discontinuities. The S11 magnitude alone does not uniquely identify which one is responsible. Use additional evidence—such as a controlled comparison or an appropriate time-domain analysis—rather than announcing a root cause from the curve’s shape.

Report a Reflection Requirement Without Sign Ambiguity

A useful report names the quantity, inequality, band, reference impedance and measurement boundary. For example: “Calculated teaching requirement: return loss ≥20 dB across the stated band; equivalent S11 log magnitude ≤−20 dB.” Replace the example threshold with the actual approved requirement.

Include the dataset, setup notes and relevant uncertainty or validation limitations. For our coupon, release requires the agreed evidence across the band, not a universal “good S11” number. Keep forward transmission and other channel requirements in their own acceptance checks so one passing metric cannot conceal another failing one.

FAQ

Is −10 dB S11 better or worse than −20 dB?

For the ordinary passive reflection comparison at the same frequency and conditions, −20 dB indicates less reflection. It corresponds to 1% reflected power, versus 10% at −10 dB. Whether either result is acceptable depends on the actual requirement and operating band. Do not turn these conversion examples into universal PCB pass limits.

Why does a report call a negative trace return loss?

People sometimes use return loss informally to refer to an S11 log-magnitude plot. Read the axis, instrument format and stated formula before applying an inequality. If the report is ambiguous, ask the author to name the quantity explicitly. Changing a label without clarifying its definition can reverse an acceptance decision.

Does a 20 dB return loss mean 99% reaches the output?

No. It means 1% is reflected under the stated conditions. The remaining power is not necessarily all delivered through the intended output; dissipation, radiation or other paths may matter. Check the relevant transmission measurement separately. A well-matched attenuating structure is a useful reminder that input matching and forward transmission are different properties.

Can I add return-loss dB values along a channel?

Not as a general channel calculation. Reflections interact with phase and multiple discontinuities, so scalar return-loss numbers do not preserve enough information to predict the cascade. Use suitable complete network data and a validated connection model. Keep reference impedances, port orientation and measurement boundaries consistent when evaluating the combined structure.

Is dB the same as dBm on an RF plot?

No. A ratio expressed in dB is not an absolute power level in dBm. S11 log magnitude describes a wave ratio, while a receiver power readout can be an absolute quantity. Check the selected measurement and units before converting numbers or comparing them with a reflection specification. Similar-looking axes can represent different physical questions.

What if S11 appears above 0 dB?

First establish the device and measurement context. An active network is not covered by the simple passive assumptions used here. For an expected passive interconnect, examine calibration, processing, reference definitions and uncertainty before drawing conclusions. Do not merely flip the sign or delete inconvenient points to make the curve resemble a typical passive result.

Does a Smith chart contradict the negative-dB trace?

Not necessarily. A Smith chart displays complex reflection information in a different representation. A log-magnitude plot discards phase and shows only a magnitude transformation. Verify that both use the same frequency, port, reference impedance and dataset before comparing them. One view may reveal information that the other deliberately does not display.

What should a supplier send with a return-loss plot?

Request the measured structure identity and revision, port map, frequency range, reference impedance, calibration or de-embedding boundary, and the underlying data where available. Ask how the reported quantity and limit are defined. This makes the plot reviewable and prevents confusion between a connectorized coupon, a corrected trace model and a complete installed channel.

References and RF Enquiries

The linked Keysight and Teledyne LeCroy documentation supports the parameter definitions and sign conventions; the numerical examples are calculated and explicitly hypothetical. For a Best Technology RF PCB enquiry, send the stackup, geometry and measurement requirement to sales@bestpcbs.com. Specific fabrication and verification scope require confirmation.

Cookie	Duration	Description
cookielawinfo-checkbox-analytics	11 months	This cookie is set by GDPR Cookie Consent plugin. The cookie is used to store the user consent for the cookies in the category "Analytics".
cookielawinfo-checkbox-functional	11 months	The cookie is set by GDPR cookie consent to record the user consent for the cookies in the category "Functional".
cookielawinfo-checkbox-necessary	11 months	This cookie is set by GDPR Cookie Consent plugin. The cookies is used to store the user consent for the cookies in the category "Necessary".
cookielawinfo-checkbox-others	11 months	This cookie is set by GDPR Cookie Consent plugin. The cookie is used to store the user consent for the cookies in the category "Other.
cookielawinfo-checkbox-performance	11 months	This cookie is set by GDPR Cookie Consent plugin. The cookie is used to store the user consent for the cookies in the category "Performance".
viewed_cookie_policy	11 months	The cookie is set by the GDPR Cookie Consent plugin and is used to store whether or not user has consented to the use of cookies. It does not store any personal data.

PCB Ground Bounce: Isolate the Glitch Before a Respin

what is ground bounce

what causes ground bounce

simultaneous switching noise

oscilloscope probe ground spring

ground bounce measurements

simultaneous switching noise analysis

decoupling capacitor placement

pcb ground plane rules

FAQ

Can a long scope ground lead create a false ground-bounce trace?

Is ground bounce the same as supply droop?

Why does the low output move if it never toggles?

Does slowing the clock eliminate ground bounce?

Should I add a larger decoupling capacitor first?

Is ground bounce always worse on a two-layer PCB?

Can I use two passive probes to measure between grounds?

What waveform proves the fix worked?

Technical References

Request a Fabrication Review

You may also like

Thermal Via Solder Wicking: Protect the QFN Pad Joint

thermal via solder wicking

thermal pad via design

thermal vias size and spacing

should thermal vias be tented

thermal via filling

via in pad plated over

qfn ground pad stencil design

qfn solder void

FAQ

Does every open thermal via wick solder?

Is tenting on the bottom the same as a filled and capped via?

Can I simply reduce the amount of paste to stop wicking?

Why are there solder deposits on the opposite side of the board?

Can a large void prove the exposed pad is not soldered?

Will resin-filled vias provide the same thermal result as copper-filled vias?

What must I tell the fabricator before selecting a via treatment?

Should I compare a modified stencil using the same assembly process?

Discuss Your Project

You may also like

PCB Trace Delay

pcb propagation delay formula

pcb propagation delay per mm

fr4 pcb propagation delay

Microstrip vs. stripline for timing

pcb propagation delay calculator

FAQ

Is propagation delay the same thing as impedance?

Should I use 150 ps/in for every FR-4 trace?

Does equal PCB length guarantee that two signals arrive together?

Do I include the device package delay in length tuning?

How does a via enter a propagation-delay budget?

Can a faster rise time change which delay estimate I should use?

Should I measure a connector and trace together?

How should I convert a skew budget into a length tolerance?

Discuss Your Project

You may also like

TDR Resolution

Separate detection from resolution

Record the parameters that set the test

Compare three different measurement claims

Convert spacing to an echo interval

Test the two-feature teaching example

Treat rise-time rules as screening only

Account for the path before the device

Check the effect of polarity and magnitude

Avoid confusing oversampling with bandwidth

Use an edge sweep as a diagnostic comparison

Validate a coupon against the intended question

Report uncertainty instead of inventing a second location

FAQ

Does seeing one bump mean there is one defect?

Can a TDR see a feature smaller than its quoted resolution?

Does averaging make two reflections easier to separate?

Should I test at the fastest available edge?

Can a VNA time-domain plot answer the same question?

Is a launch artifact always removed by calibration?

Can the impedance coupon prove an assembled channel will pass?

What should a report say when separation is borderline?