IPC 620: Wire Harness Classes, Inspection and Testing

October 16th, 2026

IPC 620 is the commonly used name for IPC/WHMA-A-620, the requirements and acceptance standard for cable and wire harness assemblies. It addresses workmanship in wire preparation, crimped and soldered connections, connector assembly, and associated inspection and testing. For a production order, the useful reference is not simply “IPC compliant”: it is the agreed revision, product class, drawing, and test requirements. Those details determine how an assembly is evaluated. At EBest Circuit, we supply custom wire harnesses alongside PCB and PCBA services, helping customers coordinate the cable and board connections in one manufacturing project.

Wire harness with crimp terminal, connector lock and cable protection callouts

Key Takeaways

IPC 620 refers to IPC/WHMA-A-620, a cable and wire harness manufacturing and acceptance standard—not a bare PCB acceptance standard.
Class 1, Class 2 and Class 3 distinguish end-use performance needs; the class is not a wire gauge or a connector current rating.
The official English F revision is dated October 2025. The revision specified for the order governs acceptance; a new edition does not automatically change an existing contract.
Crimp height, wire size, terminal identity and pull-test results must be considered together. A single pull-force result cannot describe the entire termination.
Continuity checks establish electrical connections. They do not establish contact retention, insulation condition or the performance of a complete powered system.
IPC 620 certification usually refers to personnel training and assessment. It does not replace inspection and test evidence for the delivered harness.
For a harness connected to a PCBA, inspect both sides of the interface: the cable pinout and terminals, and the board connector orientation and solder joints.

What Does the IPC 620 Standard Cover?

The IPC 620 standard covers the manufacture and acceptance of cable and wire harness assemblies, including crimped, soldered and mechanically secured interconnections. Our wire harness assembly guide explains the production steps behind these inspection points. Its purpose is to give the customer and assembler a shared basis for judging workmanship.

A useful way to understand its role is to separate the finished cable from the circuit board and from the manufacturing process used to join parts:

Document	Main application
IPC/WHMA-A-620	Cable and wire harness requirements and acceptance
IPC-A-610	Acceptance of electronic assemblies, including assembled PCBs
J-STD-001	Requirements for soldered electrical and electronic assemblies
IPC-D-620	Cable and wiring harness design and critical process requirements

For example, a cable plugged into a board-mounted header creates two inspection tasks. The cable terminals and housing belong to the harness inspection; the header’s solder connections belong to the board assembly inspection. Specifying A-620 alone does not define every aspect of the finished electronic product.

What Are IPC 620 Classes 1, 2 and 3?

Class 1 prioritizes basic product function, Class 2 addresses sustained service, and Class 3 addresses critical operation or demanding environments. The following IPC 620 Class 1 2 3 definition summary is a practical orientation, not a replacement for the standard’s detailed acceptance criteria.

Class	Performance priority
Class 1	The completed assembly performs its intended function.
Class 2	Longer service life and continued operation matter; interruption is undesirable but not critical.
Class 3	Operation when needed is critical, downtime is unacceptable, or service conditions are unusually demanding.

Select the class from the product’s actual failure consequences. A monitoring accessory and an emergency control circuit may be installed in the same machine yet have different reliability needs. An industry label such as “industrial” or “medical” is not enough to settle the requirement.

The practical manufacturing consequence is that inspectors need the class before evaluating a questionable condition. Changing it after samples are approved can change acceptance decisions and create avoidable rework.

What Is the Current Version of IPC 620?

The official English IPC/WHMA-A-620F publication is dated October 2025, superseding revision E. This version information was checked on October 16, 2026 against the Global Electronics Association’s public publication material.

A drawing that specifies revision E should not silently be changed to F. Resolve the revision with the customer and record the decision before production. The drawing revision and the standard revision are separate fields: updating a connector position on a drawing does not automatically update the acceptance standard.

What Should Be Checked on a Crimped Connection?

Check the terminal and wire combination, conductor capture, insulation support, crimp dimensions and mechanical strength. These checks answer different questions and should not be reduced to “the wire did not pull out.”

Part match: confirm the terminal part number, conductor size, insulation diameter and specified tooling.
Wire preparation: look for cut strands, spreading strands and insulation caught in the conductor crimp.
Conductor crimp: check the formed barrel and measure height where required by the applicable application specification.
Insulation support: verify that the rear support grips the jacket without damaging it.
Mechanical evidence: use the specified pull-test setup; unintended support from the insulation grip can distort the result.

Illustrative open-barrel terminal showing the conductor crimp and separate insulation support

Molex’s application-tooling guidance directs users to the tooling specification for crimp height, pull force and strip length. That is a useful production discipline: a value copied from another terminal family is not a valid setup instruction merely because the wire gauge matches.

Suppose two approved 18 AWG wires have different insulation materials or strand constructions. A change between them can affect stripping and crimp formation even though both carry the same gauge designation. Review the exact combination before treating the substitution as interchangeable.

How Should Soldered Wire Terminations Be Inspected?

Inspect the wire placement, wetting, insulation condition, clearance and mechanical support around the soldered termination. A shiny surface alone does not establish a sound connection.

For a solder-cup termination, examine whether the conductor is positioned inside the cup and whether solder has joined the conductor to the terminal. Also look beyond the joint:

Excess solder must not bridge adjacent contacts.
Heat must not leave the wire jacket melted or displaced.
Solder wicking should not create an unsupported rigid section where the wire must repeatedly bend.
Sleeving must cover the intended exposed area without obstructing connector assembly.

Illustrative solder-cup wire termination with insulation and separate heat-shrink sleeve

Use the applicable acceptance criteria for the actual terminal style. A cup, a turret and a through-hole board connection do not have identical geometry. When the harness is integrated with our PCB assembly service, the cable connection and board-side solder joints need their own inspection coverage.

What Connector and Routing Problems Can Inspection Miss?

A harness can have the correct pin-to-pin connections while still containing an unseated contact, an incomplete lock or a branch under mechanical strain. Electrical continuity does not reveal every assembly problem.

Contact seating: verify that the terminal has reached its intended position and engaged the retention feature.
Lock position: inspect the secondary lock where the connector design uses one.
Orientation: identify the mating face and wire-entry face before checking cavity numbers.
Routing: check branch exits, service movement and contact with sharp enclosure edges.
Protection: confirm that ties and sleeving do not crush the jacket or leave a planned wear point exposed.

Illustrative connector cutaway showing contact seating, a secondary lock and wire routing

A useful first-article check is to fit the harness to its actual mating components. A flat drawing can miss an inaccessible latch or an awkward branch exit. Record any agreed routing change in the drawing rather than leaving it as an unwritten instruction to the next production operator.

Which Electrical Tests Matter for a Wire Harness?

Continuity and isolation checks verify the wiring network; insulation-resistance and dielectric-withstand tests address insulation performance when applicable. The test plan must match the assembly, including any electronic components already connected to it.

Test	What it checks	Recorded quantity
Continuity	Expected pin-to-pin connections	Resistance in Ω, or connection result
Short-circuit check	Unintended connections between separate nets	Net-pair result against the programmed limit
Insulation resistance	Leakage through insulation between isolated conductors	Resistance in MΩ at a stated test voltage
Dielectric withstand	Ability to withstand the specified electrical stress	Voltage, leakage limit and dwell time

Cable harness connected to test adapters for continuity, short-circuit and insulation checks

Do not copy a voltage from a generic cable-testing chart into a program for an assembly containing sensors, LEDs or protection devices. Determine whether the cable should be tested separately, which nets may be energized and what limits protect the connected components.

A simple four-wire example shows why the netlist matters: a cable can pass four individual continuity measurements yet still have two adjacent wires shorted together. The program must check intended connections and unintended connections, not only whether each wire conducts.

How Can Inspection Results Support Repeatable Production?

Connect each result to the drawing revision, component combination, setup and test program used to build the harness. A pass label without that context is difficult to investigate when a later batch behaves differently.

For a practical production record, capture:

The harness part number, drawing revision and agreed acceptance requirements.
The terminal and wire identifiers used for the build.
The tooling setup and required measurements or sample tests.
The electrical test program revision and results.
Any rework, approved deviation and subsequent verification.

If a pull-test result deteriorates, compare it with crimp measurements and material changes. If only one connector position fails continuity, examine that cavity, its terminal and the test fixture contact. This narrows the investigation more effectively than repeating the entire assembly process without a hypothesis.

What Does IPC 620 Certification Mean?

IPC 620 certification commonly means that an individual has completed a standards-based training and assessment program, such as Certified IPC Specialist (CIS). It is different from a test report for a particular batch of cable assemblies.

The Global Electronics Association distinguishes introductory operator training from its standards-based CIS program. When checking a credential, identify the program, holder, relevant standard and current validity rather than relying on a statement that a supplier is “IPC certified.”

For purchasing, request two different kinds of evidence: personnel qualifications where your project requires them, and product-specific inspection or test records. Neither is a substitute for the other.

FAQ About IPC 620

What is the difference between IPC 610 and IPC 620?

IPC-A-610 addresses acceptance of electronic assemblies, while IPC/WHMA-A-620 focuses on cable and wire harness assemblies. An electronic product containing a PCBA and a separate harness may use both, with the applicable document identified for each assembly.

What affects IPC 620 certification cost?

IPC 620 certification cost depends on the selected program, training provider, delivery format, included modules and whether materials or examination fees are included. Request a current itemized course price; a standards-document purchase is not the same as a certification course.

Can a pull test replace visual crimp inspection?

No. A pull test measures mechanical strength under its test conditions. It does not by itself confirm correct terminal identity, insulation support, connector fit or the absence of visible damage. Use it alongside the other checks specified for the termination.

Does a Class 3 harness automatically meet every industry requirement?

No. A product class does not establish the harness’s current rating, sealing performance, chemical resistance or suitability for a specific regulated application. Those requirements depend on the design, component ratings, qualification plan and applicable customer or industry specifications.

Does a normal multimeter fully test a finished harness?

No. A multimeter can help find basic opens and incorrect connections, but it does not automatically execute a complete netlist or perform dielectric-withstand testing. Select the test equipment and fixtures from the defined test plan, particularly for multi-connector assemblies.

How Can EBest Circuit Support Your Harness and PCBA Project?

At EBest Circuit, we offer custom wire harnesses, PCB fabrication, component sourcing and PCB assembly. Bringing the cable and board requirements together helps us review connector compatibility, pin assignments and assembly access before manufacturing.

If your project specifies IPC/WHMA-A-620, send the required revision and class with your harness drawing and test requirements to sales@bestpcbs.com. We will review the scope with you and identify the manufacturing and verification requirements for your project.

IPC-1783-CO2E: New Standard for PCB & PCBA Carbon Footprint Data

October 13th, 2026

IPC-1783-CO2E, officially released by the Global Electronics Association on October 8, 2026, introduces a standardized approach to collecting and reporting carbon emissions data across the electronics manufacturing supply chain. But it raises an important question: If two PCB manufacturers report different carbon footprints for the same circuit board, how can customers tell whether one produces fewer emissions or simply counts them differently?

What Is the Newly Released IPC-1783-CO2E Standard?

IPC-1783-CO2E is the International Standard for Data Collection and Reporting of CO2 Equivalent (CO2e) Emissions for the Electronics Manufacturing Supply Chain. It provides electronics-specific guidance on what emissions information should be measured, estimated, collected, and reported for subsequent product carbon footprint calculations.

Unlike manufacturing specifications that establish physical or performance requirements for circuit boards, IPC-1783-CO2E focuses on emissions data and how that information is developed and reported. Its published description includes methodology choices and associated data quality indicators.

The standard is intended for use across the electronics manufacturing supply chain, including PCB fabrication, electronic component production, PCB assembly, and other manufacturing activities that contribute to finished electronic products.

For example, a bare PCB and a fully assembled PCBA involve different materials and production processes. Each contributes to the carbon footprint of the final device, but the underlying emissions information must reflect the activities associated with that particular stage of manufacturing.

IPC-1783-CO2E, https://www.bestpcbs.com/blog/2026/10/ipc-1783-co2e/

Why Was IPC-1783-CO2E Introduced?

Electronics manufacturers increasingly receive requests for product carbon footprint data from customers, procurement teams, and supply chain partners. The challenge is that different suppliers may use different data sources, assumptions, and accounting methods.

Consider two manufacturers producing the same PCB design. Both report their results in kilograms of CO2 equivalent per board.

Manufacturer A includes laminate production, copper materials, and PCB fabrication activities.
Manufacturer B calculates emissions using only electricity consumed during PCB fabrication.

Manufacturer B might report a much smaller figure, even though the difference comes primarily from the activities included in the calculation rather than more efficient manufacturing.

This is one of the problems IPC-1783-CO2E is designed to address. The standard provides a shared approach to developing and reporting emissions information so that customers can better understand how the data was produced.

A lower reported carbon footprint does not automatically mean a lower-emission product. Meaningful comparisons require appropriate product definitions, accounting boundaries, and calculation methods.

What Does CO2e Mean for PCB and PCBA Products?

CO2e stands for carbon dioxide equivalent, a unit that expresses the climate impact of different greenhouse gases using their global warming potential over a specified time horizon.

In PCB manufacturing, CO2e represents estimated greenhouse gas emissions associated with materials and manufacturing activities included in a defined assessment. It does not refer to the physical carbon content of a circuit board.

The reporting unit depends on what is being assessed.

Reporting Basis	What It Represents
kg CO2e per bare PCB	Emissions associated with one specified unpopulated circuit board
kg CO2e per PCBA	Emissions associated with one specified populated circuit board assembly
kg CO2e per m² of PCB	Emissions normalized to a defined PCB area

These units describe product-related results, but the unit alone does not reveal which manufacturing or life cycle stages were included.

A product carbon footprint is also different from a company’s greenhouse gas emissions inventory.

A product carbon footprint accounts for emissions associated with a defined product over its specified life cycle stages. A corporate emissions inventory records greenhouse gas emissions associated with an organization and its defined activities and value chain, often reported annually.

For example, a PCB factory may report its annual electricity-related emissions as part of its corporate inventory. A product-level assessment instead determines how the relevant emissions contribute to a particular PCB within the selected accounting boundary.

This distinction matters when customers request carbon information for individual boards rather than a manufacturer’s overall environmental performance.

What Does IPC-1783-CO2E Cover in Carbon Data Collection and Reporting?

IPC-1783-CO2E provides guidance for collecting and reporting information used in product-level CO2e calculations. Its published scope includes choices of methodology and associated data quality indicators.

To understand how this works in a manufacturing environment, four accounting elements are particularly useful.

Accounting Element	Manufacturing Example
Activity data	Electricity consumed, material quantities, or production output
Emission factors	Values used to estimate greenhouse gas emissions from a measured activity
Allocation methods	Approaches for assigning shared resource consumption to specific products
Data quality	Information about the reliability and representativeness of the underlying data

These are practical accounting concepts, rather than a complete list of mandatory requirements reproduced from the standard.

How does a PCB manufacturer turn production data into a CO2e figure?

Consider a simplified example in which a PCB production batch uses 1,000 kWh of attributable electricity. Assume an illustrative emission factor of 0.40 kg CO2e/kWh.

The estimated electricity-related emissions would be:

1,000 kWh × 0.40 kg CO2e/kWh = 400 kg CO2e

If all 400 kg CO2e were allocated to 2,000 accepted circuit boards, the result would be:

400 kg CO2e ÷ 2,000 boards = 0.20 kg CO2e per board

This is a hypothetical calculation for a single electricity-related contribution, not a complete PCB carbon footprint or an emission factor prescribed by IPC-1783-CO2E. A broader assessment would include other relevant activities and inputs according to its defined boundary.

The important consideration is whether the electricity consumption, emission factor, output quantity, and allocation approach can be supported by appropriate records.

What Carbon Footprint Data Matters in PCB Manufacturing?

PCB carbon footprint data is closely connected to the materials used and the processes required to manufacture a board.

A two-layer FR4 PCB, a multilayer rigid board, and a metal core PCB have different material structures and manufacturing requirements. Their emissions contributions cannot be accurately represented by assuming that every circuit board follows the same production route.

Material consumption is one important source of product-level information. PCB manufacturers can identify the laminate, prepreg, copper foil, metal substrates, and other materials associated with a released design. Material quantities, supplier information, and production records can support the assessment of relevant upstream inputs.

Manufacturing operations contribute additional data. Depending on the board construction, these may include drilling, lamination, imaging, electroplating, etching, surface finishing, and other fabrication processes.

Energy use and shared services may also need to be allocated across production orders. In a facility producing multiple PCB types, electricity consumption from compressed air systems, production equipment, and supporting operations cannot always be attributed to one product through a direct measurement.

Production yield is another practical consideration. If a manufacturing order requires additional panels because of scrap or rejected boards, more materials and processing activity may be needed to produce the same accepted quantity.

For long, narrow PCBs and other boards with demanding dimensional requirements, panel utilization and manufacturing yield can influence material consumption per finished unit.

Connecting these records to the actual PCB design, fabrication route, and accepted production quantity gives manufacturers a stronger basis for preparing product-specific emissions information.

What Additional Carbon Footprint Data Matters in PCBA Production?

PCBA manufacturing introduces electronic components and assembly operations that are absent from bare-board fabrication.

A populated circuit board may contain integrated circuits, resistors, capacitors, connectors, power devices, and other components sourced from multiple suppliers. Their upstream emissions can form part of the assembly’s product carbon footprint, depending on the selected accounting boundary.

The approved Bill of Materials (BOM) provides an important starting point for identifying component inputs. It defines which components and quantities belong to the released assembly. Where supplier-specific emissions data is unavailable, an applicable carbon accounting methodology may permit appropriate estimates using secondary information.

Assembly operations add another category of activity. Relevant processes may include solder paste printing, SMT placement, reflow soldering, selective soldering, inspection, programming, and functional testing.

The actual process route matters. For example, a PCBA requiring extended powered burn-in may involve different electricity consumption from an assembly that undergoes only a short functional test.

Rework, process losses, solder materials, and protective coatings may also affect the assessment when they fall within its defined boundary.

An important accounting consideration is avoiding double counting when combining the bare PCB contribution with component and assembly data.

If the bare PCB figure already includes laminate production and fabrication, those same activities should not be added again as separate contributions to the assembled product.

The resulting PCBA information should represent the specified assembly configuration and the life cycle stages covered by its calculation.

How Does IPC-1783-CO2E Relate to Existing Carbon Accounting Frameworks?

IPC-1783-CO2E was developed with reference to established greenhouse gas accounting principles, including those associated with the Greenhouse Gas Protocol and ISO.

However, these frameworks serve different purposes.

Standard or Framework	Primary Focus
IPC-1783-CO2E	Collecting and reporting emissions data within the electronics manufacturing supply chain
GHG Protocol Corporate Standard	Accounting for greenhouse gas emissions at the organizational level
GHG Protocol Product Standard	Quantifying and reporting greenhouse gas emissions associated with individual products
ISO 14067	Requirements and guidelines for quantifying and reporting product carbon footprints

The GHG Protocol’s corporate accounting framework categorizes emissions into Scope 1, Scope 2, and Scope 3.

Scope 1: Direct emissions from sources owned or controlled by the reporting company.
Scope 2: Indirect emissions associated with purchased electricity, steam, heating, or cooling.
Scope 3: Other indirect value-chain emissions, including relevant purchased goods and services.

For example, emissions arising from a PCB manufacturer’s operations can contribute to that manufacturer’s corporate inventory. Relevant emissions associated with purchasing those boards may also contribute to a customer’s Scope 3 inventory.

Product carbon footprint accounting takes a different perspective. It evaluates emissions associated with a particular product and the activities included within the defined life cycle boundary.

IPC-1783-CO2E supports the collection and reporting of electronics-specific data that may be used within these broader accounting approaches. It should not be treated as a replacement for a complete product carbon footprint methodology such as ISO 14067.

Even when suppliers use recognized accounting frameworks, direct product comparisons require additional care. Equivalent product functions, consistent boundaries, appropriate data quality, and applicable product-category rules may all be necessary to support a meaningful comparison.

What Does IPC-1783-CO2E Mean for the PCB and PCBA Industry?

The release of IPC-1783-CO2E introduces a more defined reference for electronics companies responding to product-level carbon footprint requests.

For PCB and PCBA manufacturers, implementation may involve connecting existing production information with emissions-related records. Board specifications, BOM revisions, material consumption, manufacturing routes, and production quantities can all help establish what was actually manufactured.

For procurement teams, the change is particularly relevant when evaluating supplier-reported carbon data.

Rather than accepting a standalone CO2e number, buyers can request supporting information about the identified product, data sources, reporting period, and activities included in the calculation. This makes it easier to assess whether the information meets the requirements of their own reporting process.

Engineering teams also have a role. Changes in board materials, PCB stackups, component selections, or assembly processes can affect the underlying activity data. Keeping the product definition aligned with the production records helps identify which inputs may require reassessment.

IPC-1783-CO2E does not establish a universal carbon emission limit for PCBs or automatically demonstrate that a product has a lower environmental impact. Its value lies in improving the way relevant emissions data is developed and communicated.

For the electronics industry, more reliable manufacturing information can support product carbon footprint calculations, supply chain reporting, and the evaluation of potential emission reduction opportunities.

Frequently Asked Questions About IPC-1783-CO2E

Q1: Where Can I Obtain the Official IPC-1783-CO2E Standard?

The official IPC-1783-CO2E-2026 standard is available through the Global Electronics Association’s standards store and ANSI Webstore. For a free overview, read the official release announcement.

Q2: Is IPC-1783-CO2E Mandatory for Every PCB Manufacturer?

No, its publication does not make it universally mandatory; applicable customer requirements, contracts, and regulatory obligations determine whether it must be used.

Q3: Does IPC-1783-CO2E Set Carbon Emission Limits for Circuit Boards?

No, IPC-1783-CO2E addresses emissions data collection and reporting rather than establishing universal carbon emission limits for PCBs.

Q4: Does ISO 14001 Certification Replace Product Carbon Footprint Data?

No, ISO 14001 addresses environmental management systems and does not replace product-specific greenhouse gas emissions accounting.

Q5: How Often Should Product Carbon Footprint Data Be Updated?

The review frequency depends on the applicable accounting method and customer requirements, with reassessment appropriate when significant materials, processes, or data assumptions change.

Q6: Does Using IPC-1783-CO2E Mean a Product Is Carbon Neutral?

No, using IPC-1783-CO2E does not demonstrate carbon neutrality, which requires separate assessment and substantiation.

IPC-1783-CO2E marks an important development in how the electronics manufacturing supply chain collects and reports emissions information. For PCB and PCBA projects, accurate product definitions, manufacturing records, and appropriate accounting methods provide the foundation for meaningful carbon footprint data.

For PCB fabrication, component sourcing, and assembly projects, send your Gerber files, BOM, quantities, and manufacturing requirements to sales@bestpcbs.com. Our engineering team can review your production requirements and provide technical support and a quotation.

How an IPC-356 Netlist Catches PCB Connection Errors

September 27th, 2026

An IPC-356 netlist gives PCB manufacturers a reference for which board connections belong together and which must remain separate. Comparing that reference with the copper and drill data can reveal a missing connection or unintended short before fabrication. After manufacturing, the connectivity data also supports electrical testing of the physical bare board.

EBest Circuit supports PCB fabrication, manufacturing-data review and bare-board electrical testing, with component sourcing and PCBA assembly available for the next stage. If your board is ready for fabrication, send your manufacturing files to sales@bestpcbs.com to discuss the build and its electrical test requirements.

What Is an IPC-356 Netlist?

An IPC-356 netlist is a standardized text file that describes the electrical connectivity of a PCB. A net is a group of connection points intended to share the same electrical connection, such as a ground network or a signal running between two component pads.

The file associates those points with physical information, including their locations on the board. This lets manufacturing software relate an electrical connection to an actual pad, hole or accessible test location.

For example, if connector pin J1-1 and component pad R1-1 belong to the same net, the bare PCB should provide a conductive path between them. A nearby pad on a different net should remain electrically separate unless the design includes an intentional connection.

The name is often shortened to IPC-356, while PCB software may label the export IPC-D-356 or IPC-D-356A. It is a manufacturing and test-data format, not a complete PCB design file. It does not replace the copper artwork, drill files or fabrication drawing.

How Does the IPC-D-356 Netlist Format Describe PCB Connections?

The IPC-D-356 netlist format uses structured text records to identify connection points and their net membership. The fields let CAM and test software locate those points without opening the original PCB design application.

Information	What it identifies
Net name	The electrical network assigned to a point
Reference and pin	The component location and pin or pad identifier, where applicable
X and Y coordinates	The point’s position on the PCB
Access information	The board side or layer information used to locate the connection
Pad and hole details	Physical features associated with the point, where exported

Think of the file as a connectivity map rather than a drawing of every copper track. Two pads may be far apart and connected through several layers, yet still belong to one net. The netlist identifies their relationship; the copper and plated-hole data describe the physical route.

A simple example: J1-1 and R1-1 are assigned to SIGNAL_A, while J1-2 is assigned to GND. A comparison should find J1-1 connected to R1-1 and separate from J1-2. If the extracted copper network combines all three, it disagrees with the intended grouping.

That example describes the meaning of the records, not the literal file syntax. Actual records use defined field positions, so manually changing spacing or identifiers can make the file unreadable or alter its meaning. Regenerating the export from the PCB design is safer than editing it as ordinary text.

Why Compare an IPC Netlist with Gerber and Drill Data?

The comparison checks whether the manufacturing geometry preserves the connectivity in the PCB design. It is especially useful because a board can look correct in a Gerber viewer while containing an electrical discrepancy.

CAM software reads the copper layers and drill information, then extracts the networks formed by connected copper and plated holes. It compares that result with the separately exported CAD netlist.

The two references answer different questions:

CAD netlist: Which connection points are assigned to the same net?
Gerber and drill extraction: Which points are actually joined by the supplied manufacturing geometry?

Suppose an exported copper layer is missing a short track between two pads. The CAD netlist still groups those pads together, but the extracted network separates them. The disagreement reveals the missing connection before a board is manufactured.

If both the test reference and the board artwork come only from that same incomplete Gerber dataset, they may agree with each other. That agreement does not establish that they match the original design.

Gerber X2 can carry attributes, including net-related information where supported. Even so, the value of a separate CAD export is its independent reference path. It helps expose export or interpretation errors; it does not prove that an incorrect circuit connection already present in the design is functionally correct.

How Do You Export an IPC-356 Netlist from Altium Designer?

In Altium Designer, an IPC-D-356A file can be generated through a Test Point Report fabrication output. An Output Job keeps that export alongside the other manufacturing outputs for the same PCB document.

Using an Output Job:

Open the project’s Output Job file, or add one if none exists.
Under Fabrication Outputs, add Test Point Report and select the intended PCB document as its data source.
Open the output’s configuration to display Fabrication Testpoint Setup.
Enable IPC-D-356A as an output format.
Connect the output to a folder container and set the destination and filename.
Generate the output and locate the resulting IPC file.

Altium also provides a direct route through File > Fabrication Outputs > Testpoint Report in the PCB editor. Menu wording can vary by software version.

Generate the netlist from the same released PCB revision as the Gerber and drill files, after the copper pours and design changes are finalized. Otherwise, a valid file from an older revision can produce mismatches against the new artwork.

An exported file is not itself a successful netlist comparison. The comparison happens after the manufacturing layers, hole data and IPC netlist are imported and interpreted together. For boards with blind or buried vias, missing drill spans or an incorrect layer setup can change the extracted connectivity.

What Causes Netlist Mismatches, Opens and Shorts?

A netlist mismatch means two descriptions of the board disagree. It may reveal a real copper error, but it can also result from mixed revisions or an incorrect CAM import. The mismatch needs to be understood before it is treated as a board defect.

Cause	How it appears in the comparison
Missing track or copper connection	One intended net is split into separate networks
Unintended copper bridge	Two intended nets become one connected network
Incorrect layer polarity or copper interpretation	Plane connections differ from the design reference
Missing or incorrectly assigned plated-drill data	Connections between layers appear absent or incorrect
Netlist and artwork from different revisions	Changed pads or nets no longer correspond
Intentional net tie	Differently named nets are physically joined by design

An open breaks an intended path. In the manufacturing data, this may be a missing track or an unconnected plane feature. On a finished board, a broken conductor or defective plated connection can create an open even when the source files were correct.

A short joins paths that should be separate. It may exist in the supplied artwork or arise during fabrication. File comparison addresses the former; electrical testing of the manufactured board addresses the latter within the test’s coverage.

Not every missing-net message represents an open. Some extraction tools omit isolated single-node features or handle no-net objects differently. Likewise, an intentional net tie can join separate logical names without being an unwanted short. Reviewing the reported locations and the corresponding copper distinguishes these cases from genuine errors.

How Is an IPC-356 Netlist Used for Bare-Board Electrical Testing?

An IPC-356 netlist supplies connectivity information used to prepare a bare-board electrical test program. The equipment then measures the manufactured board rather than merely comparing files.

The main electrical checks are:

Continuity: Does a path that should conduct meet the specified resistance limit?
Isolation: Do networks that should remain separate meet the specified insulation-resistance requirement under the test conditions?

Flying-probe equipment moves probes between accessible locations without a dedicated bed-of-nails fixture. Fixture-based testing uses an array of contacts made for the board and can suit repeat production where fixture cost is justified. Both approaches depend on suitable access and a correctly prepared test program.

The netlist is only part of that preparation. Test voltage, resistance thresholds, probe access and coverage also affect what the test can establish. The existence of an IPC file alone does not define these settings or guarantee complete coverage.

This is why CAM comparison and bare-board electrical testing complement each other. The first can find an error in the manufacturing dataset before production. The second can find a physical connection defect introduced while making the board.

A passing bare-board test does not establish assembled-product performance. Component values, soldered assembly connections, firmware behavior and signal quality require the relevant PCBA inspections or functional tests.

Can ODB++ or IPC-2581 Replace a Separate IPC Netlist?

Yes, when the exported package contains the required connectivity and the manufacturer’s CAM and test workflow can use it. ODB++ and IPC-2581 can combine physical board information and logical connectivity in a richer manufacturing dataset.

Manufacturing package	How connectivity is supplied
Gerber and drill files with IPC-D-356	A separate netlist accompanies the manufacturing geometry
ODB++	Net information can be included within the manufacturing package
IPC-2581	Connectivity can be included in the structured manufacturing data

An integrated package can reduce the need to match several separately exported files. However, the format name alone does not prove that the export contains all the data needed downstream. Export settings and the receiving software still matter.

A separate IPC netlist may therefore remain useful even when an integrated format is supplied, particularly when it provides an additional CAD-derived comparison reference. Whichever package is used, matching revisions and correctly interpreted connectivity matter more than the filename extension.

FAQs About IPC-356 Netlist

1. Is IPC-356 the same as IPC-D-356A?

IPC-356 is commonly used as shorthand when discussing this family of PCB netlist formats. IPC-D-356A is a specific designation that may appear in the export settings. Use the version supported by the receiving CAM or test system rather than assuming every variant is interchangeable.

2. Can I open an IPC-356 netlist in a text editor?

Yes. It is a text-based file, so a text editor can display its records. A compatible CAM viewer is more useful for relating those records to board locations. Opening the file successfully does not confirm that its contents are correct.

3. Can an IPC netlist be generated from Gerber files?

CAM software can extract connectivity from correctly interpreted Gerber and drill data and may export that result as an IPC netlist. However, a Gerber-derived netlist is not an independent record of the original CAD connectivity. An artwork error may be reproduced in the extracted netlist.

4. Does an IPC-356 netlist include the BOM?

No. References and pin identifiers associate connection points with board features, but they do not replace a bill of materials. Component values, manufacturer part numbers and procurement information belong in the assembly documentation.

5. Do I need a new netlist after changing the PCB layout?

Export a new netlist with the revised manufacturing files. Even when the circuit connections are unchanged, moved pads or altered vias can change the physical information used in comparison and test preparation. Keeping the files together as one revision avoids comparing different versions of the board.

Preparing your next PCB build? Send your manufacturing package and IPC-356 netlist, if available, to sales@bestpcbs.com. EBest Circuit can help review the fabrication data and plan bare-board electrical testing before the boards move into assembly.

IPC 1601A: PCB Handling, Storage and Baking Guide

September 15th, 2026

IPC 1601A is the June 2016 guide for handling, packaging and storing printed circuit boards before and during assembly. It addresses moisture uptake, contamination, mechanical damage and loss of solderability. It is not the current edition: IPC-1602 replaced it in 2020, and the official revision table lists IPC-1602A, November 2024, as of September 2026.

If your drawing still specifies IPC-1601A, confirm that edition with your customer rather than silently changing it. For production, the useful questions are concrete: what packaging protects this board, how should an opened lot be stored, and does it need a validated drying cycle before soldering?

IPC 1601A PCB handling and storage illustration with bare boards, dry packaging and humidity indicator card

What Does IPC-1601A Cover?

IPC-1601A covers the handling of printed boards from fabrication through shipment, receiving, storage and soldering. Its focus is preserving the board’s condition, not defining every fabrication acceptance limit or every assembled solder-joint criterion.

The IPC 1601A 2016 edition organizes the subject into fabrication and handling, packaging and shipment, then receiving and assembly. A board that passes electrical testing can still become difficult to solder after poor storage; these are different quality checks.

Document	Main purpose
IPC-1601A	Historical printed-board handling and storage guidance
IPC-1602	Printed-board handling and storage requirements and recommendations
J-STD-003	Solderability testing of printed boards
J-STD-001	Requirements for soldered electrical and electronic assemblies

IPC 1601 and 1602: What Is the Difference?

IPC-1601 is a guideline series; IPC-1602 replaced it with a standard containing both requirements and recommendations. In IPC-1602, “shall” identifies a requirement, while “should” identifies guidance.

August 2010: original IPC-1601.
June 2016: IPC-1601A revision.
April 2020: IPC-1602 explicitly superseded IPC-1601A.
November 2024: IPC-1602A, the revision currently listed by the publisher.

For a new purchase specification, identify the document and revision explicitly. For an existing approved product, resolve any revision change through the customer’s document-control process. A newer publication is not permission to alter an agreed acceptance basis.

PCB Storage Requirements

Keep boards in their specified protective packaging, monitor the storage environment, and follow the supplier’s limits for the exact laminate and surface finish. Room storage and low-humidity dry storage are not interchangeable conditions.

Published manufacturer examples show why a single number can be misleading:

Published example	Condition	Application
KSG storage guidance	20°C ± 5°C; maximum 60% RH	Boards kept in closed transport packaging under its stated conditions
Würth Elektronik flex guidance	5% RH at room temperature	Dry-cabinet storage of its flex and rigid-flex products

These are supplier-specific examples, not universal IPC-1601A limits or EBest Circuit guarantees. Specify the permitted temperature and relative humidity, packaging state, storage duration and action after an excursion. Record actual conditions where the stock is held, not just the building’s air-conditioning setpoint.

Keep lots identifiable and use the earliest approved expiry date first. Do not mix opened boards with an unopened lot and retain only the newer package label.

What Belongs in PCB Dry Packaging?

Dry packaging combines a moisture barrier bag, desiccant and a humidity indicator card sealed around the boards. Each part has a different function.

Moisture barrier bag (MBB): restricts water-vapor entry; its barrier performance and seal matter more than a shiny appearance.
Desiccant: absorbs moisture within its rated capacity. Select the quantity for the package and storage requirement.
Humidity indicator card (HIC): indicates package humidity; read it using that card’s instructions.

Moisture barrier bag, desiccant and humidity indicator card arranged around a bare PCB

Vacuum sealing alone does not establish a dry-pack system. For example, an ordinary polyethylene bag can appear tightly sealed yet lack the specified moisture barrier. Likewise, adding a fresh desiccant sachet does not demonstrate that an already damp laminate is ready for soldering.

Mechanical protection remains separate. Thin or routed panels may need rigid backing or separators so transport pressure cannot bend unsupported sections or rub solderable surfaces. ZVEI’s implementation recommendations specifically identify thin boards below 1.40 mm, flexible boards and complex contours for protective-backing consideration, subject to customer–supplier agreement.

How Should You Handle Bare PCBs?

Hold bare PCBs by their edges with clean, suitable gloves, and keep fingers away from pads, plated holes and contact surfaces.

Use clean trays or separate rack slots instead of sliding boards across one another.
Replace dirty gloves; a contaminated glove can transfer residue just as a bare hand can.
Support thin panels during transfer rather than lifting them by a narrow breakaway tab.
Keep packing debris, hand lotion and loose fibers away from exposed boards.
Apply the specified ESD controls where sensitive devices or product requirements make them necessary.

Gloved hands holding a bare PCB at its edges beside a slotted storage rack

What Should You Check When Opening a PCB Package?

Check the seal, identification, storage history and HIC at opening, then record the exposure start time for the lot.

Before opening: inspect for punctures, separated seals, wet cartons or missing labels.
Match the lot: confirm part number, revision, finish and quantity against the production order.
Read the card promptly: use the card’s own reference and the agreed acceptance procedure.
Release or hold: send acceptable boards to the planned process; segregate suspect packages for engineering review.
Protect the remainder: restore the approved packaging or dry-storage condition and retain its exposure record.

A card reading is not a direct measurement of water inside the laminate. If the exposure history is unknown, do not infer a safe soldering condition solely from a dry-looking card or an undamaged board surface.

When Do PCBs Need Baking Before Assembly?

PCBs need a drying step when their product instructions require it or when a qualified assessment finds moisture incompatible with the planned soldering process. Baking every incoming lot by default can unnecessarily age its finish.

Review a lot before release if its bag is damaged, its exposure limit has been exceeded, or its storage history is missing. Polyimide flex constructions may also carry explicit pre-solder drying instructions even when shipped in protective packaging.

Use the actual board thickness, resin system, copper coverage, finish and exposure history to select the response. Drying a 0.8 mm board and drying a 3.2 mm board with extensive copper planes are not automatically equivalent processes; those dimensions are examples of different constructions, not thresholds in this guideline.

The preheat stage of reflow soldering is not a substitute for a qualified drying cycle. Its short thermal exposure serves the soldering process and does not establish that moisture has diffused out of the board.

What Baking Temperature Should You Use?

Use the board supplier’s approved, product-specific drying profile—not a universal “120°C for every PCB” rule.

For context, Würth Elektronik’s January 2022 flex specification describes 120°C drying, with 4–24 hours potentially needed, and explicitly requires product-specific verification. Those figures illustrate the range within one supplier’s flex guidance; they are not a recipe for every FR-4, OSP or assembled board.

PCB drying review showing an oven, copper and resin cross section, and protected storage after drying

Material and geometry: resin, thickness and copper coverage affect the drying path.
Surface finish: confirm permitted heat exposure for OSP, immersion tin and other finish systems before selecting a cycle.
Equipment loading: allow the validated airflow and support boards against deformation.
After drying: control the wait before assembly so the boards do not simply reabsorb moisture.

Keep the drying record with the lot: profile identifier, oven run, start and finish times, and subsequent storage condition. Do not apply a bare-board oven profile to populated PCBAs without checking component and assembly limits.

Does Baking Restore PCB Shelf Life?

No. Baking removes moisture under suitable conditions; it does not renew an aged surface finish, reverse corrosion or erase the board’s storage history.

Shelf life depends on finish, packaging and exposure conditions. A remaining storage allowance should come from the approved supplier specification, not an automatic six- or twelve-month extension after an oven cycle.

When the concern is whether solder can wet an old pad or plated hole, review J-STD-003 PCB solderability testing. Moisture condition and solderability may both need evaluation, but one result cannot stand in for the other.

Where Can You Get the IPC 1601A PDF?

Obtain a licensed IPC 1601A PDF through the publisher or an authorized standards distributor, and verify that the listing is for the June 2016 revision.

The publisher’s publicly accessible table-of-contents PDF is only a preview. It does not contain the complete baking-profile table, packaging provisions or acceptance instructions. For a new project, also check whether IPC-1602A is the specified document before buying a historical edition.

FAQ About IPC-1601A

Is IPC-1601A a PCB certification?

No. It is a handling and storage guideline, not a stand-alone factory certification. Ask a supplier which documented controls satisfy your specified revision and purchase requirements.

Can an antistatic bag replace a moisture barrier bag?

Not solely because it is antistatic. Electrostatic protection and resistance to water-vapor transmission are different properties. A bag intended to provide both must meet both specified functions.

Does ENIG prevent the laminate from absorbing moisture?

No. ENIG protects solderable copper surfaces; it does not turn the complete PCB into a moisture-impermeable object. Laminate condition still needs to suit the assembly process.

Should every bare PCB use the same component MSL floor-life table?

No. Do not assign a component moisture-sensitivity level to every bare board by assumption. Follow the printed-board requirements and supplier instructions; a supplier may specify an analogous handling rule for a particular product.

What should a PCB storage label record?

Record the part and revision, lot identity, packaging date and applicable storage instruction. For opened material, retain the opening time and any subsequent drying or repacking record needed by your process.

How Can EBest Circuit Support Your PCB Project?

At EBest Circuit, we provide PCB fabrication and PCBA services, from prototypes to production. We can review your board construction, surface finish and assembly requirements together, including the handling and packaging instructions your project needs.

Send your Gerber files, fabrication drawing, quantity and specified IPC revision to sales@bestpcbs.com. Include any storage, dry-pack, labeling or pre-assembly drying requirements so we can confirm the project scope before production.

What Does J-STD-003 Reveal About PCB Solderability?

September 11th, 2026

J-STD-003 addresses the solderability of bare printed circuit boards: whether the exposed surfaces intended for soldering can be wetted by molten solder. For your PCB project, that matters before components reach the assembly line. At EBest Circuit (Best Technology), we connect PCB fabrication and assembly support so that the board finish, component layout and soldering process are considered together.

J-STD-003 PCB solderability concept illustration showing exposed pads and plated-through holes

What Is J-STD-003?

IPC J-STD-003 (also written IPC J STD 003 or J STD 003) is the solderability test standard for printed boards. Its subject is the board’s exposed conductors, attachment lands and plated-through holes, rather than component leads or completed solder joints.

Solderability testing helps separate a surface-wetting problem from an assembly-process problem. A satisfactory bare-board result does not prove that every joint will form correctly during production: solder paste deposition, component placement and the thermal profile remain separate parts of assembly quality.

Why Can a PCB Look Clean but Solder Poorly?

A clean-looking pad is not necessarily a readily wettable pad. Thin oxidation or contamination can interfere with the solder-to-metal interface without producing an obvious defect in an ordinary board photograph.

On our FR4 printed circuit boards, the solderable features include both surface-mount pads and connection points for through-hole parts. If solder withdraws from a pad, the resulting connection can be incomplete even though the copper circuit passes an electrical continuity test. Continuity and wettability answer different questions.

Appearance also depends on the solder alloy. Lead-free solder does not necessarily spread or look like tin-lead solder, so a comparison based only on shininess can be misleading. The important distinction is whether the intended metal surface has been wetted under the applicable test conditions.

Which Solderability Test Methods Are Used?

J-STD-003D includes visual evaluation methods and wetting-force measurement. The method must suit the board features being assessed.

Method family	Main evaluation
Edge dip	Wetting of exposed surface conductors
Surface-mount simulation	Wetting of surface-mount lands
Wave solder or solder float	Solderability of plated-through-hole features
Wetting balance	Wetting behavior recorded as force over time

For a board carrying both fine-pitch components and connectors, a surface-pad observation cannot answer every question about the holes. Likewise, a test on an unrelated reference board cannot establish the condition of your production lot. Representative material and the agreed evaluation method are essential to a useful result.

What Does a Wetting Balance Test Measure?

A wetting balance test records the force acting on a specimen as it contacts molten solder. The force-time response shows how wetting develops, adding information that a photograph taken after cooling cannot provide.

Conceptual wetting balance test with a PCB coupon, solder bath and illustrative force-time curve

The response reflects surface tension, buoyancy and the developing solder meniscus. Test temperature, alloy, flux and specimen geometry affect the signal; curves obtained under different conditions are not automatically comparable. The illustration shows the measurement principle, not a measured result or a pass/fail limit.

For a difficult-to-solder pad, this measurement can help investigate delayed or weak wetting. It does not identify the root cause by itself, and it does not replace examination of the finish or the actual assembly process.

How Do Nonwetting and Dewetting Differ?

Nonwetting means solder has not formed the intended wetted interface. Dewetting describes solder withdrawing after initially covering an area, leaving an uneven coating. Both can reduce useful solder coverage, but they describe different behavior.

Observation	What it suggests	What it does not prove
Solder beads beside an uncovered pad	Possible nonwetting of that surface	That the PCB finish is the sole cause
Irregular solder islands after coverage recedes	Possible dewetting	A specific contamination source without further analysis
Smooth-looking solder on only part of the feature	Incomplete coverage still needs evaluation	Acceptance based on appearance alone

For an assembly defect, the PCB pad and the component termination should be distinguished. A board can have satisfactory solderability while a component lead has a separate surface problem. Adding more heat or flux without identifying the affected interface can damage the assembly rather than resolve the cause.

How Does PCB Surface Finish Affect Solderability?

The surface finish protects exposed copper and establishes the surface presented to the soldering process. ENIG, OSP, immersion silver, immersion tin and HASL use different protection systems, so the finish name alone cannot describe every assembly constraint.

Conceptual comparison of an ENIG plated pad and an OSP protected copper pad before soldering

Finish	Relevance to assembly	Project consideration
ENIG	Flat nickel-gold finish for component lands	Finish integrity and the planned soldering sequence
OSP	Organic protection over copper without a raised solder coating	Handling, storage and cumulative thermal exposure
Immersion silver or tin	Thin metallic protection on exposed copper	Packaging and finish-specific assembly conditions
HASL or lead-free HASL	Solder coating on exposed features	Pad planarity and alloy compatibility

For our HDI boards, fine-pitch pad geometry makes surface planarity and solder-paste deposition particularly relevant. A readily wettable finish cannot compensate for a stencil opening that delivers too little paste. Our finish options include ENIG, ENEPIG, OSP, immersion silver, immersion tin and lead-free HASL; we match the available construction to your board and assembly requirements.

Can Storage and Repeated Heating Change the Result?

Yes. The condition of a solderable surface can change between fabrication and assembly. Packaging, handling and thermal exposure therefore matter alongside the original finish selection.

A double-sided assembly may expose the second-side pads to heat before they are soldered. A later selective-soldering operation adds another thermal stage. These histories differ from soldering a fresh, unheated specimen, and their effect depends on the finish and process.

For boards held in storage, the production date alone is not a complete description of their condition. Whether the original packaging stayed intact and whether surfaces were exposed to contamination are also relevant. Baking should not be treated as a universal way to restore solderability: a moisture-removal step cannot simply reverse oxidation or damaged surface chemistry.

Is J-STD-003 Class 3 the Same as Coating Durability?

No. J-STD-003 Class 3 concerns the product classification; coating durability is a separate rating. A higher product class does not automatically specify an aging treatment.

In J-STD-003D, coating-durability notation differs between Pb-containing and Pb-free finishes. Category 2 or Category 3 terminology must not be exchanged blindly with the lettered categories for another finish system. Your specified revision and finish determine the applicable requirements.

What Is the J-STD-003 Latest Revision?

The J STD 003 latest revision listed when this article was checked in September 2026 is J-STD-003D. Older J-STD-003B and J-STD-003C references still appear in drawings and search results; they should not be treated as interchangeable editions.

If an existing design calls for an earlier revision, changing its acceptance basis is an engineering decision, not just a document-name update. We work from the agreed fabrication requirements rather than silently substituting a newer edition.

How Is J-STD-003 Different from J-STD-002 and J-STD-001?

The main difference is what is being evaluated: the bare board, the component connection surface, or the assembled soldered connection. The related standards are complementary, not substitutes.

Standard	Primary subject
J-STD-003	Printed-board solderability
J-STD-002	Solderability of component leads, terminations and related connection surfaces
J-STD-001	Requirements for soldered electrical and electronic assemblies
J-STD-004	Soldering flux requirements
J-STD-005 / J-STD-006	Solder paste / electronic-grade solder alloys and related forms

For example, a connector joint joins a board barrel to a component pin. Evaluating the barrel does not establish the pin’s solderability, while evaluating both surfaces still leaves the production soldering process to be controlled. This is why one bare-board test result cannot stand in for complete assembly acceptance.

How Do We Connect Bare-Board Quality with PCB Assembly?

We provide PCB fabrication and PCB assembly services, including SMT, through-hole and mixed assembly. This lets us consider the solderable board surface together with the components and the planned assembly sequence.

Concept illustration showing the same PCB layout before and after surface-mount and through-hole assembly

Our FR4 manufacturing capability extends to 32 layers, with the final construction subject to engineering review. For a multilayer controller with dense surface-mount parts and through-hole connectors, the board stack-up, pad finish and thermal demands all affect how fabrication and assembly fit together. We review these requirements as a connected PCB project, not as an isolated finish choice.

Discuss your J-STD-003 requirement with our engineering team at sales@bestpcbs.com. We can review the fabrication drawing, surface finish and assembly plan, and confirm the applicable project requirements before production. Any dedicated test method, sampling arrangement or report requirement must be agreed for that project.

How Does IPC-SM-840C Apply to PCB Solder Mask?

September 11th, 2026

IPC-SM-840C is the C revision of the specification for qualifying permanent solder mask used on printed circuit boards. It connects the coating’s electrical, physical and environmental performance with its intended application. For your PCB, the practical questions are which mask class applies, how the coating fits the layout, and whether it is compatible with fabrication and assembly. At EBest Circuit (Best Technology), we provide PCB manufacturing and assembly support to help turn those requirements into a buildable board.

Conceptual illustration of IPC-SM-840C solder mask on a printed circuit board

What Is IPC-SM-840C?

IPC-SM-840C addresses the qualification and performance of permanent polymer solder mask, also called solder resist. The coating covers selected copper and laminate surfaces while leaving soldering pads, contacts and other specified areas exposed. It helps protect conductors and define where solder should wet during assembly.

The C revision dates to January 1996, with Amendment 1 issued in June 2000. It is a historical edition, so an existing drawing may name it even when a current material datasheet names a later revision. The standard concerns both material evaluation and the way the mask is used on a board. For example, a coating qualified on a test substrate still needs a suitable application process on the actual copper pattern.

What Do IPC SM 840 Classes T and H Mean?

Class T and Class H distinguish solder mask performance requirements by end-use reliability needs. Class T covers telecommunications and other high-performance commercial or industrial equipment. Class H addresses high-reliability applications where continued operation is critical. For drawings that specify IPC-SM-840C Class T or IPC SM 840C Class H, the required designation should carry through to the selected mask material.

Solder mask class	Application emphasis	What to specify for your board
IPC SM 840 Class T	Long service life in commercial and industrial electronics	Required revision, compatible mask material and intended assembly conditions
IPC SM 840 Class H	Higher assurance where uninterrupted operation is essential	Required revision and class, with the qualification evidence applicable to that material and process

These letters describe the solder mask requirement. The finished PCB’s IPC-6012 Class 2 or Class 3 requirement is a separate specification covering the rigid board. Keeping both requirements explicit makes the intended coating performance and overall board quality clear.

Which Solder Mask Properties Affect PCB Reliability?

Adhesion, electrical insulation and resistance to processing exposure determine whether the coating can protect the circuit throughout manufacture and use. Colour and surface appearance matter for inspection and product presentation, but the functional properties are the basis for material selection.

Property group	What it addresses	Relevance to the finished PCB
Adhesion and mechanical integrity	Bonding to the underlying surface; resistance to cracking or peeling	Maintaining coverage around tracks, pads and machined edges
Electrical performance	Dielectric strength and insulation resistance	Helping preserve insulation between neighbouring conductors
Soldering and chemical resistance	Exposure to soldering heat, fluxes and process chemicals	Keeping the mask intact through board finishing and assembly
Environmental performance	Moisture exposure, thermal changes and electrochemical migration	Matching the material to the board’s service conditions
Cure and surface condition	Developed film properties and usable surface quality	Supporting consistent handling and subsequent processing

For our FR4 printed circuit boards, solder mask selection belongs alongside copper layout, surface finish and assembly requirements. A controller with exposed test points has different mask artwork needs from a densely populated communications board, even when both use the same laminate family.

How Does LPI Solder Mask Become a Protective Pattern?

Liquid photoimageable solder mask is applied as a coating and patterned by light exposure and development. A typical LPI soldermask process includes surface preparation, coating, preliminary drying, imaging, development and final cure. The result is a permanent film with openings matched to the circuit artwork.

Surface preparation supports adhesion; imaging and development define the openings; final cure develops the required film properties. Their combined effect explains why the material name alone is only part of the finished-board result. Dry-film photoimageable solder mask offers another material format, with different behaviour over the board’s raised copper features.

The phrase LDI vs LPI solder mask can cause confusion: LPI describes liquid photoimageable material, while laser direct imaging describes an imaging method. An appropriately formulated LPI material can be used with direct imaging. Material selection and imaging compatibility therefore need to be considered together.

What Is the Recommended Thickness for PCB Solder Masks?

The recommended finished thickness is material- and layout-specific; one universal value does not describe every PCB. Solder mask thickness affects protection over copper edges, available clearance and the local surface height around component pads. A patterned PCB is not flat: copper traces, planes and gaps create different coating conditions. Thickness over a conductor and thickness beside it may therefore differ.

Not-to-scale conceptual cross-section showing solder mask covering raised copper traces and laminate

An IPC SM 840 solder mask thickness requirement should identify the measurement location and the agreed finished-film requirement. A value measured over bare laminate is not directly interchangeable with one measured over copper. The material system, copper profile and circuit geometry determine the practical coating window.

This becomes especially relevant on our heavy copper PCBs: taller conductors make edge coverage and coating transitions more demanding. Providing the outer-layer copper requirement with the mask artwork allows these features to be considered together, rather than treating the mask as a uniform flat sheet.

Why Do Pad Openings and Mask Dams Matter?

Pad openings expose the intended solderable surface, while a solder mask dam is the narrow strip of coating between adjacent openings. Registration is the alignment between the mask pattern and the copper pattern. Together, these features influence usable pad area and separation around fine-pitch components.

Conceptual top view of fine-pitch solder pads with separate openings and green solder mask dams

For our HDI boards, the pad pitch, opening size and achievable registration must work together. If a proposed dam is too narrow to manufacture consistently, the layout or opening strategy needs adjustment. The package’s land-pattern requirements remain important, particularly when choosing solder-mask-defined or non-solder-mask-defined pads.

Via tenting is a separate artwork choice: mask covers the via opening rather than filling the hole. Keep probe-access test points exposed, and specify via filling separately where that structure is required. These details help us preserve both assembly access and the intended coverage during DFM review.

How Do Surface Finish and Assembly Affect Mask Selection?

The mask must tolerate the selected board-finishing process and subsequent assembly exposure. ENIG, immersion tin and HASL use different chemical or thermal processing routes. Reflow, wave soldering and cleaning add further conditions after the bare board has been manufactured.

We offer finishes including ENIG, lead-free HASL, OSP, immersion silver and immersion tin. Sharing your intended finish and assembly route helps us discuss the appropriate board construction and mask compatibility. For a mixed SMT and through-hole assembly, the total processing sequence matters more than considering one reflow pass in isolation.

Mask colour can also affect imaging and cure settings within a material family. A green-to-black or green-to-white change is therefore a material/process choice as well as a cosmetic one. Its effect on fine features should be reviewed with the board requirements.

Solder Mask vs Conformal Coating: What Is the Difference?

Solder mask protects selected areas of the bare PCB and defines soldering openings. Conformal coating is normally applied after assembly to protect the populated board from its environment. They occupy different places in the build and can be used together.

Conceptual comparison of solder mask on a bare PCB and a translucent protective coating over an assembled circuit

For an industrial sensor exposed to humidity, the bare board may use solder mask while the completed assembly receives a compatible conformal coating. Connectors and test interfaces can require selective exclusion from that later coating. Adhesion between the two coatings and compatibility with cleaning residues become part of the assembly design.

Our PCB and PCBA services let you discuss bare-board manufacture and assembly as a connected project. Where additional protective coating is required, include that requirement with the assembly information so the intended materials and exposed areas are clear.

IPC SM 840 Latest Version: Is Revision C Still Current?

No. As of September 2026, the IPC document revision table lists revision E, issued in December 2010, after revision D from April 2007. C remains relevant to legacy specifications, but new project documentation should identify the edition actually required.

In the IPC SM 840 family, IPC SM 840C was followed by IPC SM 840D and IPC SM 840E. Revision E’s scope includes flexible cover materials as well as permanent solder mask. The revision letter therefore conveys technical scope, not merely a newer publication date.

If your drawing calls for C and the proposed mask documentation references E, send both with the project files. We can discuss the specified material and manufacturing route with you; any change to the drawing’s requirement should be agreed before production. The selected edition and class provide a clearer requirement than simply writing “IPC solder mask.”

How Can We Support Your PCB Solder Mask Requirements?

We combine PCB manufacturing, DFM support and assembly services, helping you match the solder mask pattern to the actual circuit. Our FR4 capability extends to 32 layers, and our HDI capability includes minimum line/space down to 2/2 mil, subject to materials, stack-up, board dimensions and engineering review. These are circuit-fabrication capabilities; the mask opening and dam requirements are reviewed separately.

For a board specified to IPC-SM-840C, send the Gerber files, fabrication drawing, required class, mask colour, surface finish and any critical pad or via details. Add assembly files when PCB assembly is part of the project. Contact our team at sales@bestpcbs.com or through our PCB manufacturing enquiry page to discuss your board.

What Does IPC-6012 Class II Mean for Your PCB?

September 11th, 2026

IPC-6012 class II identifies a performance level for rigid printed circuit boards used in dedicated-service electronics. Usually written Class 2, it addresses the quality of the manufactured bare board, including its conductors, plated holes, insulation and structural integrity. It is not simply an appearance grade. At EBest Circuit (Best Technology), we manufacture PCBs and help you connect the specified performance class with a practical board construction, so your assembly starts with the right foundation.

Conceptual illustration of IPC-6012 Class II rigid PCB quality with a plated board and inspection coupon

What Is IPC-6012 Class II?

IPC-6012 Class II means the Class 2 requirements within the qualification and performance specification for rigid printed boards. Class 2 serves equipment where dependable operation and an extended service life matter, but uninterrupted operation is not as critical as it is for Class 3 applications. The numeral II does not mean a two-layer board or revision two of the standard.

IPC 6012 class 2 can apply to different rigid constructions, from a double-sided controller board to a multilayer interconnect. Layer count, laminate grade and surface finish still need their own specification. A Class 2 designation therefore answers one important question about acceptance, but does not define every feature of your PCB.

Which Products Are Suitable for Class 2 PCBs?

Class 2 is a relevant starting point for many commercial instruments, communications peripherals and industrial controls whose service requirements match dedicated-service electronics. The application name alone does not determine the class: the consequence of failure and the required operating conditions matter more.

Application example	What the PCB contributes	What still needs application-specific attention
Commercial measurement instrument	Stable connections between sensing, conversion and display circuits	Leakage paths, noise-sensitive layout and calibration requirements
Communications peripheral	Interconnects for processing, power and external interfaces	Controlled impedance, connector loading and signal integrity
Non-safety-critical industrial controller	Reliable mounting and connections for control and input/output circuits	Temperature cycling, contamination and terminal mechanical loads

Conceptual industrial controller assembly showing a rigid PCB application, not a customer product or conformity claim

For these types of circuits, our FR4 printed circuit boards provide a manufacturing route from prototypes to multilayer builds. We review the board design against the requested construction; an instrument’s safety function or environmental exposure may require additional requirements beyond a general Class 2 designation.

What Do IPC 6012 Class 2 Requirements Cover?

IPC 6012 class 2 requirements cover the finished bare board’s physical and electrical quality, not just its visible surface. The areas below explain why a board can look acceptable yet still need evidence about its internal connections or insulation.

Quality area	Examples of relevant features	Value to your product
Conductors and spacing	Trace geometry, copper continuity and separation	Maintains intended current paths and reduces short-circuit risk
Holes and interconnections	Hole copper, registration and connection to internal lands	Supports reliable connections between layers and component leads
Laminate and structure	Bonding integrity and response to specified thermal stress	Reduces vulnerability to internal damage during subsequent processing
Solderable surfaces and mask	Surface condition, coverage and mask alignment	Provides a suitable foundation for component assembly
Dimensions and flatness	Finished geometry, hole position, bow and twist	Helps the board fit fixtures, connectors and the enclosure
Electrical performance	Continuity and insulation-related requirements	Checks conditions that appearance cannot establish

The applicable revision and your agreed drawing determine the actual acceptance limits. Our PCB testing capabilities include AOI, microsection analysis and flying-probe testing. These address different types of evidence; a continuity pass alone does not demonstrate every structural requirement.

Why Are Hole Copper and Annular Rings Important?

A plated hole is an electrical connection through the board, while its annular ring is the copper land around the hole. Their geometry and integrity affect whether a connection remains reliable after soldering and use. Drilling, layer registration and plating all contribute to the finished result.

Conceptual four-layer PCB cutaway with a continuous plated through-hole and annular ring; not to scale

The copper weight chosen for a surface layer is not the same measurement as hole-wall plating thickness. Likewise, a round pad in the design file does not guarantee the same annular ring after drill and registration tolerances. Preserving manufacturing allowance around these features helps avoid late layout changes and marginal interconnections.

For our HDI boards, the connection between a microvia and its target land is also important. A small surface footprint can save routing space, but microvia construction needs its own engineering review; it should not be treated as a scaled-down conventional through-hole with identical behavior.

How Do Laminate and Thermal Stress Affect Reliability?

The laminate must maintain insulation and structural integrity through the thermal conditions relevant to the build. Copper and resin expand differently, so soldering heat places stress on the board and its interconnections. This is why material selection and plated-hole quality work together rather than as separate purchasing choices.

Conceptual rigid PCB in a thermal chamber illustrating thermal exposure; not an actual factory test or a specified IPC test setup

Our high-Tg PCBs are relevant when the assembly and operating conditions call for a suitable higher-Tg laminate. However, Tg alone is not a complete reliability rating: moisture behavior, thermal expansion, board thickness and the soldering profile also matter. A higher-Tg material does not automatically turn a Class 2 board into Class 3.

For your product, the useful distinction is between the specified board qualification evidence and the environment the assembled equipment will actually encounter. Repeated field temperature cycles or a harsh environment may need additional validation even when the bare board meets its agreed acceptance requirements.

IPC 6012 Class 2 vs Class 3: Which Fits Your Application?

The central difference in IPC 6012 class 2 vs class 3 is the required level of service performance and the associated acceptance criteria. Class 3 is intended for applications where continued operation is more critical. It is not simply the same board with a better finish or an extra final inspection.

Decision	Class 2	Class 3
Service expectation	Dependable operation and extended service	Higher-performance service where continued operation is critical
Design and fabrication impact	Features must meet the agreed Class 2 requirements	Some features need tighter acceptance conditions and corresponding manufacturing allowance
Project implication	Appropriate when product requirements fit this class	Needs early alignment of design, fabrication and qualification requirements

IPC 6012 class 1 addresses general electronic products and is not a substitute for a required Class 2 build. At the other end, specifying IPC 6012 class 3 does not by itself establish compliance with every medical, automotive or aerospace requirement. Relevant addenda and product-specific obligations can apply. Choosing the class early is more effective than trying to upgrade a completed lot through inspection alone.

How Does IPC-6012 Differ from IPC-A-600 and IPC-A-610?

IPC-6012 defines rigid-board qualification and performance requirements; IPC-A-600 helps interpret printed-board acceptability visually; IPC-A-610 concerns electronic assemblies. These documents address related but different parts of the product, so they are not interchangeable.

A solder joint on a mounted component belongs to the assembly discussion, whereas a plated hole inside the bare board belongs to board fabrication. If your project includes both PCB manufacture and assembly, we can support both stages, but each needs its appropriate acceptance basis. Our IPC-A-600 bare PCB inspection explanation describes how visual and internal observations complement performance requirements.

Does Class 2 Determine Layer Count, Finish or Impedance?

No. Class 2 is not a complete stack-up or electrical design. A board can require controlled impedance, a particular laminate or a specific surface finish in addition to Class 2 acceptance. Those choices come from the circuit and its assembly requirements.

For example, a communications board may need a defined impedance structure, while an industrial control board may place greater emphasis on current capacity and terminal spacing. Both can use a Class 2 acceptance basis without sharing the same construction. We offer FR4 builds up to 32 layers, subject to engineering review. We can discuss the stack-up, routing density and assembly needs together to identify a suitable construction for your design.

Early DFM support helps connect your intended circuit with manufacturable pads, holes and conductor geometry. It also makes special requirements visible before production, rather than leaving them to be inferred from a general class note.

Which IPC-6012 Revision Applies?

The IPC 6012 latest revision listed in the official revision table is IPC-6012F, September 2023, checked on September 11, 2026. The agreed revision for an existing product can differ. The letter identifies the edition; Class 2 identifies a performance level within that edition.

A legacy drawing referring to IPC 6012D class 2 should therefore not be silently treated as a Class 2 callout under revision F. Where your product moves to a newer edition, the affected requirements need to be aligned with the design and manufacturing agreement. Different editions of an IPC-6012 PDF are not interchangeable simply because they discuss the same class.

What Does IPC-6012 Certification Mean?

IPC-6012 certification can refer to different things, including an individual’s training credentials or a manufacturing qualification program with a defined scope. Neither should be confused with the conformity of a particular board lot. The certificate, issuing organization and scope determine what a certification claim actually establishes.

For the PCBs you receive, the useful evidence relates to the agreed board revision, specified class and applicable manufacturing or test records. A company-level quality certificate alone does not replace that product-specific evidence, and a bare-board acceptance result does not prove the completed equipment’s functionality.

How Can We Support Your Class II PCB Project?

We support PCB fabrication, DFM and PCB assembly, helping you carry the intended board requirements from design into a practical build. Our available inspection and test capabilities include microsection preparation and analysis, copper-thickness checks, AOI and flying-probe testing. Tell us which test reports your project needs so we can confirm the test scope and delivery documentation with your build.

Send your board files, fabrication drawing and intended application to sales@bestpcbs.com. At EBest Circuit (Best Technology), we can review your IPC-6012 class II requirements alongside the stack-up, material and assembly needs, so the board specification supports the product you are building.

How Do You Use IPC-A-600 for Bare PCB Inspection?

September 11th, 2026

IPC-A-600 gives PCB manufacturers and customers a common visual reference for judging bare-board workmanship. It is used alongside the agreed performance specification, product class and drawing requirements. At EBest Circuit (Best Technology), we manufacture custom PCBs and provide inspection and testing capabilities that help evaluate the boards before assembly. For your project, the practical question is how these requirements and checks relate to solderable pads, sound interconnections and the circuit you expect to receive.

Conceptual illustration of IPC-A-600 bare PCB inspection under an optical microscope

What Is IPC A 600, and Why Does It Matter for Your PCB?

The IPC A 600 standard is an illustrated acceptability reference for unassembled printed boards. Its title, IPC A 600 Acceptability of Printed Boards, covers the board itself: the conductive pattern, laminate and interconnections that will later support your components. It is not an assembly solder-joint standard.

For a customer, a shared reference makes a quality discussion more specific. A pad, hole or board edge can be evaluated against an agreed requirement instead of an impression that it looks unusual. For us as a fabricator, that same distinction connects the intended board construction with the features that need examination. Appearance is one part of acceptance; measurements and testing supply the additional evidence required by the design.

Which IPC-A-600 Revision Applies to Your Order?

The revision agreed for your order is the applicable baseline. The IPC A 600 latest revision is IPC-A-600M, released in May 2025. A repeat order may still reference an earlier edition; a newly released standard does not automatically change an existing contractual requirement.

Using the IPC A 600 current revision for a new design and maintaining an established revision for an existing product are different decisions. We can discuss the revision stated in your fabrication requirements as part of the engineering review. This helps keep the requested board, inspection expectations and subsequent repeat builds aligned.

An authorized IPC A 600 PDF or printed copy contains the detailed criteria for the selected edition. This article explains their role in PCB manufacturing; the complete standard and your agreed specification remain the references for individual acceptance decisions.

How Do Class 2 and Class 3 Affect PCB Acceptance?

The product class expresses the service expectations behind the acceptance requirements. In an IPC A 600 class 2 vs class 3 comparison, the useful distinction is the intended level of service, not the appearance of the finished board or a universal quality ranking.

Class reference	Service expectation	Meaning for your board
IPC A 600 class 2	Dedicated-service products requiring extended life and continued performance	The specified Class 2 criteria establish the relevant acceptance baseline.
IPC A 600 class 3	High-performance products where continued operation is especially important	The applicable Class 3 criteria and any additional requirements need to be reflected in the build requirements.

A drawing may use the wording IPC A 600 class II for Class 2. The class, revision and any customer-specific requirements together define what is requested. We can review those requirements against your stack-up and features before manufacture; assigning a class alone does not establish every material, construction or test requirement.

How Does IPC-A-600 Relate to IPC-6012 and IPC-A-610?

IPC-A-600 helps interpret observable board conditions, while the applicable performance specification defines requirements for the board construction. IPC A 600 vs IPC 6012 is therefore a comparison of complementary documents, not two interchangeable inspection options.

Document	Scope	Connection to the product we supply
IPC-A-600	Illustrated acceptability of bare printed boards	A common reference for interpreting visible and sectioned board features.
IPC-6012	Rigid-board qualification and performance requirements	Relevant to specifying rigid PCB fabrication requirements.
IPC-6013	Flexible and rigid-flex board qualification and performance requirements	Relevant to constructions with flexible sections.
IPC-A-610	Acceptance of electronic assemblies	Relevant after components are assembled onto the PCB.

For IPC A 600 vs IPC A 610, the key boundary is bare PCB fabrication versus electronic assembly. We offer both PCB manufacturing and PCB assembly, so these are distinct stages of a project: board acceptance addresses the substrate and circuitry; assembly acceptance addresses the populated product.

Which Bare-Board Features Affect Assembly Quality?

Pads, conductor geometry, holes and solder-mask openings form the interfaces between a bare PCB and the assembly process. Their condition matters because components must fit, intended soldering areas must remain accessible, and conductors must retain the geometry required by the design.

Conceptual view of bare PCB pads, holes and conductor patterns examined with a magnifier

Exposed lands: pad condition and unwanted mask coverage affect the available soldering surface.
Conductor patterns: unwanted copper connections or missing conductor material can change the intended circuit.
Holes and mounting features: finished dimensions affect lead insertion, mounting and mechanical fit.
Board outline and laminate: edge condition and visible material damage can affect handling and fit in the assembly.

Our PCB inspection capabilities include AOI, hole-diameter inspection and dimensional measurement. These methods support different questions: an optical examination locates a visible feature, while a measurement establishes its size or position. For your board, the relevant drawing requirements provide the link between what is observed and what the assembly needs.

What Can Microsection Analysis Reveal Inside Your PCB?

Microsection analysis exposes internal construction that cannot be assessed from a surface photograph. A prepared section can show the relationship between a plated hole, inner-layer copper and the surrounding laminate. That is valuable when the question concerns an interconnection inside the board rather than an exposed pad.

Conceptual PCB microsection showing a plated hole wall and internal copper connections, not to scale

We provide microsection preparation and analysis and copper-thickness testing as part of our PCB testing capabilities. For our HDI boards, the question may involve a microvia interface or an interconnected via structure. The section location and represented construction therefore matter as much as the image itself.

The benefit for your project is evidence about an otherwise hidden feature. A section represents the sampled area; additional sampling or reliability evaluation may be needed for the application’s requirements. The illustration above explains the inspection concept and is not a production micrograph.

How Does Electrical Testing Complement Visual Inspection?

Electrical testing evaluates whether intended nets are connected and separate nets remain isolated under the test conditions. Visual inspection examines physical features. Together they address two different aspects of the bare board: its construction and its circuit connectivity.

Conceptual flying-probe test station contacting separate pads on an unpopulated PCB

Our PCB testing capabilities include flying-probe testing, universal electrical testing and open/short testing. These are directly relevant to finding connectivity faults before components are added. A conductor pattern may appear complete yet contain an open connection; electrical testing addresses that question without relying on appearance alone.

For designs with controlled-impedance traces, we also provide impedance testing. This answers a different question from continuity: whether the specified transmission-line characteristic is achieved. The tests required for a particular board depend on its design and the agreed requirements; an electrical pass is not a substitute for every other specified evaluation.

Why Do Different PCB Constructions Need Different Checks?

Different constructions contain different interfaces and interconnections. The acceptance reference remains useful across them, but the features relevant to a two-layer rigid board are not identical to those in a multilayer HDI or rigid-flex design.

PCB construction	Relevant features	What they mean for your design
FR4 printed circuit boards	Outer patterns, plated holes and the internal connections present in the stack-up	Component mounting and the intended paths between copper layers.
HDI boards	Microvia interfaces and filled or capped vias where specified	Connections that support dense routing and fine-pitch component layouts.
Rigid-flex circuits	Coverlay openings, bonded regions and rigid-to-flex transitions	Electrical connections and the mechanical interfaces involved in installation or flexing.

Our FR4 manufacturing capability extends to 32 layers, subject to the stack-up, dimensions, materials and engineering review. As internal connections become more complex, the construction information becomes more important to selecting meaningful inspection evidence. This is why layer count alone is not enough to describe the board we are being asked to manufacture.

How Can Inspection Evidence Help Resolve a Board Concern?

A useful quality discussion connects the observed condition to the affected feature and its requirement. If you have a concern about a supplied board, we can review it with your part information, the location of the feature and the relevant photographs or measurements. That gives both teams a specific technical issue to discuss.

For example, a question about whether a lead will fit a hole calls for finished-hole dimensions and the component requirement. A concern about an internal connection may call for sectioning or electrical evidence instead. The benefit is a response directed at the actual board function, rather than a general judgment based on one photograph. Any proposed change to an agreed acceptance requirement needs customer agreement.

What Does IPC-A-600 Certification Mean for Customers?

IPC A 600 certification refers to personnel training and assessment credentials. It answers a question about knowledge of the standard, whereas inspection and test results answer questions about a particular board or lot. These are different forms of evidence.

For your project, the relevant discussion with us is the required board construction, acceptance basis and available inspection or testing support. Personnel credentials, when required, need separate confirmation of their scope and validity. A credential is not a replacement for evidence about the product being delivered.

How Can We Support Your Next PCB Build?

We combine custom PCB manufacturing, DFM engineering review and PCB testing support. This lets us discuss your acceptance requirements in the context of the actual board, from its stack-up and holes to its surface finish and assembly interfaces.

For an IPC-A-600 question about your next build, contact sales@bestpcbs.com with your fabrication data and the requirements already defined for the project. At EBest Circuit (Best Technology), we can review the design and discuss the applicable inspection and testing needs before manufacture.

What Is IPC-7351? PCB Land Pattern Design, Courtyard and Spacing Guide

September 2nd, 2026

IPC-7351 provides a method for developing surface-mount land patterns from component dimensions, tolerances and solder-joint goals. The useful result is a set of copper pads that accommodates the intended terminals and assembly process. A package label such as 0603 or QFN-32 is only the starting point: it does not supply all the dimensions needed to draw those pads.

A practical footprint design connects the package drawing to pad geometry, placement space and manufacturing outputs. The sequence below follows that connection, including a real 0603 resistor example that turns a manufacturer’s recommended land pattern into CAD pad sizes and coordinates.

What Is IPC-7351, and Which Version Applies?

IPC-7351 covers land patterns for surface-mount components. Its method relates terminal geometry and dimensional variation to the solder connection. This makes it useful when building a footprint library, comparing an imported footprint with a component drawing, or reviewing a package substitution.

The official IPC revision table, checked on August 31, 2026, lists IPC-7351B from June 2010 and marks it as no longer maintained. It also lists IPC-7352, Generic Guideline for Land Pattern Design, from 2023, covering surface-mount and through-hole land patterns. Review that newer guidance for new library work; retain the specified edition for an existing design rather than silently changing its basis.

IPC-7351 succeeded IPC-SM-782. Broader board design, stencil design and soldered-assembly requirements are addressed separately by the IPC-2220 series, IPC-7525 and J-STD-001. They support different release decisions and do not replace the land-pattern calculation.

What Is Included in an IPC-7351 Land Pattern?

A land pattern primarily defines the copper lands and their geometric relationship to the component terminals. A complete PCB footprint also carries the mask, paste, courtyard, assembly outline and orientation information needed to use that geometry in a board design.

Footprint information	What the designer must establish
Copper lands	Pad width, length, spacing and terminal numbering
Solder-mask openings	Exposed copper and the permitted registration allowance
Paste apertures	The stencil openings required for the chosen solder deposit
Courtyard	A placement boundary around the component and land-pattern envelope
Assembly outline and orientation	Body location, pin-1 reference, origin and rotation convention

An IPC-7351 land pattern becomes a usable library footprint when these outputs agree. For example, a QFN’s copper thermal pad, its segmented paste openings and its courtyard have different jobs; changing one does not automatically define the other two.

Which Component Dimensions Are Required Before Pad Design?

Extract the dimensions of the solderable terminals, not just the package body. Work from the exact manufacturer part number and drawing revision, and preserve the drawing’s top-view or bottom-view designation.

Terminal width: find the minimum and maximum width of each solderable lead or electrode. This controls the transverse pad width and side-joint allowance; body width is not a substitute for a narrow lead.
Terminal length: record the solderable length and its limits. For opposing terminals, it helps establish the gap between their inner edges and the available heel connection.
Lead span: locate the outside-to-outside terminal dimension. On a gull-wing package this extends beyond the molded body; using body length here would shorten the calculated outer land span.
Pitch: identify the center-to-center terminal spacing. Check adjacent copper after calculating pad width, because a suitable side allowance on one lead may leave inadequate separation from its neighbor.
Body dimensions and height: retain their limits for courtyard, silkscreen and mechanical checks. These dimensions describe placement space, while terminal geometry determines the solder connection.
Exposed-pad dimensions: capture the center pad, its location and its electrical assignment. Check whether it has a separate terminal number and a device-specific paste or via recommendation.
Minimum and maximum limits: convert each tolerance explicitly. A dimension of 0.40 ± 0.05 mm has limits of 0.35 and 0.45 mm and a total range of 0.10 mm; entering 0.05 as the full range changes the calculation.

Where a calculator requests fabrication and placement tolerances, use the definitions required by that tool’s method. A plus/minus coordinate accuracy, a total tolerance range and a true-position diameter are not interchangeable inputs.

How Do You Calculate an IPC-7351 Land Pattern?

Start with terminal limits, select the solder-joint goals and combine the relevant component, fabrication and placement tolerances. For an opposing-terminal pattern, the main outputs are the outer land span Z, inner gap G and land width X. These describe the copper arrangement rather than the body outline.

Output	Geometric meaning	Main joint relationship
Z	Outside edge to outside edge of opposing lands	Toe allowance beyond the terminal ends
G	Clear gap between the inner land edges	Heel allowance toward the package center
X	Width of one land across the terminal	Side allowance beside the terminal

Toe, heel and side joint goals control different land edges: increasing the toe goal generally extends Z; increasing the heel goal generally reduces G; increasing the side goal generally widens X. The selected component-family method determines the actual values, signs and tolerance treatment. A gull-wing heel goal should not be transferred to a chip termination or BGA ball.

The calculation path is: drawing limits → family and density choice → joint goals and process tolerances → Z, G and X → individual pads. Check the resulting copper against the terminal extremes, then against neighboring pads and the intended assembly process.

For the IPC presentation’s opposing-terminal outer-span model, the relationship can be written as:

Z = Lmin + 2JT + R

R = √(C² + F² + P²)

Here Lmin is the minimum outer terminal span, JT is the toe goal, C is the component span tolerance, F is fabrication tolerance and P is placement tolerance, expressed in that model’s conventions. The root-sum-square term combines variation; it is not another fillet goal. G and X use their corresponding terminal dimensions and heel/side goals.

For two equal rectangular lands centered symmetrically about the origin, the last step is simple geometry:

Pad length Y = (Z − G) / 2

Pad-center distance = (Z + G) / 2

Each center lies at ±(Z + G)/4 along the component’s length axis, and each land has width X. These relationships convert an already selected land pattern into CAD objects; they do not determine the joint goals or replace the tolerance calculation. The real resistor example below uses this conversion with manufacturer-recommended dimensions.

How Do You Choose IPC-7351 Density Levels A, B and C?

Select the density level by balancing the joint geometry, placement space and process capability. Within a supported component family, the three choices generally move from more generous to more compact land patterns and courtyard allowances. The amount of that change is family-dependent; it is not a single scale factor applied to every pad.

Level	Lands	Courtyard allowance	Selection context
A — Maximum	More generous	Typically larger	Extra assembly or service space where the process benefits
B — Nominal	Medium	Typically medium	An initial choice for a documented general assembly process
C — Least	More compact	Typically smaller	Tight layouts with a proven process

Level A: compare the additional copper and placement area with the actual soldering and service needs. Extra allowance can improve access, but a courtyard alone does not prove that a rework nozzle will fit or that the larger paste deposit is suitable.
Level B: use the nominal family targets as a starting point, then compare the result with the manufacturer’s attachment recommendation. A default selection is useful only when its underlying tolerances match the intended process.
Level C: examine the smallest pad gaps, mask webs, paste apertures and available placement margin before committing to the compact option. If the fabricator or assembler cannot support those features, change the footprint choice or placement rather than suppressing the design-rule warning.

IPC-7351 density levels are not IPC product Classes 1, 2 and 3. Neither a Level A footprint nor a larger courtyard establishes an assembly’s reliability classification.

How Do You Use an IPC-7351 Land Pattern Calculator?

Enter component and process data, generate the geometry, then compare the exported result with the package recommendation. An IPC-7351 land pattern calculator is most useful when its inputs and outputs remain visible and reviewable.

Select the component family and method. Choose the actual terminal structure, such as chip, gull-wing or QFN, and record the implemented standard revision. The input diagram should match the package drawing.
Enter the dimensional limits. Supply pitch, terminal width and length, outside span, body dimensions and any exposed pad. Verify the units and the meaning of every min/max field before generating a preview.
Set density and process inputs. Choose the family-specific joint goals and supported fabrication and placement tolerances. Save those settings with the footprint so a later reviewer can reproduce the result.
Read the generated outputs. Check pad width and length, inner gap, overall span and courtyard; inspect the name, numbering, origin and any optional mask or paste layers. Some tools generate more of these objects than others.
Compare and export. Overlay the copper with the manufacturer’s recommended footprint and investigate differences. Reopen the exported CAD footprint to confirm that its pad geometry and layer assignments match the reviewed preview.

Before using an older IPC-7351 land pattern viewer, check its supported standard revision and export features. A working preview does not establish that the tool is current or supported.

How Is an IPC-7351 Courtyard Defined and Sized?

A courtyard is a library placement boundary used to check a component against its neighbors. It supports placement DRC and assembly-space planning by enclosing the relevant component and land-pattern envelope with an added allowance.

Establish the controlling boundary in each direction: leads or copper lands may extend beyond the body. Apply the documented component-family and density-level allowance outside that envelope. Library conventions can differ in their dimensional basis and rounding, so compare an imported courtyard with its source method before adjusting it.

IPC-7351, illustrative copper lands and component envelope inside a dimensioned courtyard

For an illustrative geometric example, not an IPC default, take a 3.40 × 2.10 mm controlling envelope and an agreed excess of 0.25 mm per side:

Width = 3.40 + 2(0.25) = 3.90 mm

Height = 2.10 + 2(0.25) = 2.60 mm

Place that boundary on the CAD courtyard layer and run placement checks on the actual board. Investigate overlaps against the assembly plan; do not shrink the whole library to make warnings disappear. Additional rework or electrical spacing belongs in separate constraints.

How Much Component Spacing Is Required Beyond the Courtyard?

There is no single IPC-7351 component spacing value suitable for every package and assembly process. Courtyard checks answer one placement question; they do not replace copper, insulation or tool-access checks.

Check	What controls it
Courtyard separation	The selected land-pattern method and library allowance
Copper spacing	Actual copper edges, electrical requirements and fabrication capability
Creepage and clearance	Working voltage, insulation system, environment and applicable product requirements
Assembly access	Placement equipment, neighboring component shapes and the SMT process
Rework access	Package removal method, tooling and nearby heat-sensitive parts

If two facing courtyards each include 0.25 mm beyond their underlying envelopes and their boundaries touch, the example produces a 0.50 mm envelope gap. That does not make 0.50 mm a universal body gap or an approved rework clearance. Measure each required separation between the physical features to which that requirement applies.

For a dense area, review the limiting pair of components with the assembler. A local, documented exception can preserve useful DRC elsewhere; a global reduction removes the warning from unrelated placements as well.

How Does IPC-7351 Apply to 0402 and 0603 Components?

There is no universal IPC-7351 pad size for every 0402 or 0603 part. Terminal construction and dimensional limits can differ between resistor, capacitor and inductor families, even when their nominal body sizes match.

First resolve the size-code system. These are common nominal body-size families, not pad dimensions:

Imperial code	Metric code	Nominal body size
0201	0603	0.6 × 0.3 mm
0402	1005	1.0 × 0.5 mm
0603	1608	1.6 × 0.8 mm

Consider the actual Vishay D11/CRCW0603 e3 package. Its D/CRCW e3 datasheet, revision 14-Apr-2026, page 11, gives L = 1.55 +0.10/−0.05 mm, W = 0.85 ±0.10 mm, H = 0.45 ±0.05 mm and T1/T2 = 0.30 ±0.20 mm. Thus L spans 1.50–1.65 mm, while each termination-length limit spans 0.10–0.50 mm.

The same page recommends this reflow land pattern: G = 0.75 mm, Y = 0.75 mm, X = 1.00 mm and Z = 2.25 mm. It references IPC-7351 among its design considerations; it does not identify these values as a particular density-level calculation.

IPC-7351, Vishay 0603 reflow land dimensions with outer span, inner gap, pad width and center spacing

To draw that pattern in CAD:

Create two rectangular copper lands. Set length along the component axis to 0.75 mm and transverse width to 1.00 mm.
Place their centers at (−0.75, 0) and (+0.75, 0) mm. The resulting center distance is 1.50 mm.
Measure the finished geometry. The inner gap is 1.50 − 0.75 = 0.75 mm; the outer span is 1.50 + 0.75 = 2.25 mm.

This is a manufacturer-recommended reflow example, not a reconstructed IPC calculation with invented fabrication, placement or fillet inputs. To generate a different density variant, enter the actual terminal limits and agreed process assumptions into the selected method, then compare its Z/G/X outputs with this reference. Record why any difference is accepted.

For a chip capacitor, balanced land geometry and paste deposition help limit unequal wetting forces that can cause tombstoning during reflow. For an inductor, verify where its electrodes are exposed before reusing a same-size capacitor footprint; the body outline alone cannot establish the solder connection.

How Do You Design an IPC-7351 Land Pattern for QFN Packages?

Design the perimeter connection and exposed center-pad attachment as separate, coordinated features. Use the exact device drawing to establish terminal pitch, width, length, pullback and exposed-pad geometry before selecting a generic QFN calculation.

Perimeter lands: match pad numbering and the terminal extents, then inspect neighboring copper and mask gaps. Whether the package has solder-wettable flanks affects what a side fillet or visual inspection can establish.
Exposed pad: follow the specified electrical connection and thermal layout. Confirm pad number, dimensions and location; a generic QFN outline does not establish the center pad’s net or the via arrangement.
Paste apertures: coordinate segmentation, stencil thickness and the intended solder volume. Excess solder under the center can lift the package and compromise perimeter joints. TI’s QFN and SON attachment guide discusses approximately 50%–70% paste-area coverage in its stated context; this is not a universal copper-pad reduction.
Thermal vias: specify their construction together with the stencil design. Open vias can remove solder from the joint area, so review via treatment and paste loss before releasing fabrication files.

The review should produce consistent copper, mask and paste layers, plus an agreed via specification. For a new assembly process, define how the hidden center joint and perimeter connections will be inspected or evaluated; visible outside edges do not reveal the entire attachment.

How Do You Design an IPC-7351 Land Pattern for BGA Packages?

Begin with the device’s ball map and PCB attachment recommendation, then fit the escape routing around the approved lands. Ball pitch alone does not define copper diameter, populated positions or mask openings.

Match the physical array. Check ball diameter, pitch, row/column labels and intentionally absent positions. The populated ball map must agree with the schematic-to-pad mapping.
Select the land and mask construction. With NSMD pads, the mask opening is larger than the copper land. With SMD pads, the mask opening defines the exposed solderable area. TI’s WCSP guidance favors NSMD in that context, but NSMD is not a blanket requirement for every BGA; use the specific device recommendation.
Prove the escape geometry. Compare pad diameter, trace width, clearance, via size and the proposed layer structure. If a route cannot fit between lands, reassess the routing and fabrication options before reducing approved pads merely to make space.

IPC-7351, NSMD and SMD pad concepts compared by copper edge and solder-mask opening

Mask definition is a separate classification from QFN or BGA terminal construction. Keep those decisions separate in the library record, and use the device’s orientation drawing to confirm A1 before exporting placement data.

How Does the IPC-7351 Naming Convention Work?

A footprint name encodes package characteristics so similar-looking geometries can be distinguished. The exact fields depend on the family and the naming implementation. Read a name with its convention, rather than assuming every CAD library uses the same string format.

For example, SOT23-95P280X110-5N encodes a SOT23-family package using these fields:

Code element	Meaning in this example
SOT23	Package family designation
95P	0.95 mm terminal pitch
280	2.80 mm nominal lead span
110	1.10 mm package height
5	Five terminals
N	Nominal-density suffix

The naming fields for QFN, BGA and chip components vary with terminal structure and package geometry:

QFN: the example TI-QFN50P350X350X100-19N carries pitch, body dimensions, height and terminal count. Preserve exposed-pad details as well; the family name alone does not describe that pad.
BGA: the pattern includes ball count, pitch, array rows/columns and body dimensions. Its internal C/N field denotes collapsing or non-collapsing balls, so it must not be confused with a nominal-density suffix used in another family.
Chip components: RESC, CAPC and INDC identify resistor, capacitor and inductor families, followed by the required body-dimension fields. A two-terminal chip does not need the same pitch-and-pin-count sequence as a multi-lead package.

Store supported part numbers, drawing revision and any custom pad geometry beside the name. Two manufacturers can share nominal package dimensions while differing in tolerances, so matching names alone does not prove interchangeable footprints.

What Does IPC-7351 Zero Component Orientation Mean?

Zero component orientation defines the CAD library’s angular reference. A board placement rotates the component relative to that reference; the library convention does not automatically match the tape pocket or assembly machine’s zero angle.

Mentor Graphics’ 2010 application note, IPC-7351B Electronic Component Zero Orientation for CAD Library Construction, shows family-specific references: pin 1 on the left for chip resistors and capacitors, pin 1 toward the upper left for QFN, and A1 toward the upper left for BGA land patterns. Other package families may place the reference pin at a different location. This application note is not the complete IPC-7351B standard.

IPC-7351, CAD reference orientation checked against PCB placement and assembly data

Check the viewing direction before copying a pin position. A component bottom view and PCB top view require the appropriate transformation. Compare the library pin map with the actual device pinout, then verify one polarized or asymmetrical part in the exported placement file. Confirm board side, origin and angle convention with the assembler so the same physical orientation survives the handoff.

Use the assembly drawing to confirm the exported pin-1 position.

Download PDF: IPC-7351B Zero Component Orientation Guide (24 pages)

Which Checks Should a Footprint Pass Before PCB Release?

Approve the part-to-board connection through five checks. Each should leave a specific reviewed output rather than a general statement that the footprint looks correct.

Component identity: match the BOM and approved alternatives to their package drawings; retain the supported part-number list.
Library layers: review copper, mask, paste, courtyard and numbering; record the calculation settings and approved exceptions.
Board placement: run copper and courtyard DRC, then resolve constrained neighbors against the assembly process.
Manufacturing exports: reopen the fabrication, stencil and placement outputs; confirm units, layers, origin, side and rotation.
Assembly verification: agree on inspection or test methods for hidden joints and unfamiliar processes, with defined acceptance criteria.

A change to the part, terminal geometry or placement convention reopens the affected checks. Keep the resulting review with the released board revision.

FAQs About IPC-7351 Land Pattern Design

Q1: Can two manufacturer part numbers share one footprint?

A1: Yes, when every approved alternative fits the reviewed geometry. Compare terminal limits, numbering, exposed pads and mounting recommendations. Record the approved part numbers so a purchasing substitution can be distinguished from a new package that still needs engineering review.

Q2: Can a 3D model prove that the copper pads are correct?

A2: No; it supports mechanical checking. A model can expose body collisions or an obvious rotation error, but its terminals may be simplified. Use the controlled drawing and pin map to verify the lands, and check soldering requirements independently of visual alignment.

Q3: Should the courtyard be printed on the silkscreen?

A3: Normally it remains a CAD placement boundary. Silkscreen serves identification and polarity marking on the physical board. Review the legend separately for readability and clearance from exposed pads instead of copying the entire courtyard onto the printed layer.

Q4: Does a courtyard check include component height?

A4: A two-dimensional courtyard does not verify vertical clearance. Compare maximum package height with shields, housings, mating parts and other mechanical constraints. Keep those limits in the mechanical review even when planar placement DRC passes.

Q5: Is pin 1 always the positive terminal?

A5: Pin numbering does not establish polarity. A resistor’s reference pin need not imply an electrical direction, and a diode’s numbered reference may be its cathode. Read the device pinout and marking convention before assigning anode, cathode or positive supply.

Q6: Can thermal vias remain open in a QFN center pad?

A6: That depends on the approved attachment process. Open holes can draw solder away from the joint. Agree on via treatment, stencil design and the required attachment with the assembler; the copper pad outline alone does not specify how the vias are manufactured.

Q7: Can an unused BGA ball be omitted from the footprint?

A7: An electrically unused ball may still be physically present. Distinguish absent positions from populated balls marked NC or reserved. Follow the manufacturer’s land and connection instructions; circuit inactivity alone does not justify removing a copper land or connecting a reserved position.

Q8: Do Gerber files preserve the complete library approval record?

A8: They preserve the exported layer images, not the full design rationale. Retain the BOM, package drawing, calculation settings and approved alternatives with the design release. Placement and assembly data are also needed to communicate the intended component identity and orientation.

Q9: Does IPC-7351 define finished solder-mask and paste-aperture sizes?

A9: Do not treat a copper-land result as a complete mask or stencil specification. A footprint tool may generate those layers, but their settings still need review against the device recommendation, mask process, stencil thickness and required solder deposit before manufacturing release.

Q10: Is there a universal IPC-7351 pad size for 0402 or 0603 components?

A10: No; approve the pattern for the actual component and process. A useful reuse test is to compare the proposed alternative’s terminal limits and mounting recommendation with the library’s supported parts. The shared size code alone is not evidence that the existing pads remain suitable.

Conclusion

IPC-7351 provides a structured route from component geometry and process assumptions to SMT land patterns. Reliable footprints require the inputs and resulting copper arrangement to be checked together, with the applicable standard edition recorded.

For PCB/PCBA manufacturing or a free DFM review of custom footprints, send EBest Circuit the Gerber files, BOM, package drawings and placement data at sales@bestpcbs.com. Include build quantity and any constrained spacing or approved footprint exceptions so the team can review the proposed build and prepare a quotation.

IPC-2222 Standard Explained: Rigid PCB Types, Materials, Holes, Spacing and Design Requirements

September 1st, 2026

IPC-2222 is the sectional design standard for rigid organic printed boards. Used with IPC-2221, it brings the discussion down to the physical details of a rigid board: materials, construction, thickness, mechanical features, holes, lands and conductor geometry. IPC currently lists IPC-2222B, issued in October 2020, as the latest revision.

The document is useful because it turns a broad PCB design requirement into information that can be placed on a stackup, drawing or fabrication dataset. It does not replace every electrical, thermal, manufacturing or acceptance standard. Instead, it shows which rigid-board details need to be settled and where those details connect with other IPC documents and the finished board.

IPC-2222 rigid PCB design title above a centered green rigid PCB

What Is IPC-2222 and When Is It Used?

Use IPC-2222 when the interconnecting structure is a rigid organic printed board. It is read alongside IPC-2221 when the board type, material system, construction, holes, lands, profile and rigid-board circuit features have to be defined.

IPC-2221 supplies the generic design foundation; IPC-2222 adds the details that belong specifically to rigid boards. A fabrication drawing can cite IPC-2222 and still be incomplete if it omits the applicable generic, performance or procurement requirements.

Put the approved revision on the fabrication drawing or controlled standards list. The IPC document revision table lists IPC-2222B from October 2020 and IPC-2222A from December 2010. Once a revision is contractually selected, it remains the baseline until the project formally changes it.

What Types of Rigid PCBs Does IPC-2222 Cover?

IPC-2222 covers six construction types. They are distinguished by conductive-layer structure, blind or buried vias and the presence of a metal core. The type describes how the board is built; it says nothing by itself about performance class.

PCB Type	Board Structure	Design Focus
Type 1	Single-sided printed board	One conductive layer; hole and component attachment choices still need a defined material and mechanical design.
Type 2	Double-sided printed board	Two conductive layers with the applicable through-hole and interconnection design.
Type 3	Multilayer board without blind or buried vias	Stackup, plated-through holes, registration and internal plane relationships become central.
Type 4	Multilayer board with blind and/or buried vias	Via depth, sequential construction and the applicable interconnection controls must be defined.
Type 5	Multilayer metal-core board without blind or buried vias	The metal core changes the material, electrical isolation, thermal and fabrication decisions.
Type 6	Multilayer metal-core board with blind and/or buried vias	Metal-core construction and non-through interconnections must be reviewed together.

Type 3 and Class 3 are different designations. Type 3 describes a multilayer construction without blind or buried vias. Class 3 refers to performance expectations under the applicable performance and acceptance documents. When both matter, state both.

How Does IPC-2222 Relate to IPC-2221 and Other PCB Standards?

The standards are easiest to separate by the job each one performs. IPC-2221 provides the generic design basis, IPC-2222 adds rigid-board requirements, IPC-6012 addresses qualification and performance, and IPC-A-600 illustrates bare-board acceptability.

Standard	Primary Role	When It Applies
IPC-2221	Generic printed board design requirements	Provides the common design framework used with the relevant sectional standard.
IPC-2222	Sectional design standard for rigid organic printed boards	Adds rigid-board-specific construction, material, mechanical, hole, land and circuit-feature requirements.
IPC-2223	Sectional design standard for flexible printed boards	Applies to flexible and rigid-flexible board applications instead of treating them as ordinary rigid boards.
IPC-2226	Sectional design standard for HDI printed boards	Adds HDI-specific design requirements and considerations where high-density interconnect technology is used.
IPC-6012	Rigid PCB qualification and performance specification	Defines the applicable delivered-board performance and qualification requirements.
IPC-A-600	Bare printed board acceptability illustrations	Supports visual interpretation of acceptance criteria together with the governing procurement documents.

The IPC design standards list assigns IPC-2222, IPC-2223 and IPC-2226 to different board technologies. The publisher’s IPC-6012 description places that document in qualification and performance. They work together, but evidence against one document cannot stand in for evidence against another.

Rigid PCB, stackup and fabrication drawing representing the IPC-2222 design-document hierarchy

What Are the Main Design Requirements in IPC-2222?

IPC-2222 defines the rigid-board details that sit beneath a generic PCB design. It touches electrical and thermal subjects, but it is not the sole source for current capacity, signal integrity, thermal analysis or every spacing rule. Those decisions may also draw on IPC-2221, product requirements and other applicable standards.

Design Area	IPC-2222 Scope
Materials	Laminate, dielectric, conductive and embedded-component materials, including property and substitution controls
Board construction	Board type, dielectric arrangement, copper construction and overall thickness
Mechanical features	Finished profile, cutouts, notches, slots, routing, scoring, datums and tolerances
Assembly interface	Board and array features that affect component attachment, handling and separation
Holes and interconnections	PTHs, unsupported holes, vias, fit, tolerance, plating and aspect ratio
Lands and planes	Land geometry, annular copper, nonfunctional lands and plane interaction
Circuit features	Edge spacing, balanced conductors, offset lands and large conductive areas
Documentation	Controlled information needed to communicate the approved rigid-board design

How Does IPC-2222 Guide PCB Material and Laminate Selection?

“FR-4” is not a complete material specification. An IPC-2222 review needs enough information to connect the laminate system, dielectric construction, copper and permitted substitutions with the board’s electrical, thermal and mechanical demands.

Laminate system: name the approved material grade or define the properties and test methods that an equivalent material must satisfy. A glass transition temperature value alone does not define the full material behavior.
Core and prepreg: show the layer sequence and target dielectric thicknesses. The design and fabrication teams should agree which dielectric separates each copper layer and reference plane.
Copper construction: distinguish starting foil from finished copper where plating changes the result. Copper thickness affects etching, spacing, current paths, thermal behavior and impedance geometry.
Material properties: review the electrical, thermal, moisture and mechanical properties that affect the application instead of selecting a laminate from one headline value.
Substitution control: state which changes require engineering approval. A substitute that changes dielectric, thermal-expansion or pressed-thickness behavior can invalidate an otherwise completed review.

This is a material-definition exercise, not a full stackup tutorial. The review succeeds when the proposed construction can be checked without guessing which laminate, dielectric or copper assumptions were used.

What Does IPC-2222 Require for PCB Thickness, Profiles and Mechanical Features?

Mechanical fit depends on the finished board, not the nominal CAD model. Finished thickness, the delivered profile and functional datums must still fit the connector, enclosure, guide rail or mounting system at their tolerance limits.

Finished thickness: state a nominal value and the applicable overall tolerance. Compare the complete delivered range with card-edge connectors, guides, press-fit tooling and enclosure slots.
Board profile: provide closed, unambiguous outline geometry and identify the dimensions that control the finished edge.
Cutouts, slots and notches: define finished size, position, corner radius and plated status where relevant. Check the geometry against mating hardware and router capability.
Mechanical datums: locate mounting holes, connectors and critical features from shared datums. Temporary panel rails should not control the dimensions of the delivered board.
Tolerance purpose: tighten only the dimensions that protect an actual interface. Unnecessary tolerance reduction can lower yield without improving product function.

How Does IPC-2222 Address Panelization, Routing and V-Scoring?

Routing, scoring and breakaway features define both the finished edge and the stress applied during depanelization. That is why they belong in the rigid-board design review. The IPC-2222B public contents specifically name scoring parameters, V-groove conductor clearance, low-stress breakaway tabs, mouse bites, routed slots and a break line.

Panel borders: define rails, tooling features and the relationship between the array and the delivered boards.
Routing: show routed outlines, internal channels and slots with the finished dimensions and process tolerances that matter to the board.
V-scoring: agree the score geometry, residual web and conductor clearance with the fabricator. The score path and separation method should not be inferred from a line on an assembly drawing.
Breakaway tabs and mouse bites: place them where separation will not load fragile components or leave an unacceptable edge.
Copper and component clearance: evaluate the worst-case remaining distance after routing or scoring variation, not only the nominal CAD distance.

The PCB panelization guidelines cover assembly-side choices in more detail. If a tab, rail, score or routed channel changes, review it again; the change can affect handling, separation stress and the delivered edge.

What Does IPC-2222 Require for PTHs, NPTHs and Vias?

Start with what the hole does, then define its finished condition. Drill-tool size, finished-hole size, plating, tolerance, aspect ratio and component fit belong to one tolerance chain. Copying those values separately from another board can produce a combination that no longer fits or plates as intended.

Plated-through hole: define the finished hole and compare its minimum size with the maximum component-lead envelope. Confirm that the remaining clearance supports insertion and the intended soldering process.
Via: select the drill and finished geometry with the plated depth, board thickness, land size, registration and the fabricator’s process capability.
Unsupported or non-plated hole: identify the hole as non-plated, state its finished size and tolerance, and review nearby copper and hardware contact.
Press-fit hole: use the connector manufacturer’s finished-hole, plating, insertion and qualification requirements. An ordinary soldered-hole fit cannot define a press-fit interface.
Aspect ratio: evaluate plated depth relative to drill diameter with the proposed stackup and process. It is a manufacturing review input, not one universal target for every supplier.

Consider an illustrative round lead specified as 0.60 ± 0.02 mm and a finished plated hole of 0.78 ± 0.05 mm. These are example design inputs, not IPC-2222 minimum limits.

Parameter	Minimum-Clearance Case	Maximum-Clearance Case	Review Check
Lead diameter	0.62 mm maximum	0.58 mm minimum	Include lead shape, plating, straightness and positional variation.
Finished hole	0.73 mm minimum	0.83 mm maximum	Confirm the drawing specifies finished size rather than drill-tool size.
Diametral clearance	0.11 mm	0.25 mm	Check insertion and soldering across the complete assembly tolerance chain.

The minimum diametral clearance is 0.73 − 0.62 = 0.11 mm; the maximum is 0.83 − 0.58 = 0.25 mm. A square lead needs its maximum corner-to-corner envelope checked against the minimum hole. Multi-pin insertion also depends on lead position, hole position and straightness.

Plated through-hole cutaway showing the IPC-2222 relationship between a component lead, finished hole and copper barrel

How Does IPC-2222 Address Lands, Annular Rings and Plane Clearance?

Hole size, land size, remaining annular copper and plane clearance have to be reviewed together. Increasing the land may protect the annular ring, yet reduce isolation to an unrelated plane. Treating either check alone hides that tradeoff.

Start with hole function and finished size. The land must suit the plated or non-plated feature and the connection it is expected to make.
Add fabrication allowance and registration. Drill position, layer registration, etching and finished-hole variation determine the copper that remains at the narrowest point.
Evaluate the annular ring. The centered CAD difference between pad and hole diameters is only the nominal starting point.
Recheck plane clearance. A larger land can improve remaining copper while reducing isolation to an unconnected plane.
Choose the plane connection. Thermal relief or a solid connection should follow electrical duty, heat flow, copper thickness and soldering needs.
Decide how to treat nonfunctional lands. Removal can affect registration support and clearance; retention can constrain routing and plane geometry.

The PCB annular ring guide develops this geometry further. Whenever a land changes, repeat the annular-ring, plane-clearance and conductor-spacing checks before closing the design.

What Does IPC-2222 Say About Conductor Features and PCB Edge Spacing?

Conductor geometry must survive both copper processing and edge formation. IPC-2222B specifically names printed board edge spacing, balanced conductors, offset lands and large conductive areas among its circuit-feature topics.

Printed board edge spacing: measure from the finished routed or scored edge and include process tolerance. A nominal CAD clearance does not describe the minimum delivered distance.
Balanced conductors: review copper distribution through the stack and across the panel. Strong asymmetry can contribute to distortion and should be discussed before release.
Offset lands: use offset geometry only when the connection and fabrication allowances remain clear; do not treat it as a generic repair for congested routing.
Large conductive areas: evaluate their electrical and thermal role together with copper balance, etching and assembly heat flow.
Edge-process interaction: repeat the spacing check after changing routing, V-scoring, tabs, mouse bites or the board datum that defines the final profile.

What Changed from IPC-2222A to IPC-2222B?

IPC-2222B supersedes IPC-2222A and reorganizes several material, mechanical, interconnection and circuit-feature topics. The public previews for IPC-2222A and IPC-2222B reveal headings and table titles, not every requirement or numerical change. The comparison below is therefore a review guide rather than a clause-by-clause redline.

Design Area	IPC-2222A	IPC-2222B	B-Revision Review
Material properties	Table 4-1 focuses on clad-laminate UL maximum operating temperatures.	Section 4.3.1 is “UL Parameters,” and Table 4-1 covers typical thermal properties of selected dielectrics.	Review the complete material property set and its test methods rather than carrying forward one temperature value.
Embedded component materials	No standalone embedded-component-materials section appears in the A preview contents.	Section 4.5 is “Electronic (Embedded) Component Materials.”	Identify the additional construction controls when components or materials are embedded.
Assembly array	Section 5.3.1 is “Assembly, Palletization and Test.”	Section 5.3.1 is “Assembly Array (or Pallet).”	Review the controlled array, rails, tooling features and separation method.
Overall thickness	Table 5-3 is “Printed Board Thickness Tolerance Levels.”	Table 5-3 is “Printed Board Overall Thickness Tolerance Levels.”	Confirm the delivered overall range required by connectors and mechanical interfaces.
Interconnection lands	The A preview proceeds to pad-to-plane clearance without a separate fabrication-allowance table.	Table 9-1 is “Minimum Standard Fabrication Allowance for Interconnection Lands.”	Recheck land geometry with process allowance before approving annular-ring or plane-clearance changes.
Plated-hole data	The preview lists PTH aspect-ratio and minimum diameter-tolerance tables.	The preview lists plated-hole aspect ratio, LMC/MMC hole-size limits and a recommended minimum drill-size table.	Revalidate drill, finished-hole limits, plating, aspect ratio and component fit as one chain.
Breakaway and edge features	The preview lists low-stress breakaway tabs and routed slots.	The figure titles explicitly include mouse bites, routed slots and a break line; the contents also name printed board edge spacing.	Recheck tabs, scoring, routing and minimum delivered copper-to-edge distance.

Use the authorized editions before applying clause values or making a compliance claim. When a project moves from A to B, record the revision decision and update every affected design and procurement document.

How Should IPC-2222 Be Applied During PCB Design and DFM Review?

A practical review moves from board identity to controlled production data. DFM then tests the proposed design against a manufacturing process. It cannot choose the applicable standards, product requirements or approved exceptions on behalf of the project.

Determine the board type. Identify the layer structure, blind or buried vias and any metal-core construction.
Confirm the applicable IPC documents. Record the IPC-2221 and IPC-2222 revisions, performance basis and any customer-specific requirements.
Define materials and construction. Approve the laminate system, dielectric sequence, copper build, finished thickness and impedance information.
Review mechanical dimensions. Check the delivered profile, datums, cutouts, slots and component or enclosure interfaces at tolerance extremes.
Check holes and lands. Separate PTH, via, press-fit and NPTH requirements; then review finished size, fit, aspect ratio, registration and annular copper.
Check plane and edge clearance. Evaluate the complete tolerated hole-and-land feature and the minimum copper distance after the edge process.
Review panel features. Confirm routing, scoring, tabs, mouse bites, rails, handling and separation effects.
Release controlled production data. Reopen the final outputs and verify that the fabrication data, drill files, stackup and drawing describe the same revision.

What Files and Documentation Are Needed for an IPC-2222-Based PCB Design?

The released files must describe one approved board construction without contradiction. IPC-2222 does not prescribe a universal upload package, so the exact records depend on the product, contract and manufacturing route.

Gerber, ODB++ files or another agreed fabrication format: copper, mask, legend, profile and other released layers.
NC drill and rout data: plated and non-plated holes, slots, routed channels and any controlled-depth features.
Fabrication drawing: board revision, dimensions, datums, tolerances, surface finish, scoring or routing and applicable standards with revisions.
Stackup: material, dielectric construction, copper build, finished thickness and impedance information.
Hole table: hole functions, finished sizes, tolerances, plated status and special press-fit or component requirements.
Special requirements: approved substitutions, coupons, reports, inspection, test and any agreed exceptions.

After accepting a DFM change, update every file it touches. An approval email is not enough if the released drill table, stackup or drawing still carries the old value.

Rigid PCB with controlled stackup, drill data, fabrication drawing and CAM layers for an IPC-2222-based design

What Are the Most Common IPC-2222 Design Mistakes?

Most IPC-2222 mistakes begin with a wrong assumption about scope or with a nominal value taken out of its tolerance chain. Both can pass a superficial checklist while leaving the board definition incomplete.

Treating IPC-2222 as a standalone standard: use it with IPC-2221 and the applicable performance, procurement and acceptance documents.
Confusing PCB type with performance class: Type 3 describes a multilayer construction; it does not automatically mean Class 3.
Specifying only nominal board thickness: include the finished tolerance and test the complete range against mechanical interfaces.
Confusing drill size with finished-hole size: plating and process compensation separate the tool diameter from the delivered opening.
Increasing land size without rechecking plane clearance: more annular copper can reduce isolation to unconnected copper.
Ignoring the edge process: routing and scoring tolerances determine the minimum delivered copper-to-edge distance and separation stress.
Using an outdated revision reference: identify the contractual revision and formally review any move from IPC-2222A to IPC-2222B.
Treating DFM approval as automatic IPC compliance: DFM confirms selected manufacturing conditions; it does not choose every applicable standard or product requirement for the designer.

How Can EBest Circuit Support Rigid PCB Design and Manufacturing?

EBest Circuit can check whether the proposed rigid-board construction is buildable and whether the released files agree. The free DFM review supports prototype and production preparation, while standards selection, product qualification and compliance responsibility remain with the customer and project owners.

Materials and stackup: review the proposed laminate system, copper build, finished thickness, impedance targets and substitution boundaries.
Holes and lands: compare finished-hole intent, aspect ratio, annular copper, plane clearance and special connector requirements with the proposed process.
Board edge and panelization: review routing, cutouts, V-scoring, tabs, rails and copper or component clearances.
CAM and document consistency: compare Gerber or ODB++, NC drill, stackup and fabrication drawing for revision, outline, hole and construction conflicts.
Prototype to production: keep approved DFM changes in the controlled files used for the prototype, follow-up builds and inspection plan.

Send your Gerber or ODB++ files, drill files, stackup and fabrication drawing to sales@bestpcbs.com for rigid PCB DFM review and quotation.

FAQs About IPC-2222

Q1: Is IPC-2222B the latest revision of IPC-2222?

A1: Yes, according to the IPC revision table checked on September 1, 2026. It lists IPC-2222B with an October 2020 date. Check the table again at project start and follow the revision named by the contract.

Q2: Where can I get the official IPC-2222 standard or IPC-2222B PDF?

A2: IPC provides a four-page preview that confirms the document identity, scope and contents. The preview is not the full standard, so use an authorized edition before applying clause values. Download the official IPC-2222B PDF preview (4 pages).

Q3: Can IPC-2222 be used without IPC-2221?

A3: No. IPC-2222 adds rigid-board-specific design requirements to the generic framework in IPC-2221.

Q4: Does a Type 3 board mean a Class 3 board?

A4: No. Type describes board construction; class describes performance expectations under the applicable documents.

Q5: Does IPC-2222 cover metal-core rigid PCBs?

A5: Yes. Types 5 and 6 are multilayer metal-core constructions. The project still has to define the material system, isolation, thermal conditions and supplier agreements.

Q6: Does IPC-2222 contain every electrical and thermal PCB design rule?

A6: No. IPC-2222 includes rigid-board electrical and thermal topics, but current capacity, signal integrity and detailed thermal analysis may also depend on IPC-2221, other standards and the product specification.

Q7: Are press-fit holes designed like ordinary soldered PTHs?

A7: No. Use the connector manufacturer’s finished-hole, plating, insertion and qualification requirements.

Q8: Does a fabricator’s DFM approval prove IPC compliance?

A8: No. DFM can confirm that selected features suit a manufacturing process. Compliance also depends on the chosen standards and revisions, the product requirements and any documented exceptions.

Q9: Should flex, rigid-flex or HDI boards use only IPC-2222?

A9: No. IPC identifies IPC-2223 for flexible and rigid-flexible applications and IPC-2226 for HDI printed boards. Use the standards that match the actual technologies in the design.

Q10: Which files should be sent first for an IPC-2222-based review?

A10: Send the current Gerber or ODB++, NC drill data, stackup and fabrication drawing first. Include any component or mechanical requirement that controls hole fit, finished thickness or the board edge.

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