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Castellated PCB Manufacturing, Assembly, and Inspection
Monday, August 24th, 2026

A Castellated PCB is a module board with plated holes cut through its edge so the remaining half-holes can be soldered directly to matching pads on a carrier board. A reliable result depends on four connected decisions: the module edge must be manufacturable, the carrier footprint must support a controlled solder joint, the assembly process must limit movement and solder loss, and inspection must confirm both the plated edge and the completed joint.

This guide is written for hardware designers, manufacturing engineers, quality teams, and sourcing teams who need to release a castellated module without treating the edge connection as an ordinary row of vias. It explains what to specify in fabrication data, what to check during assembly, which defects change electrical or mechanical performance, and what evidence should accompany a production order.

Before requesting a fabrication and assembly review, prepare the proposed stackup, Gerber or ODB++ data, NC drill file, module drawing, carrier-board footprint, quantity, and inspection requirements. EBest Circuit can use those inputs to identify open manufacturability questions before pricing.

Castellated PCB, plated half-hole module under optical inspection

What Must Be Confirmed Before Manufacturing a Castellated PCB?

A Castellated PCB release should proceed only after the board-edge geometry, finished-hole intent, surface finish, panel support, carrier footprint, and acceptance evidence are specified together. These inputs are linked: changing the routed outline changes the remaining half-hole, which changes the carrier-pad overlap, solder volume, and visible inspection result.

The following release map separates design intent from factory interpretation and shows which record should close each decision.

Release Input Decision Required Risk if Undefined Approval Record
Board outline and drill data Confirm which plated holes the routed edge intersects and how much hole remains Uneven half-holes, exposed substrate, or an edge that misses the plated barrel CAM image or marked fabrication drawing
Pad and annular-ring geometry Preserve enough copper on the outer layers and required inner layers after routing Weak edge plating, copper breakout, or local delamination during depanelization ODB++ or Gerber review plus stackup
Surface finish Choose a finish compatible with the edge geometry, storage plan, and soldering process Poor wetting, excessive thickness variation, or finish damage at the routed edge Purchase specification and supplier confirmation
Panel and break-tab plan Keep tabs, rails, and tooling features away from functional castellated edges Burrs, crushed plating, module distortion, or uncontrolled manual rework Approved panel drawing
Carrier-board land pattern Match module pitch, body outline, solder fillet space, and placement tolerance Open joints, bridging, module rotation, or insufficient visible fillet Footprint drawing and assembly review

A quotation should state which inputs remain provisional. If the factory must choose the finished hole, remaining-hole ratio, panel-tab position, or carrier-pad extension, those decisions belong in the engineering-question record rather than being inferred silently during CAM.

How Are Castellated Half-Holes Formed and Finished?

Castellated PCB half-holes are normally produced by plating complete drilled holes first and routing the final board outline through those plated barrels afterward. The sequence matters because drilling, copper deposition, surface finish, routing, cleaning, and inspection each affect a different part of the remaining edge.

Step 1: Register the drill and outline. CAM must confirm that the finished outline intersects the intended plated-hole centers within the supplier’s routing and registration capability. The check uses the released drill file, outline layer, fabrication drawing, and the supplier’s documented tolerance; an offset cut can leave too little barrel or too much protruding copper.

Step 2: Plate the complete hole. The drilled barrel receives the same hole-wall preparation and copper-plating controls required by the applicable board construction. Copper continuity should be evaluated before routing because the cut edge cannot restore a thin, voided, or poorly bonded barrel.

Step 3: Apply the specified surface finish. The purchase data must name the finish and any thickness or storage requirements that matter to assembly. Finish selection is order-specific; one supplier’s published minimum hole or preferred finish should not be treated as a universal design rule.

Step 4: Route through the plated barrels. A suitable tool, feed strategy, support method, and cut direction are selected to limit copper tearing, resin smear, and edge burrs. The factory should verify the routed sample at magnification before the lot proceeds when the geometry is new or near its process boundary.

Step 5: Clean and inspect the edge. Loose copper, laminate debris, plating stubs, and conductive particles must be removed without thinning the usable barrel. Final inspection compares the remaining copper, edge condition, pitch, and board dimensions with the approved drawing and acceptance plan.

Castellated PCB, plated half-hole panel inspected under an optical microscope

The manufacturing sequence above is consistent with Eurocircuits’ published explanation of plating complete holes before routing through the barrels. Its published dimensions are useful examples of one supplier’s process, but the order must use the capability statement of the factory that will build the board.

Which Board-Edge Details Control Castellated Hole Quality?

Castellated PCB edge quality is controlled by the routed split position, copper retained around the barrel, solder-mask clearance, local laminate support, and distance from panel tabs. These features determine whether routing leaves a stable plated semicircle or a damaged copper shell with little mechanical support.

Nominal remaining plated-hole width = finished hole diameter ÷ 2

This relationship applies only when the routed outline passes through the finished-hole centerline. Drill registration, routing registration, tool runout, copper condition, and the supplier’s finished-edge tolerance still determine the acceptable production window.

  • Split position: Show the finished edge through the intended hole location and obtain a CAM image of the resulting half-hole. A centerline assumption is not enough when routing and drill registration consume a large share of the remaining copper.
  • Copper retention: Specify outer-layer pads and any required inner-layer support so that routing does not remove the copper needed to anchor the barrel. The acceptable geometry must come from the chosen supplier’s stackup and capability review.
  • Solder-mask opening: Keep mask from covering the area intended to wet, but avoid unnecessary exposed copper that can collect excess solder or reduce spacing to adjacent nets. Review the actual mask swell used in CAM.
  • Edge clearance: Keep unrelated traces, planes, components, and mechanical features outside the supplier’s routed-edge clearance. An exposed plane or trace at the cut edge can create corrosion, shorting, or handling risk.
  • Tab separation: Reserve nonfunctional edge length for panel support. A mouse bite or break tab across a functional plated half-hole can tear copper and make the final module dependent on manual filing.

Prototype data should also identify intentional full holes, slots, or header pads near the castellations. These features can change paste flow and local copper balance, so the supplier must distinguish them from the plated holes intended to be routed.

How Should a Carrier PCB Footprint Support a Castellated Module?

A Castellated PCB carrier footprint must give every half-hole a matching pad, enough exposed copper for a controlled fillet, and a body outline that prevents placement ambiguity. The module drawing and carrier land pattern should be approved as a pair because module pitch tolerance, routed-edge tolerance, and placement tolerance accumulate at the outer joints.

  • Pad alignment: Center each carrier pad on the nominal castellated feature and verify the worst-case overlap at both ends of the row. Do not correct pitch mismatch by enlarging pads until adjacent-net spacing becomes marginal.
  • Fillet extension: Extend the carrier pad beyond the module edge only as much as required for solder deposition, wetting, and visible inspection. The amount should be validated with the stencil and reflow process rather than copied from an unrelated module.
  • Body clearance: Keep components, test points, and copper features clear of the module body, underside terminations, and any permitted overhang. Include courtyard space for placement tooling and optical inspection.
  • Assembly datum: Add a clear outline, polarity or pin-one mark, and usable fiducials so the placement program does not rely only on the castellated row. Confirm that the module can be held flat during reflow.
  • Rework access: Preserve probe and soldering access to the edge joints when field repair or engineering rework is expected. Dense neighboring parts can make a nominally visible joint impossible to inspect or touch up.

Before release, place the module footprint over the supplier’s maximum board outline and half-hole envelope. This worst-case overlay reveals end-pad loss, courtyard conflicts, and solder-mask spacing problems that a nominal 3D rendering can hide.

How Should Castellated PCB Modules Be Assembled?

A Castellated PCB module can be assembled as a surface-mount part only when paste deposition, placement support, reflow history, and joint visibility have been specified for that module and carrier board. The process should control both electrical wetting and the module’s final height, rotation, and coplanarity.

Step 1: Confirm the received module condition. Inspect the routed edges for loose plating, oxidation, contamination, bent boards, and dimensional damage before paste printing. Record the lot and sample results so fabrication damage is not confused with an assembly defect.

Step 2: Approve the stencil and paste deposit. Set aperture geometry from the carrier pad, half-hole volume, paste type, and reflow method. The trial build should check for insufficient fillet, excessive side accumulation, solder balls, and bridging rather than assuming that a full-size pad aperture is correct.

Step 3: Place and support the module. Use an outline, fiducials, and a package definition that centers the rows while keeping the body flat. Verify the placement force and nozzle contact point against the module’s component layout so the board is not bowed or damaged.

Step 4: Reflow within the approved thermal history. The carrier-board profile must wet the edge joints without exceeding the temperature exposure allowed for the module components and its previous assembly cycles. Record the measured profile on a representative assembly when the combination is new.

Step 5: Inspect before cleaning or rework. Check alignment, solder bridges, incomplete wetting, void-like gaps at visible fillets, lifted corners, and contamination. State which defects can be reworked, the permitted rework method, and when the module must be rejected.

Castellated PCB, soldered module half-holes inspected on a carrier board

A module that was previously reflowed during its own assembly will experience another thermal cycle when mounted to the carrier. Component, laminate, and solder-joint exposure therefore belongs in the assembly review, especially for reworked or moisture-sensitive modules.

Which Solder Defects Occur at Castellated PCB Edges?

The main Castellated PCB edge-joint defects are opens, partial wetting, bridging, excess solder, module lift, and contamination, but the visible symptom does not identify the cause by itself. Diagnosis should connect the joint appearance to paste deposition, pad geometry, module condition, placement, and thermal history.

Observed Defect Likely Process Cause Evidence to Check Corrective Direction
Open or weak fillet Low paste volume, poor wetting, edge contamination, module lift, or inadequate pad overlap Stencil aperture, paste inspection, edge condition, coplanarity, and profile data Restore wettable surfaces and validate deposit, support, and land pattern
Bridge between half-holes Excess paste, tight mask spacing, placement offset, or solder drawn from a nearby through hole Paste height, mask image, X-Y placement record, and neighboring pad geometry Reduce or reshape the deposit and correct spacing or placement
Excess side solder Oversized aperture, large exposed carrier pad, or uneven module seating Stencil data, carrier footprint, module height, and joint-to-joint variation Balance deposit volume and module support before changing reflow temperature
Lifted corner or rotated module Unequal wetting forces, board warp, placement error, or inconsistent paste volume Coplanarity, placement image, paste inspection, and corner-height measurement Correct support, deposition balance, and placement references
Intermittent connection Partial barrel damage, cracked fillet, contamination, or mechanical loading after assembly Magnified edge inspection, continuity under controlled movement, and failure-location analysis Separate fabrication damage from assembly and system-level mechanical stress

Reworking one visible joint may hide a row-level process problem. Compare several joints across the module, including both ends of each row, before deciding whether the defect is isolated or caused by systematic alignment, paste, or routing variation.

How Should Castellated Holes and Solder Joints Be Inspected?

Castellated PCB inspection should cover the bare module edge before assembly and the completed fillets afterward, using acceptance criteria tied to the drawing, joint function, and agreed workmanship standard. A cosmetic photograph is not enough; the record should identify the view, magnification, sample plan, defect limits, and disposition.

  • Bare-edge inspection: Check remaining barrel copper, routed-edge smoothness, burrs, plating folds, mask encroachment, exposed conductors, and laminate separation. Measure pitch and board dimensions when fit to the carrier is sensitive.
  • Paste inspection: Verify deposit position, area, and repeatability on the carrier pads before placement. Compare the result with the approved stencil revision rather than relying on nominal CAD apertures.
  • Post-reflow optical inspection: Confirm module alignment, visible wetting, bridge clearance, fillet continuity, corner seating, and residue condition from repeatable viewing angles.
  • Hidden-joint assessment: Use X-ray or another suitable method only when the joint geometry or underside connections contain information that optical inspection cannot reveal. State what the image must prove before ordering the test.
  • Traceable disposition: Link each defect image to the board lot, assembly lot, module position, defect code, reviewer, and rework or rejection decision. This record supports root-cause analysis if failures recur.

Supplier-specific notes can also reveal what a low-cost service treats as best-effort rather than a controlled capability. For example, OSH Park documents possible plating stubs and manual cleanup in its service context; a production order should instead state the delivered edge condition it requires.

How Do Panelization and Depanelization Affect Castellated Edges?

Castellated PCB panelization must support the module through fabrication and assembly without placing break tabs, router entry marks, or depanelization loads on functional plated half-holes. Panel rails and tab locations therefore need approval before production, not after the first edge is damaged.

  • Support path: Place rails and tabs where they can carry drilling, plating, routing, finish, handling, and assembly loads without flexing the narrow module body.
  • Functional-edge protection: Keep tabs and scoring away from plated half-holes unless the supplier has an explicitly approved process for the proposed geometry.
  • Tool access: Provide router approach and exit space that does not force an unstable tool path across copper-dense edges or nearby components.
  • Depanelization method: State whether boards are routed free, tab-routed, or separated after assembly, along with the allowed burr and edge-cleanup condition.
  • Mechanical verification: Inspect samples from different panel positions because edge quality can vary with support, tool wear, and routing direction across the panel.

A fully castellated perimeter may leave no suitable location for panel tabs. That geometry should trigger an early panelization review because a late compromise can sacrifice functional edge length or introduce manual separation work that was not included in the quote.

Which Electrical and Mechanical Tests Should Be Specified?

Testing should prove the functions and loads assigned to the castellated connection, not merely confirm that the assembly powers on once. The acceptance plan needs the applied condition, measurement point, limit source, sample size, and output record for every required test.

  • Continuity and isolation: Measure the required nets and adjacent-net isolation using limits from the released schematic, product requirement, or test specification. Record failures by module position and pin.
  • Functional operation: Exercise interfaces, power rails, programming paths, and communications at the specified supply, load, and environmental condition. A simple boot indication does not cover intermittent edge joints.
  • Mechanical retention: If the module experiences handling, shock, vibration, or connector forces, establish a product-relevant load path and acceptance condition. Do not invent a pull-force limit without a design requirement and validated fixture.
  • Thermal cycling or aging: Use only when the product risk assessment requires it, with temperature range, dwell, transition, cycles, powered state, and post-test checks stated in the test plan.
  • Failure analysis: Preserve the operating state and joint condition before rework. Localize electrical symptoms first, then correlate them with edge images, cross-sectioning, or material analysis when destructive evidence is justified.

Test coupons and sample modules should match the production stackup, finish, edge routing, carrier pad geometry, paste process, and reflow exposure. A simplified coupon can validate one mechanism, but it cannot replace assembly-level verification when the load path or thermal history is different.

What Changes Castellated PCB Cost and Lead Time?

Cost and schedule change when the edge geometry requires tighter routing control, special panel support, additional inspection, extra test coverage, or repeated engineering confirmation. The fastest way to stabilize a quote is to submit complete, internally consistent files and identify which criteria are mandatory.

Cost Driver Why It Changes Work How to Reduce Uncertainty
Fine pitch or small remaining barrel Consumes more drill-to-route registration margin and may require tighter inspection Submit the exact outline, finished hole, pad geometry, and acceptable split condition
Castellations on several edges Reduces space for panel tabs and complicates support during routing and assembly Approve a panel drawing before the order is released
Special finish or storage control Adds material, process, handling, packaging, or shelf-life requirements Name the finish and packaging requirement in the purchase specification
Assembly and rework access Changes stencil development, placement support, inspection, and repair labor Provide module and carrier assembly data plus rework limits
Custom inspection or testing Requires fixtures, programming, measurements, records, and additional review State the method, sample plan, limits, and required report format

A repeat Castellated PCB order can move more predictably when the approved panel, CAM decisions, stencil revision, profile, inspection criteria, and test records remain under revision control. Any change to hole geometry, outline, finish, carrier footprint, or module components should reopen the affected approval rather than being treated as a purchasing-only change.

What Files Should Be Included in a Castellated PCB RFQ?

An accurate RFQ needs fabrication data, module and carrier assembly data, acceptance criteria, quantity, and revision identity in one consistent package. The supplier should not have to infer the routed half-hole intent from a rendering or reconstruct the carrier footprint from a datasheet image.

  • Fabrication package: Supply Gerber or ODB++, NC drill files, board outline, stackup, copper requirements, finish, solder-mask data, dimensions, tolerances, and a drawing that identifies every castellated edge.
  • Panel requirements: State delivery format, permitted rails and tabs, tooling needs, fiducials, break-off method, and the edge condition required after separation.
  • Assembly package: Provide the BOM, centroid data, module and carrier drawings, polarity marks, paste and stencil requirements, placement constraints, and reflow limitations.
  • Inspection plan: Specify bare-edge views, solder-joint criteria, magnification, sample plan, defect disposition, required images, and any dimensional report.
  • Test package: Include the test method, fixture interface, firmware or programming instructions, input conditions, measurement points, limits, sample quantity, and report format.
  • Commercial inputs: Specify prototype and production quantities, delivery destination, target schedule, packaging, traceability, approved substitutions, and change-control contacts.

Before sending the RFQ, compare the file revision printed on the fabrication drawing, assembly drawing, BOM, centroid file, test instruction, and purchase request. A mixed-revision package can produce a technically valid quote for the wrong module.

What Castellated PCB Services Can EBest Circuit Provide?

EBest Circuit can review and quote PCB design support, prototype fabrication, mass production, component sourcing, and PCB assembly for projects that use castellated modules. The usable scope for a specific board is confirmed from its geometry, materials, quantity, carrier-board data, inspection needs, and test requirements.

  • Design and DFM review: Submit the drill, outline, pad, stackup, panel, carrier-footprint, and assembly data so open manufacturability questions can be consolidated before release.
  • Prototype fabrication: Use the first build to verify routed-edge condition, module dimensions, carrier fit, solder deposition, and inspection criteria before production quantities are committed.
  • Production fabrication: Freeze the approved CAM decisions, panel arrangement, finish, edge criteria, and change-control baseline for repeat orders.
  • Component sourcing and assembly: Provide the BOM, approved manufacturer list, module handling limits, stencil data, placement information, reflow requirements, and rework boundaries.
  • Inspection and testing: Specify the required edge images, solder-joint checks, electrical tests, fixtures, programming method, sample plan, and report format in the quotation package.

Order-specific capability, schedule, certificates, inspection records, and test coverage should be confirmed in the written quotation and engineering response. This ties the sourcing decision to the released board and its documented acceptance requirements.

FAQs About Castellated PCB Manufacturing and Assembly

Q1: Are castellated holes the same as ordinary plated through holes?

A1: No. A castellated feature begins as a plated hole, but the finished board outline removes part of the barrel. That extra routing operation changes copper support, edge quality, inspection access, and how the feature is soldered to another board.

Q2: Must exactly half of every plated hole remain?

A2: The required remaining geometry must be agreed with the selected fabricator. A nominal half-hole is common, but the drawing should state the intent and the supplier should confirm what drill-to-route registration and inspection limits it can control.

Q3: Can castellated edges use any surface finish?

A3: Finish selection is process-specific. The edge geometry, hole size, storage period, soldering method, and supplier capability all matter. Name the finish in the RFQ and obtain written confirmation for the proposed construction.

Q4: Can components be placed on both sides of a castellated module?

A4: Only when the carrier design provides the required underside clearance and assembly method. A flat-mounted module usually needs a component-free underside contact area, while a raised or recessed arrangement requires explicit mechanical and solder-joint design.

Q5: Can a castellated module be hand soldered?

A5: Hand soldering is practical for prototypes and rework when the joints remain accessible. The work instruction should control alignment, flux, heat exposure, solder amount, cleanliness, and inspection so manual results can be evaluated consistently.

Q6: Why does solder sometimes disappear into a nearby hole?

A6: An open through hole can wick molten solder away from the intended edge joint. Review the connected pad geometry, mask separation, paste deposit, and hole treatment instead of compensating with uncontrolled extra solder.

Q7: Does a certified radio module make the completed product certified?

A7: Module certification does not automatically approve the finished product. The host board, antenna implementation, enclosure, power conditions, labeling, and destination requirements may still need product-level review or testing.

Q8: Should every castellated solder joint be X-rayed?

A8: Use X-ray only when it reveals required information that optical inspection cannot show. Visible side fillets may be evaluated optically, while hidden underside connections or internal anomalies need a method selected for the actual failure risk.

Q9: Can a damaged plated half-hole be repaired with solder?

A9: Solder cannot restore missing barrel adhesion or laminate strength. Cosmetic wetting may hide torn copper or delamination, so the defect must be classified before a documented rework method is accepted.

Q10: What should be checked on the first assembled sample?

A10: Check module fit, alignment, joint wetting, bridge clearance, corner seating, electrical function, and the evidence required for production release. Retain the approved module, carrier, stencil, profile, inspection images, test record, and deviations as the baseline.

Conclusion

A successful castellated module starts with one controlled chain from plated-hole geometry to carrier footprint, solder process, inspection, and test evidence. Specify the routed edge and panel support before fabrication, validate paste and placement on representative assemblies, and release production only after the visible edge condition and functional checks meet the agreed acceptance plan.

For an engineering review and quotation, send your Gerber or ODB++, NC drill, stackup, BOM, module and carrier drawings, quantity, panel requirements, inspection plan, and test instructions to sales@bestpcbs.com. The quotation can then identify confirmed scope, remaining engineering questions, and the records required for prototype or production approval.

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Castellated PCB Design Guideline & Consideration
Thursday, November 20th, 2025

How to design a castellated PCB? This blog is mainly about design guideline and considerations, production process for castellated PCB.

Are you troubled these issues with castellated PCB?

  • Is board space extremely limited while traditional connections occupy too much area and fail reliability?
  • When welding modules to mainboards, is alignment often imprecise, causing high yield fluctuations and production costs?
  • Want compact board-to-board assembly but face complex processes, long cycles, and struggle to match product iteration speeds?

As a castellated PCB manufacturer, EBest Circuit (Best Technology) can provide you service and solutions:

  • Process Guarantee: Specializing in castellated PCB precision machining, we use unique processes and full-cycle quality control to ensure full copper plating, smooth hole walls, and stable “golden fingers” for reliable board connections.
  • Design Collaboration Optimization: Professional front-end DFM analysis services identify design-phase risks early, optimizing module layouts and castellated structures for precise alignment and efficient assembly.
  • Efficient Flexible Production: Rapid-response production lines for small/medium batches reduce lead times, flexibly align with R&D rhythms and market demands, and accelerate market entry.

Feel free to contact us if you have inquiry for castellated PCB: sales@bestpcbs.com.

What Is a Castellated Hole PCB?

A Castellan Hole PCB is a type of printed circuit board with specially designed semi-circular gold-plated holes (resembling castle crenellations) machined along its edges. Its core feature is that these holes are precisely cut into half-holes along the board edge, and the hole walls are metallized, exposing the internal conductor layers. This design allows the PCB to be soldered directly to the pads of another PCB through the metallized layer on the half-hole, just like surface mount technology (SMT) components, achieving a reliable vertical interconnection between boards.

What Is a Castellated Hole PCB?

Why Use Castellated Holes in PCB?

  • Achieving Vertical Board-to-Board Interconnection: Core Advantages. Allows one PCB to be directly and vertically soldered to the pads of another PCB via a metallized layer on a half-hole, just like a surface mount device (SMT) component, creating a compact 3D structure.
  • Significant Space Savings: Vertical stacking greatly optimizes the utilization of internal space, especially suitable for space-constrained miniaturized and portable electronic products.
  • Simplified Assembly Process: Eliminates the need for additional connectors such as sockets, pin headers, cables, or flexible printed circuit boards (FPCs) required for traditional board-to-board connections, reducing material costs and assembly steps.
  • Improved Connection Reliability: Direct SMT solder joints are formed between the metallized half-holes and the pads, providing stronger mechanical strength and electrical contact reliability than plug-in connectors, and offering better vibration resistance.
  • Reduced Overall Cost: By eliminating external connectors and their assembly costs, and simplifying the production process (compatible with standard SMT processes), the bill of materials (BOM) and manufacturing costs of the product can be effectively reduced.
  • Enhanced Design Flexibility: Facilitates modular design. Functional modules (such as Wi-Fi/BT modules and power modules) can be prefabricated as independent daughterboards with castle holes, simplifying the main system design and facilitating replacement and upgrades.

How To Design A Castellated PCB?

1. Define Design Goals and Constraints

  • Functional Requirement Definition: Engage in in-depth communication with clients to clarify electrical performance (e.g., signal speed, impedance requirements), mechanical dimension constraints (e.g., castellation pitch, height), thermal management needs (e.g., heat dissipation path, power dissipation), and environmental adaptability (e.g., temperature range, vibration resistance).
  • Standards and Specification Compliance: Adhere to international standards (e.g., IPC-2221A, IPC-4761) and client-specific specifications, including EU RoHS/REACH environmental requirements and UL safety certifications.
  • Castellation Feature Design: Determine geometric parameters for sawtooth edges (e.g., tooth width, pitch, height). Typically, tooth width ≥1.5mm ensures mechanical strength, pitch matches assembly tolerances (e.g., ±0.1mm), and height integrates thermal requirements (e.g., 30% surface area increase).

2. Stack-Up Structure and Material Selection

  • Layer Stack Planning: Design stack-up based on signal integrity needs. For high-speed digital circuits, use 6-layer structures (signal-ground-power-signal-ground-signal) to ensure impedance continuity (e.g., 50Ω single-ended, 100Ω differential).
  • Material Selection: Choose high-frequency/high-speed substrates (e.g., Rogers 4350B, Isola I-Tera MT40) to reduce dielectric loss, or high-Tg materials (Tg ≥170°C) for thermal stress resistance. Copper thickness matches current capacity (e.g., 1oz for signal layers, 2oz for power layers).
  • Ground Plane Design: Implement continuous ground planes covering critical signal areas to minimize signal return paths. Use thin dielectrics (e.g., 50μm) between power and ground planes to reduce PDN impedance.

3. Layout and Routing Strategies

  • Layout Principles: Partition functional modules (digital, analog, power zones). Place sensitive components (e.g., crystal oscillators) away from heat sources and noise sources. Avoid precision components near castellation edges to prevent mechanical stress damage.
  • Routing Rules: Route high-speed signals as differential pairs (length matching ±5mil, spacing ≥3× line width). Avoid 90° turns (use 45° or curved paths). Calculate power trace width for current capacity (e.g., 10mil width for 1A current) and use multiple vias for parallel resistance reduction.
  • Castellation Edge Handling: Add non-functional pads (e.g., 1mm×1mm) at sawtooth edges for mechanical reinforcement. Chamfer edges (e.g., R0.5mm) to reduce stress concentration.

4. Thermal Design and Heat Management

  • Heat Dissipation Path Planning: Place high-power devices (e.g., power MOSFETs) over thick copper pours (≥2oz) and connect to ground planes via thermal vias filled with solder paste. Design castellation edges as heat sinks to increase air contact area.
  • Thermal Via Design: Deploy dense thermal vias (e.g., 0.3mm diameter, 1mm spacing) under heat sources to form thermal channels. Fill vias with conductive materials (e.g., copper paste) to enhance thermal conductivity.
  • Simulation Validation: Use thermal simulation tools (e.g., ANSYS Icepak) to verify temperature distribution, ensuring peak temperatures stay below component limits (e.g., junction temperature ≤125°C).

5. Signal Integrity and EMC

  • Impedance Control: Calculate stack-up parameters to ensure critical signal line impedance matching (e.g., using Polar SI9000). Apply back-drilling to minimize stub effects.
  • Crosstalk Mitigation: Increase shielding for sensitive signals (e.g., 3W rule) or use ground shielding. Maintain sufficient spacing between high-speed differential pairs (≥3× line width).
  • EMC Design: Add π-type filters (inductor + capacitor) at power entry points. Place decoupling capacitors (e.g., 0.1μF + 10μF) near critical ICs. Avoid antenna effects at castellation edges (e.g., long traces).

6. Testability and Reliability

  • Test Point Design: Place test pads (≥1mm diameter) at critical nodes (power, signal I/O) with labeled identifiers. Boundary scan (JTAG) interfaces must comply with IEEE 1149.1.
  • Mechanical Reliability: Validate vibration resistance via stress analysis (e.g., ANSYS Mechanical). Reinforce critical connector areas with stiffeners (e.g., L-shaped copper traces).
  • DFM Checks: Perform DRC/ERC checks using EDA tools (e.g., Altium Designer, Cadence Allegro) to ensure compliance with manufacturing tolerances (e.g., minimum trace/spacing ≥4mil). Generate Gerber files and drilling data.

7. Testability and Reliability

  • Design Documentation: Compile detailed specifications (BOM, stack-up, routing rules), assembly drawings, and test procedures. Provide 3D models (e.g., STEP format) for mechanical fit evaluation.
  • Version Control: Track design changes using version control systems (e.g., Git) for traceability. Final deliverables include Gerber files, BOM, coordinate files, and process notes.
How To Design A Castellated PCB?

Castellation PCB Design Technical Parameter

Parameter NameRecommended Value/Range
Drill Diameter0.4 mm – 1.0 mm
Pad DiameterDrill Diameter + 0.2 mm
DepthBoard Thickness
Pitch≥ 0.5 mm (High-density designs may reduce to 0.4 mm with DFM evaluation)
Edge Clearance≥ 0.3 mm
Cu Plating ThicknessMinimum 20 μm (0.8 mil)
Surface FinishENIG / HASL / Immersion Tin
Hole Wall Roughness≤ 35 μm
Burr ControlNo visible burrs
Solder Mask OpeningSingle-side expansion 0.05-0.1 mm
Thermal Shock Test-40°C to +125°C
SolderabilityWetting area ≥95%

PCB Castellated Edges Design Consideration

Mechanical Strength and Dimensional Design

  • Minimum Hole Diameter Requirements: PCB half-hole diameter must be determined based on board thickness. For boards under 1.0mm thick, a minimum half-hole diameter of 0.6mm is recommended; for boards over 1.6mm thick, a minimum half-hole diameter of 1.0mm is advised.
  • Edge Spacing: Maintain a minimum distance of 10–15% of board thickness between half-hole edges and outer copper foil edges to minimize stress concentration and ensure soldering quality.
  • Pattern Consistency and Alignment: Precise alignment between pads and drilled holes is critical. Include adequate fiducial marks to reduce component misalignment risks.

Electrical Signal Integrity

  • Reference Layer Management: Avoid cutting through power and ground planes near half-holes. Implement reference layer bridging (keep-out area bridge design) to mitigate impedance mismatches.
  • Shielding Design: For RF/high-frequency applications, incorporate metallized shielding edges and alternating pad layouts to reduce EMI.
  • Coaxial Signal Path Recommendations: When routing high-speed differential lines, maintain consistent spacing along pads. For high-density communication modules, perform impedance simulation to validate design parameters.

Process Standardization

  • Pad Geometry Design: Half-hole pads should be oval-shaped or extended to the edge to ensure adequate plating coverage (≥65% metal retention post-drilling).
  • Pre-Soldering Preparation: Apply epoxy hole fill or solder mask control in half-hole soldering zones to enhance SMT reliability.
  • Plating and Surface Coating: Use ENIG (Electroless Nickel Immersion Gold) or immersion tin for full-board plating. Employ step plating to ensure uniform metallization in half-hole walls.

Manufacturing Compatibility

  • Process Time and Cost: Many international PCB fabricators require high-precision milling tools for panelized half-hole cutting. Confirm equipment capabilities support continuous half-hole slot cutting dimensions.
  • Thermal Stress Optimization: Integrate thermal relief designs aligned with end-device thermal cycling profiles to prevent soldering failures from thermal cycling.

Testing and After-Sales Support

  • ICT Interface Design: Include test points in the layout to accommodate FCT (Functional Circuit Test) tooling customization.
  • Documentation Clarity: Clearly annotate half-hole positions in assembly diagrams to prevent reflow misalignment.
  • Failure Diagnostics Support: Document common failure modes (e.g., insufficient solder, terminal lifting) with inspection guidelines and troubleshooting steps.
    PCB Castellated Edges Design Consideration

    How to Make A Castellated PCB?

    1. Substrate Preparation and Lamination

    • Material Selection: Choose FR-4, high-frequency materials, or flexible substrates, coated with electrolytic copper foil (thickness ≥35μm) to ensure conductivity and mechanical strength.
    • Lamination Process: Bond inner core boards, prepregs (PP), and outer copper foils through high temperature and pressure to form a multi-layer structure, controlling interlayer alignment accuracy to ±0.05mm.

    2. Drilling and Plating

    • Full Hole Drilling: Drill complete through-holes (diameter 0.6-1.2mm) at the board edge using tungsten carbide drills or laser drilling (for HDI boards with hole diameters ≤0.1mm).
    • Hole Metallization: Apply chemical copper deposition (0.3-1μm) to cover the hole walls, followed by electroplating to thicken the copper layer to 25-30μm, ensuring electrical connectivity. Use pulse plating or electroless copper plating to avoid copper layer tearing.

    3. Outer Layer Circuit Formation

    • Photolithography and Etching: Apply film, exposure, and development to form etch-resistant patterns, then etch away unprotected copper to retain circuits and copper in the half-hole area. After stripping the film, perform secondary copper/tin plating for protection.
    • Solder Mask and Silkscreen: Spray liquid photoimageable solder mask, UV cure to form the solder mask layer (with precise openings), and silkscreen identification information to prevent solder bridging.

    4. Half-Hole Shaping

    • Cutting Process: Use precision milling cutters (double-V shaped tool path) or laser cutting along the hole center to retain the half-hole structure. Optimize spindle speed and feed rate with slot cutters to reduce burrs and copper lifting.
    • Deburring: After cutting, use alkaline etching or red tape to bond unit boards and remove residual copper filaments, ensuring smooth, defect-free half-hole edges.

    5. Surface Finish

    • Enhanced Solderability: Apply ENIG, OSP, or immersion tin to improve pad solderability and oxidation resistance. For high-frequency applications, use immersion silver or gold plating.
    • Solder Mask Bridge Design: Set a solder mask bridge of ≥0.1mm between half-holes to prevent solder short circuits. Use NSMD design in non-solder mask areas to enhance solder joint reliability.

    6. Profiling and Testing

    • Outline Cutting: Use CNC milling or V-cut to cut the final outline, ensuring dimensional accuracy.
    • Electrical Testing: Perform flying probe or ICT testing for continuity and insulation resistance. Use AOI/AXI to inspect pad alignment and inner layer defects.
    • Reliability Verification: Conduct high-temperature aging, thermal shock, and vibration tests to verify mechanical strength and electrical performance (e.g., IPC Class 3 standards).

    7. Quality Control and DFM Optimization

    • Precision Control: Monitor dimensional deviations in drilling, lamination, and cutting to avoid inconsistent half-hole sizes due to swelling or shrinkage.
    • DFM Guidelines: Follow manufacturer guidelines (e.g., minimum hole diameter 0.5mm, edge gap 0.5mm) and optimize designs to reduce manufacturing difficulty and costs.
    How to Make A Castellated PCB?

    Why Choose EBest Circuit (Best Technology) as Castellated PCB Manufacturer?

    Reasons why choose us as castellated PCB manufacturer:

    • Free DFM Analysis: Professional team provides free Design for Manufacturability (DFM) analysis to identify potential manufacturing defects at the design stage, reducing trial production costs and time by over 30% for a one-time successful design.
    • End-to-End One-Stop Service: Comprehensive services from design optimization and rapid prototyping to mass production delivery. Single point of contact handles all processes, boosting efficiency by 40% and ensuring smooth project progression.
    • 1 Piece MOQ: Supports small-batch and single-piece orders to meet prototype validation and small-scale trial production needs, lowering initial investment risks and enabling rapid design iteration to capture market opportunities.
    • 19 Years of Technical Expertise: Deep experience in PCB manufacturing with over 5,000 complex projects completed. Specializes in high-density interconnect (HDI) and miniaturized designs to ensure flawless execution of innovative concepts.
    • Globally Recognized Quality Certifications: Holds ISO 13485 (medical), AS9100D (aerospace), and IATF 16949 (automotive) certifications, meeting stringent requirements for high-reliability applications in medical, aerospace, and automotive sectors.
    • Custom Material Solutions: Offers tailored material options including ultra-thin substrates, high-frequency high-speed materials, and high-temperature specialty materials to match diverse application scenarios from consumer electronics to industrial controls.
    • Engineer-Centric Support: Bilingual technical team provides 24/7 support, covering design specification interpretation and production issue diagnosis to reduce communication costs and ensure project success.
    • Eco-Friendly Manufacturing Commitment: Utilizes lead-free processes and wastewater recycling systems compliant with RoHS/REACH standards, facilitating seamless international environmental certification and enhancing global market access.

    Welcome to contact us if you have any request for castellated PCB: sales@bestpcbs.com.

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