AlN Cleaning Guide: Check Water and pH Compatibility

November 7th, 2026

Aluminum nitride, or AlN, should not be treated as a ceramic that tolerates every water-based cleaner. Cleaning compatibility depends on the material grade, exposed surface, chemistry, temperature, contact time, and the other materials in the assembly. Obtain supplier guidance and qualify the complete process before using a new cleaner on production substrates.

This guide is a planning tool, not a chemical recipe. It follows a hypothetical power-electronics substrate with residue near copper metallization. The objective is to remove the residue without damaging the ceramic, metal, joints, or later bonding surface. A clean-looking part is not automatically an undamaged or electrically acceptable part.

Illustrative dry ceramic substrate coupons with copper metallized islands — AI-generated physical-product illustration, not a photograph of a tested or certified AlN product.

1. Why AlN Cleaning Needs a Compatibility Check

AlN is used where heat transfer and electrical insulation must coexist. Its value does not make its exposed surface chemically inert. Research on aqueous treatment and guidance from cleaning manufacturers both show why the specific exposure matters.

For example, Alconox’s AlN cleaning guidance warns about alkaline attack and prolonged or repeated exposure. Its product-specific recommendations should not be copied into a universal recipe for a metallized or assembled substrate. Compatibility must cover every exposed material, not only the ceramic named in the article.

2. Identify Which Form of AlN You Have

Powder, dense sintered ceramic, a coated substrate, and a single-crystal research sample are different test subjects. Their surface area, structure, additives, and exposed interfaces can differ. A cleaning method described for one form is not automatically suitable for another.

Start with the purchased substrate’s exact designation and supplier documentation. Identify whether the cleaning step reaches bare ceramic, a protective layer, metallization, or all three. If the grade or coating is unknown, that is a missing input to resolve—not a reason to use a familiar cleaner and hope for the best.

3. Detailed Cleaning Parameters to Record

A compatibility study needs a reproducible exposure description. Record the following parameters before comparing trial results. This table specifies what to document; it does not prescribe safe numerical limits.

Parameter	What to record	Why it matters
Material and surface	Grade, supplier, finish, coating, metallization	Defines the actual test subject
Chemistry	Product, concentration, water quality, measured pH	Names the real exposure, not a broad cleaner category
Temperature	Controlled range and measurement point	Prevents an unrecorded process change
Contact	Time, immersion or spray, agitation	Distinguishes different exposure conditions
Rinse and dry	Method, sequence, limits, delay	Extends the process beyond the wash bath
Repeat exposure	Normal and permitted rework cycles	Checks cumulative processing

Write the actual pH measurement conditions rather than relying only on a bottle label. A controlled process should also identify how solution condition and concentration are maintained under the approved procedure.

4. What Water-Exposure Research Does and Does Not Prove

A 2026 study of AlN under prolonged pool boiling observed surface degradation under its specific heated-water conditions. That supports taking water compatibility seriously even for bulk material. It does not establish a universal room-temperature cleaning lifetime.

Do not convert a severe laboratory exposure into a rule that a short rinse always fails—or that it is always safe. Use research to identify mechanisms and questions, then test the proposed substrate and process. Temperature, duration, surface preparation, and the exact material form must remain attached to any reported result.

5. Why pH Alone Cannot Select a Cleaner

pH describes one aspect of an aqueous solution. It does not fully describe its ingredients, residue-removal ability, interaction with metals, or effect on coatings. Two products with similar pH can still have different compatibility and rinsing behavior.

Likewise, “neutral” is not a qualification certificate, and “acidic” does not mean safe for every assembly. Compare candidate processes using the complete exposure record in the parameter table. If a proposed cleaner changes both chemistry and operating temperature, evaluate that combined change rather than approving it from a pH comparison alone.

6. AlN vs Alumina: Do Not Transfer a Cleaning Approval

Alumina and aluminum nitride are different materials. Their shared use as insulating substrates does not establish shared chemical behavior. A process approved for an alumina part therefore needs review before being applied to an AlN part.

Comparison	What may look similar	What still needs verification
AlN vs alumina	Ceramic substrate function	Grade-specific chemical and surface response
Bare vs metallized AlN	Underlying ceramic designation	Metal, interfaces, coatings and exposed edges
Powder vs dense AlN	Chemical name	Material form and relevance of the study
Unassembled vs assembled substrate	Same starting substrate	Joints, components, adhesives and trapped solution

For the hypothetical power substrate, changing only the ceramic while keeping the old wash program is a process change to evaluate, not a clerical substitution.

7. Check Metallization and Assembly Materials Too

A cleaner reaches whatever is exposed. Copper, surface finishes, bonding layers, solder joints, adhesives, markings, and component packages may impose limits different from those of the ceramic. A process that leaves bare AlN unchanged can still be unsuitable for an assembled product.

List all affected materials and obtain the relevant compatibility guidance. Pay particular attention to crevices and interfaces that may retain solution. Do not infer that a clean coupon proves compatibility with a complete power module. Test articles should represent the production surfaces and geometry that create the risk.

8. Start with the Residue You Need to Remove

Identify the contamination before choosing a process. Handling contamination, machining debris, flux residue, and an unknown white surface deposit are not interchangeable problems. Their removal and verification may require different approaches.

In our example, first establish whether the deposit is assembly residue or a change to the substrate itself. Repeatedly increasing wash strength can make the evidence harder to interpret. Preserve an uncleaned reference and document the starting condition so that the trial can distinguish removal of contamination from creation of new surface damage.

Illustrative dry ceramic coupon and sealed laboratory sample bottle for compatibility planning — AI-generated laboratory illustration. No cleaning chemistry, procedure, or successful test result is implied.

9. Design a Small, Controlled Compatibility Trial

Use representative material and retain untreated controls. Define the wash, rinse, drying, and permitted repeat-cycle conditions. Decide in advance what measurements will demonstrate residue removal and what observations would indicate damage. Include appropriate handling and chemical safety controls under the organization’s approved procedures.

A staged trial makes discrepancies easier to interpret. If several variables change at once, a failure may not identify its cause. Do not assign production limits from one attractive photograph. Record the sample identity, process settings, inspection method, and acceptance criteria so the result is reviewable and repeatable.

10. Inspect More Than Cosmetic Appearance

Visual inspection can reveal discoloration, deposits, or obvious damage, but it cannot answer every surface or electrical question. Select verification methods according to the product’s risk: surface condition, dimensions, cleanliness, adhesion or bonding behavior, and relevant electrical performance may need separate checks.

Do not impose an arbitrary universal threshold for roughness, residue, or insulation. Use the product’s specifications and a suitable measurement method. Where qualification requires specialist analysis, involve the responsible laboratory or materials engineer before interpreting a change as harmless or assigning a chemical cause.

11. Common Failures in Cleaning Qualification

Common reasoning failures include testing the wrong ceramic grade, omitting a rinse from the trial, ignoring repeat cleaning, and checking only an unassembled coupon. Another is declaring that no visible change means no relevant change. Each can leave the actual production exposure untested.

Also avoid presenting a solvent as universally safe because it is not water-based. Solvents can introduce their own material compatibility, residue, fire, and handling constraints. This guide deliberately does not prescribe acids, alkalis, solvent mixtures, or temperatures for unknown assemblies. Supplier guidance and controlled qualification must come first.

12. Release the Process with Clear Boundaries

An approved cleaning instruction should identify the permitted material and assembly state, controlled chemistry, operating window, rinse and dry sequence, repeat-cycle allowance, inspection criteria, and change triggers. Define who reviews deviations and what to do when the starting contamination is outside the qualified scope.

For the power-substrate example, the useful result is a bounded process supported by representative evidence—not a general claim that AlN can or cannot be washed. For broader material background, see the AlN PCB substrate guide; use this cleaning checklist for the separate compatibility decision.

FAQ

Can I rinse AlN with deionized water?

Do not assume that deionization alone establishes compatibility. Confirm the substrate supplier’s guidance and assess the proposed temperature, duration, exposed materials, and drying sequence. A brief approved rinse and prolonged immersion are different exposures. Qualification should cover the actual process, including repeated cycles where those can occur in production or rework.

Is a neutral-pH cleaner automatically safe?

No. pH does not identify every ingredient or interaction with ceramic, metallization, coatings, and assembly materials. A neutral label is one input, not a complete compatibility assessment. Obtain product-specific guidance and verify cleaning effectiveness and absence of unacceptable damage under the intended conditions before releasing the process for production use.

Can an alumina cleaning instruction be reused?

It can be considered as a candidate process, but it should not be treated as already approved for AlN. Confirm the new material and all exposed surfaces, review supplier guidance, and qualify the proposed process. Similar appearance or a shared role as an insulating substrate does not establish equivalent chemical behavior.

Does a white deposit prove hydrolysis?

No. Appearance alone cannot reliably identify a deposit’s composition or origin. Contamination, dried cleaner, process residue, and material changes may need different investigation methods. Preserve a reference sample, document the exposure history, and use appropriate analysis before declaring a mechanism or trying a more aggressive wash that could alter the evidence.

Can ultrasonic cleaning be added to an approved wash?

Not without reviewing the change. Ultrasonic exposure changes the process and may interact with part geometry, surfaces, joints, and components. Ask the relevant suppliers for limitations and evaluate representative samples under controlled conditions. An approved chemistry does not automatically approve every agitation method, exposure duration, or assembled configuration using that chemistry.

Does an AlN powder study apply to my dense substrate?

It may highlight a mechanism worth investigating, but it does not automatically establish a rate or safe exposure window for a dense substrate. Material form, surface area, grade, and test conditions matter. Use the study within its stated scope and obtain evidence relevant to the actual purchased substrate and proposed cleaning process.

Is alcohol a universal alternative to water?

No. A nonaqueous route still needs compatibility, cleanliness, drying, and safety review. It may not remove the target contamination and may affect other materials or leave unacceptable residue. Follow the chemical supplier’s safety information and the assembly’s approved process requirements rather than selecting a solvent solely because it avoids an aqueous label.

When should a qualified cleaning process be reviewed again?

Review it when the substrate grade, supplier, coating, metallization, assembly materials, cleaner, concentration, equipment, exposure window, or rework allowance changes. New residue types or unexplained inspection failures are also reasons to reassess. Keep change control linked to the qualification’s boundaries so that an old approval is not silently extended to a different process.

Sources and Technical Support

The linked cleaning-manufacturer guidance and original surface-reaction studies support the compatibility cautions; they do not establish a universal production recipe. Send the substrate identification, assembly materials, residue description, and proposed process to sales@bestpcbs.com for a Best Technology technical enquiry. Specific review and manufacturing scope require confirmation.

CPW vs GCPW: Why Bottom Copper Changes the Model

November 7th, 2026

Conventional coplanar waveguide (CPW) has a signal conductor between two same-layer ground conductors without a metal plane beneath the substrate. Grounded CPW (GCPW), also called conductor-backed CPW, adds a lower ground plane electrically connected to the side grounds. The same top-layer width and gap do not make these two structures electrically equivalent.

In a teaching example, a designer calculates a 50-ohm antenna feed, then adds bottom copper and stitching vias to the board. The trace has not changed on screen, but the cross-section has. This guide explains how to select a model that represents the board, rather than assuming that any calculator labeled “coplanar” will do.

Illustrative RF coupon with a straight signal strip between two same-layer copper grounds — AI-generated physical illustration. Top copper alone cannot establish whether a structure is CPW or GCPW; inspect the layers beneath it.

Identify the Cross-Section Before Naming the Line

Start with where copper exists above, beside and below the signal, not the label attached to a CAD rule. Sonnet’s CPW documentation distinguishes conventional, grounded and floating structures. In its definitions, lower copper that is not connected to the side grounds is a different case from grounded CPW.

Sketch the actual layer stack through the antenna feed. Mark the nearest plane, side-ground extents, vias and nearby metal enclosure. If two engineers use CPW to mean different cross-sections, a discussion about trace width can appear precise while comparing different physical objects. Keep the drawing with the model so the topology is unambiguous.

CPW vs GCPW vs Microstrip: Compare the Copper

The distinction is the ground geometry surrounding the signal. A simple comparison helps select the initial model, but it does not replace reviewing discontinuities along the entire route.

Structure	Side grounds	Lower metal
Conventional CPW	Part of the line	No plane beneath substrate
GCPW / CBCPW	Tied to lower ground	Connected ground plane
Floating CPW	Not tied to lower metal	Separate lower conductor
Microstrip	Not part of the ideal model	Reference plane below

A real layout may transition between these structures. A coplanar connector launch can lead into a microstrip route. The transition itself then needs review. Calling the whole route “50 ohms” does not show that its launch, straight section and destination share the same local geometry.

Detailed Parameters Needed for a Useful Model

Record conductor dimensions and the complete electromagnetic environment before solving for width. The entries below are required input descriptions, not a universal 50-ohm recipe. Use the fabricator’s proposed stackup and relevant material data for an actual design.

Input	Unit or form	What to identify
Signal width w	mm or µm	Finished top and base widths
Side gap s	mm or µm	Left and right clearances
Plane distance h	mm or µm	Actual dielectric separation
Copper thickness t	µm	Finished conductor section
Material model	Dk, loss; frequency	Relevant grade and method
Ground geometry	Widths, vias, plane shape	Finite physical conductors
Coatings and metal	Thickness; material; distance	Mask, finish and enclosure
Analysis scope	Hz; Ω; reference planes	Band, target and ports

Use one length unit consistently. In a multilayer board, h usually means the distance to the relevant reference plane, not the total board thickness. Confusing those two values can invalidate a calculation before any discussion of fine tolerance begins.

Why Adding a Lower Plane Changes the Answer

The lower conductor changes how electric and magnetic fields occupy the surrounding space. It is not an electrically invisible support sheet. For a low-loss transmission-line approximation, characteristic impedance is related to per-length inductance and capacitance by Z₀ ≈ √(L′/C′). Changing surrounding conductors can change those quantities.

This explains the teaching example without inventing a numerical shift: a width found for a no-backplane CPW must be checked again when a connected backplane is added. The size of the change depends on the complete geometry. Do not claim a fixed percentage correction or declare the added plane harmless merely because it is on the other side of the board.

Select the Calculator by Its Assumptions

Choose a model whose illustrated stackup and boundary conditions match the proposed board. A page title saying “CPW calculator” is not enough to establish whether it includes finite substrate thickness, a lower plane or finite-width side grounds.

Check the equations or documentation, required inputs and cross-section drawing. If the board has a connected plane below the line, a conventional no-backplane result is not automatically applicable. If a tool omits a relevant feature, use it only as a clearly limited starting estimate. Record what it leaves out and move to an appropriate field model before treating its output as a release dimension.

A Worked Input Check for an Antenna Feed

Compare assumptions before comparing impedance outputs. Suppose the teaching board has w = 0.30 mm, s = 0.15 mm, h = 0.20 mm and t = 0.035 mm. These are arbitrary example dimensions, not a calculated 50-ohm structure or a Best Technology capability statement.

For Model A, remove all lower metal to represent conventional CPW. For Model B, add the intended connected lower plane to represent GCPW. Hold the specified material and top geometry constant so the comparison isolates that topology change. Then solve each case and check convergence. No impedance result is supplied here because material properties, side-ground width and frequency-dependent modeling choices have not been specified.

The useful output is a discrepancy identified before fabrication: “our calculator assumed no bottom plane, but our released board has one.” Resolve that mismatch rather than adjusting width until two unrelated tools happen to display the same number.

A DC Ground Connection Is Not the Whole RF Structure

A shared ground net name does not describe the positions and geometry of its physical connections. Review how the side grounds connect to the lower plane along the route and at the ports.

Sonnet warns that electrically long grounded structures without suitable connecting vias can show unexpected resonances. That is a reason to analyze the intended via arrangement, not a universal instruction to place the largest possible number of vias. For connector-specific detail, use the separate RF via-fence launch guide. Check the transition and reference path rather than adopting a pitch from an unrelated board.

Illustrative RF coupons showing coplanar top copper and a separate continuous copper back face — AI-generated physical illustration of top and back faces. Connectivity and impedance must come from design records and verification, not this image.

Finite Ground Width and Nearby Metal Need Attention

Real ground conductors have edges, and nearby metal can become part of the electromagnetic environment. An ideal model with infinitely wide grounds is not automatically representative of a narrow coupon inside an enclosure.

For the teaching feed, compare the side-ground width in the model with the actual copper remaining after component clearances and board cutouts. If the line is near a metal lid, include that boundary where it matters. A useful convergence check changes the modeled boundary distance or ground width and asks whether the answer has stabilized sufficiently for the design’s accuracy needs. Do not confuse solver precision with proof that omitted metal has no effect.

Use the Finished Etched Geometry, Not Only the Artwork

Etching can produce a conductor cross-section different from the ideal rectangle entered into a simple calculator. The gap that interacts with the fields is part of that finished geometry, not just an artwork dimension.

The Rogers–Sonnet comparison study discusses trapezoidal conductor shape and surface roughness in measured and modeled coplanar structures. Use that as evidence to request realistic geometry, not as a source of universal loss values. Ask which finished width and gap ranges the proposed process can support, then analyze those actual bounds rather than silently assuming the drawing’s nominal values are exact.

Keep Coatings and Finish Consistent With the Model

A model of bare copper and air does not fully describe a coated surface line. State whether mask covers the signal, the gaps and the nearby grounds, and what material model is being used.

Do not change a mask opening merely to make a calculator easier to use. Review electrical behavior, environmental protection and assembly needs together. The separate GCPW solder-mask guide focuses on that coating question. Here the first decision is still topology: a correct coating input does not rescue a calculation built on the wrong lower-plane assumption.

Verify the Straight Line and the Launch Separately

A uniform cross-section calculation does not verify a connector pad, bend, component discontinuity or the complete antenna match. Those features can require a different level of model and measurement.

Define the intended electrical acceptance before ordering: impedance, reflection, insertion loss and operating band are related but different requirements. If using a coupon, make its construction representative and state the measurement reference planes. When simulated and measured results differ, investigate the launch, fixture, material and finished geometry before assigning every discrepancy to trace width. The microstrip guide provides an adjacent reference for routes that do not intentionally use nearby side grounds.

Release a Cross-Section, Not Just a 50-Ohm Label

The release package must let the designer, fabricator and test team describe the same structure. A target number without topology and construction inputs leaves room for incompatible interpretations.

Identify conventional CPW, connected GCPW or another explicit structure.
Record the layer pair, lower-plane continuity and side-ground geometry.
Confirm finished width, gap, copper and dielectric ranges.
Keep mask, finish and material assumptions tied to the revision.
Review vias, launch and discontinuities over the required band.
Define coupon scope, measurement conditions and acceptance criteria.

For the teaching antenna feed, the correct next step is to rerun the appropriate model after adding bottom copper, not to preserve an old width because its original calculation said 50 ohms. Approve the resulting construction only after the required validation.

FAQ

Are CPWG, GCPW and CBCPW always different structures?

They are often used for the connected, conductor-backed coplanar arrangement, but naming conventions vary. Ask for a cross-section rather than resolving the design from an acronym alone. Verify the lower conductor, its connection to the side grounds and the model’s boundary assumptions before deciding that two calculators describe the same line.

Does copying a reference-board trace width guarantee 50 ohms?

No. The copied width must be considered with its original gap, dielectric separation, material, copper, coatings and ground geometry. A reference board may also use a different launch or stackup revision. Use its dimensions as design context, then validate the actual proposed construction instead of treating the width as a standalone component value.

Can a very short feed ignore the distinction?

Electrical length and the allowed error influence how much a discontinuity matters, but short physical length is not proof of equivalence. Review the operating band, surrounding structures and system requirements. A model mismatch should be understood and bounded even when the final engineering judgment accepts its effect as sufficiently small.

Does passing the CAD design-rule check verify the impedance?

Only the checks actually configured and implemented are verified. A clearance or connectivity rule can pass while the impedance model uses the wrong plane distance or topology. Inspect the rule’s purpose and the exported geometry. Treat electromagnetic validation and fabrication checks as complementary tasks, not interchangeable evidence for one another.

Is adding top ground beside microstrip always an improvement?

No automatic improvement follows from more copper. Nearby side conductors can change the line being built, especially when their gap is relevant to the fields. Review the revised structure and its connections. Keep a microstrip assumption only when the chosen analysis supports neglecting those conductors for the required accuracy and operating conditions.

Can a hatched lower plane be modeled as a solid plane?

Do not make that substitution without justification. The actual lower conductor pattern and its scale relative to the electrical behavior must be considered. A solver or calculation that assumes a continuous sheet may not represent the patterned structure. Use an appropriate model and validation plan rather than quietly changing the physical geometry in the analysis.

Why might two GCPW tools disagree with identical input numbers?

They may not use identical definitions or assumptions. Check whether gap and width refer to finished dimensions, how conductor thickness is represented, whether side grounds are finite, and which dielectric and coating models are used. Align those details before attributing the difference to numerical accuracy or selecting the more convenient answer.

Does good return loss prove low transmission loss?

No. A path can have limited reflection while still dissipating or radiating energy. Evaluate the separate performance requirements and use measurements appropriate to each. State the operating band, fixture and reference planes so a return-loss result is not presented as evidence that insertion loss or the complete antenna system also meets its target.

Discuss the RF Stackup

For a Best Technology manufacturing inquiry, send the proposed cross-section, layer stack, target impedance, operating band and coupon requirements to sales@bestpcbs.com. Confirm the construction and acceptance scope before treating nominal calculator dimensions as released production data.

100-Ohm PCB Pair Guide: Are Two 50-Ohm Traces Enough?

November 7th, 2026

Two traces that are each 50 Ω when modeled in isolation are not automatically a 100 Ω differential pair once placed close together. Mutual coupling changes the pair’s modal behavior. For a symmetric pair under differential excitation, the differential impedance is twice its odd-mode impedance—not necessarily twice the impedance of an isolated trace.

Two parallel exposed copper traces on a green PCB test structure — A pair of parallel copper traces. AI-generated illustration; geometry in a photograph does not establish impedance.

Follow a hypothetical interface whose specified differential target is 100 Ω. The designer initially selects a width that gives 50 Ω for one isolated trace, then places two such traces close together. We will distinguish what that calculation proves from what the actual pair still needs. The example does not assign a target or tolerance to every interface.

What Does a 100-Ohm Differential Target Describe?

It describes the transmission-line impedance associated with differential voltage and the corresponding loop current in the pair. It is not the DC resistance measured between the traces.

Each conductor has a voltage relative to the reference, while the receiver also sees the voltage difference between conductors. Those are different voltage definitions, so they produce different impedance definitions. AMD UG583’s transceiver guidance explicitly relates 50 Ω odd mode to 100 Ω differential. Its application-specific recommendation should not be copied as a requirement for an unrelated interface.

Which Impedance Parameters Must Stay Separate?

Name the excitation and current convention beside the impedance value. Otherwise, “50 ohms per trace” can refer to different calculations.

Quantity	Meaning for a symmetric pair	Example or relation
Isolated Z0	One trace without the coupled neighbor	Assume 50 Ω
Odd-mode Zodd	Per-line impedance under opposite excitation	Assume 45 Ω after coupling
Differential Zdiff	Between the pair under differential excitation	2 × Zodd = 90 Ω
Even-mode Zeven	Per-line impedance under equal excitation	Assume 60 Ω in that example
Common-mode Zcommon	Common voltage divided by total pair current	Zeven / 2 = 30 Ω

The numerical entries are illustrative model outputs, not results computed from the pictured board or a real stackup. The relationships follow the stated symmetric-line conventions.

Isolated-Trace vs Coupled-Pair Design

The isolated-line calculation omits the neighbor’s contribution, while the coupled-pair calculation includes it. Use the latter when checking the specified differential structure.

Design choice	Useful check	What not to assume
Choose width from isolated Z0	Single-line baseline	Pair remains twice that value at every gap
Set width and gap together	Actual coupled cross-section	One width works on every stackup
Increase separation	Recalculate both modes	“Three widths” proves a target
Change layer or dielectric	Re-solve the new structure	Same artwork keeps the same impedance
Check a transition	Use an appropriate transition model	Uniform-line results cover pads and vias

This distinction concerns model scope. It is not a demand that every differential signal be routed with the tightest possible coupling.

Derive the Factor of Two from Voltage and Current

The factor of two comes from the differential voltage definition for a balanced odd-mode excitation. It does not require adding two physical resistors to the PCB.

Suppose one trace is at +0.5 V and the other at −0.5 V, with equal and opposite currents of magnitude 10 mA. Each trace’s odd-mode ratio is 0.5 V / 0.010 A = 50 Ω. The differential voltage is 1.0 V, and its loop current magnitude is still 10 mA, so Zdiff = 1.0 V / 0.010 A = 100 Ω. These assumed traveling-wave quantities explain the definition; they are not a DC measurement prescription.

A Worked Example Shows How Two Isolated 50-Ohm Traces Miss

If coupling changes the per-line odd-mode impedance, doubling the old isolated result no longer describes the pair. Recalculate the actual cross-section.

Assume an isolated-trace model gives Z0 = 50 Ω, but a separate coupled-pair model for the intended gap gives Zodd = 45 Ω. The pair is then 90 Ω differential, not 100 Ω. The 10 Ω difference is 10% of the hypothetical target; whether it is acceptable depends on the actual specification. The 45 Ω value is an assumed teaching output, not a prediction from width alone. No fixed correction factor converts every isolated 50 Ω design into the right pair.

Why Does the Gap Change Odd-Mode Impedance?

The adjacent conductor changes the electromagnetic fields and coupling between the lines. Opposite-polarity excitation is therefore not equivalent to removing the neighbor.

Polar Instruments AP157 distinguishes the odd, even and isolated modes. For ordinary symmetric edge-coupled structures, narrowing the gap generally lowers odd-mode impedance relative to the isolated case; widening the gap reduces the coupling. Check the actual cross-section rather than treating that trend as a numerical design formula. Nearby copper, dielectric boundaries and reference-plane geometry also belong in the model.

Solve Width and Stackup Together

Width, copper thickness, dielectric geometry and material properties influence the solution along with the gap. A gap adjustment should be assessed within the complete manufacturing construction.

For the hypothetical interface, ask the fabricator for the proposed cured stackup and achievable trace geometry, then solve the candidate pair using appropriate material data. Do not keep a width selected for a different layer height merely because its old calculation said 50 Ω. Record whether the dimensions describe artwork, finished top width or another geometry convention. A clearly named input is more reproducible than a screenshot of an unlabeled calculator result.

Can a Weakly Coupled Pair Still Be 100 Ohms?

Yes. In the weak-coupling limit, two equal lines approach independent behavior, and a pair of isolated 50 Ω lines can approach 100 Ω differential. Tight coupling is not the definition of differential signaling.

That limiting case does not remove the need for suitable references, balanced routing and interface-specific constraints. Evaluate whether the available routing geometry preserves the intended behavior along the path. A long uncoupled region, connector breakout and closely coupled region can each have different cross-sections. Avoid turning a general “route together” recommendation into an arbitrary universal gap requirement.

Even Mode Is Not Another Name for Differential Mode

Even-mode excitation drives the two lines with equal polarity, while odd mode uses opposite polarity. The same physical pair therefore has different modal quantities.

Using the assumed table value Zeven = 60 Ω, a common voltage of 0.6 V produces 10 mA on each line in the idealized mode. Total current is 20 mA, so the pair’s common-mode impedance under this convention is 30 Ω. This explains why Zeven and Zcommon differ by a factor of two. It does not prove that a real link has no common-mode noise or that an arbitrary termination is appropriate.

Bare PCB differential test coupon with two separate coaxial launches — Illustrative two-port coupon connection. AI-generated, not a validated launch geometry or impedance test record.

Recognize Where the Uniform-Line Model Stops

A two-dimensional cross-section describes a uniform line, not every pad, via, connector or reference transition on the route. Those discontinuities need an appropriate additional assessment.

Inspect where the teaching pair changes gap, enters a connector or moves layers. Do not infer that a correct straight-section result proves the entire channel meets its requirements. For relevant via geometry, the Best Technology differential-antipad guide addresses a separate design decision. Keep transition effects and line-target errors distinguishable so a local mismatch does not lead to unnecessary changes across the whole board.

Write the Fabrication Requirement in the Correct Mode

State the differential target, tolerance, layer, referenced structure and test expectations explicitly. Do not ask for “50 ohms on each trace” if the actual acceptance requirement is a differential pair.

A coupon and measurement plan should represent the intended construction within their agreed scope. Confirm the instrument’s mode and reporting convention before comparing values. A single-ended observation of one conductor is not automatically a differential result. The Best Technology differential-pair design guide covers the wider routing and manufacturing handoff; this article clarifies the impedance definitions within it.

Close the Design with a Reproducible Verification Basis

Retain the input construction, mode definitions, calculated result and agreed manufacturing evidence together. The objective is a controlled, verifiable pair—not a favorable number obtained by changing unnamed assumptions.

For the hypothetical link, verify that the final model satisfies its specified 100 Ω target and any other required channel criteria, then reconcile the production evidence with that basis. To discuss Best Technology fabrication requirements, send the stackup, routed layer, differential target and tolerance to sales@bestpcbs.com. Testing and modeling scope must be confirmed for the project rather than inferred from this educational example.

FAQ

Will a 100-ohm resistor make a 90-ohm pair become 100 ohms?

No. A termination sets the load seen at its location; it does not change the characteristic impedance of the distributed line geometry. Select termination according to the actual interface and analyze mismatches appropriately. Do not use a resistor substitution as evidence that an incorrectly modeled PCB cross-section now meets its fabrication target.

Why does my multimeter not read 100 ohms between the traces?

Characteristic impedance describes traveling-wave behavior, not simply DC resistance between two bare conductors. A multimeter can be affected by termination components or circuit paths, and an unconnected bare pair may appear open. Use an appropriate impedance measurement method and clearly identify the connected circuit before interpreting the reading.

Are all high-speed differential interfaces specified at 100 ohms?

No. Required impedance and tolerances depend on the interface and implementation guidance. The 100 Ω target in this article is a hypothetical teaching requirement, not a universal recommendation. Check the actual device and interface documentation before selecting geometry, termination or a fabrication acceptance limit for the project.

Can I double a single-ended TDR result to obtain differential impedance?

Not without establishing what the measurement represents. Exciting one line while treating its neighbor differently is not automatically a pure odd-mode measurement. Confirm the setup, terminations, calibration and conversion method. Doubling is valid for the defined odd-mode impedance, not every impedance trace displayed by a single-ended instrument.

Does correct differential impedance guarantee equal propagation delay?

No. Impedance and timing are separate design quantities. Geometry and materials influence both, but meeting one numerical target does not establish acceptable skew or total delay. Review the interface’s timing requirements and the actual path, including transitions, rather than treating an impedance pass as a complete channel qualification.

Does a symmetric drawing guarantee no mode conversion?

No. The manufactured structure, surrounding references, connectors and excitation can introduce imbalance even when two traces look symmetric in CAD. Maintain appropriate symmetry and analyze relevant discontinuities. A uniform-line impedance calculation is useful evidence for its own scope, but it is not proof that the assembled channel has zero conversion.

Can a solder-mask change affect the pair without changing its artwork?

It can alter the surrounding dielectric environment, particularly for outer-layer structures, so include the intended mask construction where it matters to the model. The size of any effect depends on the actual geometry and materials. Do not assume a fixed percentage change or approve a substitution without the relevant review.

Is impedance the only reason to keep a pair’s spacing consistent?

No. Consistent geometry also helps make coupling, propagation and the modeled structure predictable. Nevertheless, short constrained breakouts may require different spacing and a separate assessment. Apply the interface requirements and suitable analysis rather than forcing every segment into one gap at the expense of reference continuity or manufacturability.

PCB Antenna Detuning Guide: Why the Case Changes Range

November 7th, 2026

PCB antenna enclosure detuning occurs when the assembled product changes the antenna’s electrical environment enough to shift its response. A plastic wall, battery, screw, cable or changed ground geometry can matter. However, reduced range after closing a case is not proof of detuning: radiation loss, a changed pattern, receiver noise and an uncontrolled test can produce similar symptoms.

Wireless sensor PCB with edge antenna beside an open plastic enclosure — A wireless board and its housing. AI-generated illustration, not a validated antenna layout or tested product.

Use a hypothetical battery-powered 2.4 GHz sensor as the running example. It communicates on the bench but becomes unreliable inside its enclosure. The goal is to identify what changed, test that hypothesis and verify the complete assembly. It is not to copy a universal keepout distance or guess a new matching capacitor.

What Changes When the Case Closes?

Closing the case changes the materials and objects surrounding the radiator, and sometimes the positions of the board, battery and cables. The antenna is part of that assembled electromagnetic system, not an isolated copper shape.

Antenova’s detuning discussion describes how nearby conductive parts and enclosure materials can affect the antenna environment. For the sensor, begin with a mechanical comparison: what moves toward the antenna when the lid is secured? A newly routed battery lead is a different suspect from the lid material itself.

Which Antenna Parameters Help Diagnose the Change?

Use measurements that distinguish port matching from radiated performance. A single range number is useful as a symptom, but it does not identify the mechanism.

Parameter	Meaning	Diagnostic boundary
Frequency response	How the antenna behaves across the band	A single point can miss a shifted response
S11	Reflection at a defined reference plane	Does not directly measure radiated efficiency
Return loss	Positive loss measure from reflection magnitude	Check sign convention against S11 in dB
Radiation efficiency	Radiated fraction of accepted power	Needs suitable radiated measurement
Radiation pattern	Direction-dependent response	One orientation is not the entire pattern
Packet error result	Link outcome under defined conditions	Also depends on radio and interference

These are diagnostic quantities, not promised sensor specifications. Record the operating band, setup and device configuration alongside each result.

Detuning vs Absorption vs Receiver Noise

Separate these candidate mechanisms before changing the antenna. More than one can exist in the same product.

Candidate	Possible observation	Useful next check
Impedance detuning	Port response shifts after assembly	Compare calibrated sweeps in both states
Loss or shielding	Weak radiated link despite acceptable match	Assess radiated performance and nearby materials
Pattern change	Some orientations worsen more than others	Repeat controlled orientation comparisons
Receiver noise	Performance changes with internal activity	Compare power and operating modes
Test variation	Results move without a design change	Control position, traffic and surroundings

The table is a diagnostic starting point, not a rule that one observation proves one cause. Preserve the baseline while investigating each hypothesis.

Respect the Radiator Keepout and Its Ground Reference

Follow the actual antenna’s reference layout, including its ground geometry and layer-specific keepout. “Ground is useful” and “no ground beneath this radiator” can both be correct for different parts of a design.

For common monopole-style board antennas, the ground region participates in antenna behavior while the designated radiator area requires its specified clearance. Infineon AN91445, revision H discusses enclosure and ground-plane effects for its illustrated antenna systems. Do not transfer one drawing’s distances to every antenna type. In the sensor review, inspect every copper layer and the assembled mechanical model.

Why Can a Plastic Lid Affect a PCB Antenna?

Nonmetallic does not mean electromagnetically invisible. Material close to the radiator can change its loading, even when it does not fully shield the signal.

The relevant question is not simply “Is the case plastic?” Record the wall position, material and nearby internal features. AN91445 explains how nearby plastic can lower resonance in its discussed antenna context. The direction and magnitude in the sensor still need measurement; do not assign a fixed frequency shift from the material name. Compare the actual production-intent lid rather than assuming a loosely placed prototype cover represents the same geometry.

Check Batteries, Screws, Cables and Coatings

Review all nearby objects as possible contributors, not just the outer wall. Conductive hardware and wiring can change coupling, current paths or radiation behavior.

For the sensor, photograph the cable route and battery position before and after closure. Check whether a mounting screw, shield or metallic coating approaches the antenna region. If one object can be moved in an engineering sample, compare controlled configurations without changing everything else. Do not conclude that a removed screw is unnecessary for the final product; mechanical retention, safety and production requirements still apply. The diagnostic result should inform a reviewed redesign.

Small enclosed wireless sensor beside its open reference unit on a test bench — Open and enclosed unit configurations. AI-generated illustration, not evidence of a measured range or matching result.

Build a Controlled Open-and-Closed Comparison

Compare the same radio configuration and physical setup while changing only the assembly state you intend to investigate. Otherwise, a changed result can have several explanations.

Keep firmware, channel, transmit power, battery state, peer device, separation and orientation fixed for an initial comparison. Use a repeatable nonconductive fixture where appropriate and record the environment. Compare more than one unit before deciding the effect is systematic. The hypothetical sensor’s “works on my desk” observation is a useful starting point, but it is not a reproducible acceptance test. Define what constitutes an improvement before trying corrective changes.

Use a VNA with a Defined Reference Plane

A vector network analyzer can compare antenna input response, but the connection and cable become part of the measurement problem. Establish where the calibrated result applies and how the radio is isolated for that measurement.

Use an RF specialist’s suitable fixture and calibration method rather than attaching a cable anywhere convenient. Record its route and keep it consistent between assembly states. A cable that cannot pass through a fully closed lid without changing the geometry may limit the comparison. Treat an observed shift as evidence within that setup, and confirm it with a representative assembled configuration before choosing corrective components.

What Does a Better S11 Actually Prove?

It proves a change in reflection at the measured port under those conditions, not automatically a better radio link. Matching and radiation are related but different.

For a calculated example, S11 = −10 dB corresponds to a reflected-power fraction of 10%, while −6 dB corresponds to about 25.1%, using 10 raised to S11/10. The remainder is accepted at the port; it is not necessarily all radiated. These are mathematical examples, not measured sensor data or universal acceptance limits. A well-matched lossy structure can still perform poorly over the air, so do not stop the investigation at an attractive dip.

Correct the Mechanism Before Guessing Matching Parts

Choose the correction from the evidence: geometry, clearance, component placement, material or matching may need attention. A matching network is not a guaranteed cure for shielding or loss.

TI AN043, revision D is a specific 2.4 GHz PCB antenna reference, not a universal shape that remains unchanged in every host board. Likewise, TE’s embedded-antenna design note discusses ground-plane and tuning limitations. For the sensor, select candidate changes, document them and measure again instead of repeatedly swapping components without a baseline.

Verify the Link in the Final Product Configuration

After correcting the suspected cause, verify radio behavior with the intended enclosure, battery, cable routes and operating modes. The best open-board result is not the delivery configuration.

Use the project’s agreed link criteria and controlled tests across relevant channels, orientations and use conditions. Include internal high-activity modes if they might affect the receiver. Retain the measurement setup and configuration identifiers so another unit can be compared. Check any required radio-compliance implications with the responsible specialist; neither this article nor an improved laboratory response establishes regulatory approval. A range claim requires its own documented conditions.

Freeze the RF-Relevant Mechanical and PCB Details

Release the validated combination, not just the antenna trace artwork. Capture the board outline, stackup, copper keepout, matching population and surrounding mechanical configuration.

The Best Technology PCB antenna manufacturing guide explains why manufacturing handoff matters. Flag a later case, battery or ground change for RF review rather than treating it as purely cosmetic. For a Best Technology fabrication discussion, send the controlled board files and antenna constraints to sales@bestpcbs.com. Any tuning, radiated testing or assembly service must be confirmed within the actual project scope.

FAQ

Can I copy a working antenna into a smaller PCB?

Not with an assumption of unchanged performance. A different board outline and ground region can alter the antenna system even if the radiator artwork is identical. Use the reference design’s complete constraints, then evaluate the actual host board and enclosure. Treat copying as a design starting point rather than validation.

Is there one safe distance between an antenna and every enclosure?

No universal distance covers every antenna, frequency, material and geometry. Use the actual antenna documentation and verify the assembled product. A distance from a particular module guide belongs to that guide’s conditions; it is not a general clearance rule for every trace antenna, chip antenna or external antenna.

Does a metal case always require the same antenna solution?

No. The appropriate solution depends on the complete RF and mechanical design. An external antenna or a deliberately designed RF-transparent region may be considered, but both need engineering evaluation. Do not assume that a small opening, plastic insert or stronger transmitter automatically restores the required coverage and compliance.

Why does touching the unit change its range?

A person’s hand changes the antenna’s nearby environment and may alter both loading and propagation. That makes handling an uncontrolled variable in a bench comparison. Use repeatable fixtures for diagnostic measurements, then include representative handling in the product’s intended-use validation rather than judging performance from one hand-held position.

Can increasing transmit power solve the problem?

It does not identify or correct the underlying mechanism and may not improve the reverse link. It can also affect battery consumption, thermal behavior and regulatory obligations. First determine whether the issue is matching, radiation, interference or the test setup. Use permitted radio settings and validate the complete link.

Why can one channel work while another fails?

The assembled antenna response and the interference environment can vary across frequency. A shifted or narrow response can affect channels differently, but that is not the only explanation. Compare channel-dependent port and link evidence under controlled conditions before attributing the result solely to the antenna or changing its geometry.

Does a pre-certified radio module remove the need for enclosure checks?

No. Follow the module’s integration instructions and the conditions of its approvals, and assess the actual host product. Antenna placement and nearby materials can still affect performance. Consult the responsible compliance specialist about allowed changes; a module’s prior approval is not an unrestricted approval of every enclosure and antenna configuration.

Should the production line repeat the complete antenna tuning exercise?

Not necessarily. Development characterization and production screening serve different purposes. Define a practical production test and controls based on the validated design and project requirements. Keep component population, board geometry and mechanical assembly controlled, and specify what result or change triggers investigation rather than improvising a full retuning procedure for every unit.

PCB Trace Resistance Guide: Check the Hot Voltage Drop

November 7th, 2026

A copper PCB trace becomes more resistive as its conductor temperature rises. If the load current stays constant, its voltage drop and resistive power loss rise as well. A room-temperature resistance calculation is therefore only the starting point for a hot power-distribution path.

Broad exposed copper power trace on a bare green PCB. AI-generated illustration, not a measurement or production record.

Use this guide to estimate the change and decide what to measure. The worked example describes a uniform trace at a specified temperature; it does not calculate its final operating temperature or establish a current rating.

What does PCB trace resistance describe?

Trace resistance is the opposition a copper path presents to direct current. For a uniform rectangular section, R = rho × L/(w × t), where rho is electrical resistivity, L is length, w is width and t is copper thickness.

Longer paths have more resistance. Wider or thicker paths have less resistance when the other inputs stay equal. This is a DC geometric model: it leaves out connector contacts, vias, local neck-downs and high-frequency effects unless they are separately included. That boundary matters before comparing a calculated trace with a measured complete power route.

Which electrical and geometry inputs are required?

Record conductor dimensions and temperature, not just nominal copper weight. Use consistent units throughout the calculation.

Input	Unit	Basis used in the teaching example
Length L	m	0.100
Width w	m	0.002
Thickness t	m	0.000035
Resistivity at 20°C	Ω·m	1.68 × 10^-8
Temperature coefficient	1/°C	0.00393 at a 20°C reference
Conductor temperature	°C	20 or 80
Constant load current	A	5

The material constants are the approximate copper values used in TI’s FPD-Link ADAS Power-Over-Coax Design Guidelines, section 3.3. The dimensions and operating points are hypothetical. Actual finished copper geometry and material properties can differ; none of these entries is a manufacturing guarantee or a safe-current recommendation.

Calculate the cold resistance first

The hypothetical 100 mm long, 2 mm wide, 35 µm thick uniform trace has a 20°C resistance of 0.024 Ω, or 24 mΩ. Its cross-sectional area is 0.002 × 0.000035 = 0.00000007 m², and 1.68 × 10^-8 × 0.100 divided by that area gives the result.

At a constant 5 A, V = I × R gives 0.120 V across this trace. P = I² × R gives 0.600 W of electrical loss. Those are calculated values for this section alone. They exclude its return path and all other series elements.

Apply the temperature correction to the copper

Use the approximate linear relationship R(T) = R20 × [1 + alpha × (T − 20°C)]. For 80°C copper and alpha = 0.00393/°C, the multiplier is 1.2358, so 24 mΩ becomes about 29.66 mΩ.

The reference temperature belongs to the coefficient and resistance data; do not silently substitute a resistance measured at a different temperature. TI presents this correction for the PCB portion of its example system. For materials, alloys or temperatures outside the intended approximation, obtain the appropriate data rather than treating one copper coefficient as universal.

Compare cold and hot voltage drop at the same current

At a fixed 5 A, the hypothetical 80°C trace drops about 0.148 V and dissipates about 0.741 W. Both are approximately 23.6% higher than their 20°C values because the current is held constant.

Condition or change	Trace resistance	Drop at 5 A
Original geometry, 20°C	24.00 mΩ	0.120 V
Original geometry, 80°C	29.66 mΩ	0.148 V
Twice the width, 80°C	14.83 mΩ	0.074 V
Half the length, 80°C	14.83 mΩ	0.074 V
Twice the thickness, 80°C	14.83 mΩ	0.074 V

The last three rows hold conductor temperature at 80°C to isolate geometry. They do not predict the new equilibrium temperature or imply equal fabrication cost, routing space or thermal behavior.

Why conductor temperature is not ambient temperature

The copper can be warmer than the air surrounding the board because it dissipates energy and exchanges heat with components, nearby copper and cooling structures. Entering ambient temperature into the correction is valid only if it represents the conductor closely enough for the intended estimate.

For a board inside a closed enclosure, the air itself can differ from the laboratory room. Measure or model the relevant conductor condition under the intended load. A datasheet’s maximum material temperature, a chosen temperature rise and an observed copper temperature are three different inputs, not interchangeable labels.

Separate current and sense connections on a PCB test coupon. AI-generated illustration, not a measurement or production record.

Include the return path and other series elements

A load sees the voltage available between its supply and return terminals. That depends on the whole current loop, not only the positive trace. Add the relevant return conductor, vias, connectors, protection devices and joints with their own appropriate resistance models.

If the example had an identical return trace at the same 80°C and current, the two copper traces together would drop about 0.297 V. That remains an illustrative copper-only subtotal. Do not apply the copper temperature coefficient automatically to semiconductor switches or contacts, whose behavior requires different data.

Handle neck-downs and changing cross sections

Divide a varying route into sections and add their resistances. A wide pour connected through a narrow segment does not have the resistance of the wide pour over its full length.

Use each segment’s relevant width, thickness and temperature. If current spreads through a large irregular plane, a simple one-dimensional rectangle may be inadequate. The BestPCBs trace neck-down guide discusses the associated local heating risk. Do not average a narrow bottleneck away by substituting the route’s widest width.

Separate electrical loss from the thermal solution

Calculating I²R tells you heat generation at the stated current and resistance. It does not tell you the final temperature without the thermal path. Temperature changes resistance, and resistance changes heating, so the electrical and thermal calculations are coupled.

A useful design process starts with an estimated temperature, evaluates loss and then checks the resulting temperature using an appropriate thermal model or measurement. Iterate as necessary. Do not use the example’s assumed 80°C as evidence that this trace will settle there, or that its surroundings can safely tolerate it.

Check how the load responds to falling voltage

The constant-current example does not describe every load. A regulated downstream converter serving approximately constant power can draw more input current as its input voltage falls, while a simple resistive load behaves differently.

Use the real load characteristic and input-voltage limits. Recalculate the operating point when route loss changes the load current materially. Startup, load steps and undervoltage behavior may also govern the design. The right question is not only “what is the trace resistance?” but “what current and voltage does this complete system reach under the required conditions?”

Verify small resistance without measuring the test leads

Use an appropriate low-resistance measurement method and defined endpoints. A four-wire arrangement separates current injection from voltage sensing, reducing the influence of lead resistance on the sensed voltage. It does not remove errors caused by incorrect probe locations or an unintended parallel path.

Measure an isolated route or account for the rest of the circuit. Record current, polarity, settling and temperature; test current itself can warm the coupon. Follow instrument limits and safe test procedures. A continuity beep is not a quantitative milliohm measurement or evidence of adequate voltage at the operating load.

Release the power route against a voltage budget

Allocate the allowed distribution drop from source to load, then verify the copper and other series elements under the relevant operating conditions. Check both the cold model and hot evidence, including the return path.

Preserve the finished copper requirement, geometry, current waveform, measurement endpoints and thermal conditions. Choose wider, shorter or thicker routing on that basis, not from copper weight alone. For a Best Technology review, send those inputs and the required load voltage to sales@bestpcbs.com. Manufacturing review does not replace complete-system thermal and electrical validation.

FAQ

Is trace resistance the same as trace impedance?

No. DC resistance describes resistive opposition in the stated path. Transmission-line impedance also depends on geometry, reference conductors and frequency-dependent behavior. A 50-ohm RF trace is not normally a 50-ohm DC resistor. Use the electrical model that matches the measurement and signal or power problem being investigated.

Can I convert a resistance measured at 25°C using the 20°C formula?

Do not treat the 25°C reading as R20. First relate it to the stated reference using the same applicable approximation, or use a coefficient and reference formulation appropriate to that measurement. Record the actual conductor temperature so the comparison does not hide a systematic reference-temperature error.

Does doubling copper weight guarantee half the measured route resistance?

Not for the entire route. The simple model halves resistance only when the actual trace thickness doubles and other relevant inputs remain equal. Vias, contacts, neck-downs, temperature and finished copper variation can prevent the complete path from following that ratio. Compare the same endpoints and operating conditions.

Can I use voltage drop to infer conductor temperature?

Only with a sufficiently characterized path, current measurement and resistance-versus-temperature relationship. Contacts, parallel current paths and nonuniform temperature can distort the inference. For a complex route, resistance represents a combined response rather than one guaranteed local hot-spot temperature. Validate the method before using it for protection decisions.

Why does my multimeter disagree with the geometric calculation?

Check units, actual copper thickness, etched shape, probe endpoints, temperature and parallel connections first. Lead and contact resistance can dominate a small trace value in a two-wire measurement. A discrepancy is not automatic evidence of bad copper; isolate the measured object before assigning a manufacturing cause.

Does low DC voltage drop prove that a power path handles a fast load step?

No. Fast behavior also depends on inductance, capacitance, regulator response and distribution geometry. A route can have low DC resistance yet show a transient voltage excursion. Check the time-domain requirement separately and do not use this uniform DC trace calculation as a power-integrity qualification.

Can I use a standard copper coefficient for a copper-alloy busbar?

Not without verifying the alloy’s properties. Its resistivity and temperature behavior can differ from the pure-copper approximation used here, and joints add their own behavior. Use the material supplier’s relevant data and the complete connection geometry rather than transferring one coefficient based only on the word copper.

Is adding solder a predictable substitute for a wider copper route?

Not by itself. Solder geometry and material properties differ from the finished copper trace, and the resulting cross section can be uneven. A controlled design change requires characterized electrical and manufacturing evidence. Do not assume an informal solder layer delivers a specified resistance, temperature rise or repeatable current capability.

Microvia Aspect Ratio Guide: Which Depth and Diameter?

November 7th, 2026

Microvia aspect ratio compares a blind microvia’s depth with a defined hole diameter. The calculation is simple, but the dimension definitions are often not. A tapered opening, an entry diameter and a target-side diameter can give different ratios, while a notation such as 1:0.8 may place diameter first rather than depth first.

Fine HDI pad array with small via openings. AI-generated illustration, not a measurement or production record.

This guide shows how to read the convention, calculate a comparable ratio and review a proposed stackup change. It does not present one ratio as a universal manufacturing or reliability guarantee.

What does a microvia aspect ratio describe?

Here, aspect ratio A means depth h divided by reference diameter d: A = h/d. A depth of 60 µm and a diameter of 100 µm give 0.60, often written 0.60:1 when depth is listed first.

The ratio describes a geometry, not every condition needed to fabricate it. The opening shape, bottom condition, material and metallization process still matter. Always state the convention beside the value instead of relying on the word aspect ratio alone.

Which dimensions must be defined?

Use a cross-sectional definition agreed with the fabricator. Nominal CAD dimensions, laser-process dimensions and finished measurements are not automatically identical.

Dimension	Unit	Definition to confirm
Depth h	µm	Start surface to target
Entry diameter	µm	At specified process stage
Target-side diameter	µm	At bottom of tapered opening
Dielectric thickness	µm	Actual laminated construction
Outer copper	µm	Whether included in depth
Ratio A	None	Named depth and diameter

Keep units consistent. Dividing a depth in micrometers by a diameter in millimeters without conversion creates a thousandfold error, even if the resulting number is formatted neatly in a report.

Read the order of the ratio before comparing it

Some published guides write diameter first. For example, Würth Elektronik’s HDI design guide expresses its microvia example as diameter/depth = 1:0.8. Expressed as depth divided by diameter, that relationship is 0.8. Check the supplier’s current design rules separately before applying the published example to an order.

This is a supplier-specific published example, not Best Technology’s capability statement or a universal limit. It shows why comparing “0.8:1” and “1:0.8” without reading the axis order can reverse the intended relationship.

A worked example with a tapered hole

Assume a hypothetical depth of 60 µm, an entry diameter of 100 µm and a target-side diameter of 70 µm. The entry-based ratio is 60/100 = 0.60. The bottom-based ratio is 60/70, about 0.86.

Both calculations describe the same hypothetical hole using different reference diameters. You cannot call one supplier more capable by comparing its entry-based number with another supplier’s bottom-based number. First establish the common definition.

Why total board thickness is the wrong depth

A blind microvia connects a limited layer span, so its depth is not normally the complete multilayer board thickness. A thicker central core does not necessarily change an outer microvia’s depth, while a thicker outer buildup dielectric can change it directly.

Identify the start and target layers on the stackup. Read the relevant local construction, including the agreed copper reference, rather than dividing total board thickness by the small via diameter as if it were a through hole.

Compare three geometry changes

If a proposed geometry is outside the agreed process envelope, compare changes in the complete layout and stackup.

Option	Geometric effect	Other checks
Increase diameter	Reduces h/d	Pad size and escape routing
Reduce buildup depth	Reduces h/d	Impedance and dielectric requirements
Change layer connection	Changes required span	Routing and lamination sequence
Use another via structure	Different fabrication problem	Space, cost and qualification

A smaller numerical ratio is not automatically a better overall PCB design. The revised construction still has to satisfy electrical, mechanical and manufacturing requirements.

Mounted PCB section specimen on a metallurgical microscope stage. AI-generated illustration, not a measurement or production record.

Why a stackup change can invalidate the old check

A material substitution or thickness change can alter the actual distance to the target layer. Suppose the same hypothetical 100 µm reference diameter remains, but the agreed depth grows from 60 to 80 µm. The ratio changes from 0.60 to 0.80.

Do not assume the CAD via definition automatically records that construction change. Recalculate against the proposed laminated stackup and ask the supplier to confirm the referenced depth rather than reusing an approval from a thinner buildup.

Keep target-pad capture separate from aspect ratio

Aspect ratio does not prove that the laser opening lands on enough target copper. Registration, target-pad dimensions and material movement affect capture. A via can satisfy a ratio requirement and still have inadequate landing geometry.

The BestPCBs microvia target-pad guide covers that separate check. Review both the depth/diameter definition and the target capture evidence when evaluating a dense escape pattern.

Why cleaning and plating still matter

A geometry within the agreed envelope does not establish the condition of the blind bottom or the deposited copper. Residue, interface preparation and plating quality can affect the finished connection. Those conditions need process and inspection evidence, not an arithmetic ratio alone.

An IPC-hosted microvia reliability presentation discusses several interacting failure mechanisms. Treat it as technical background, not a substitute for the applicable current procurement requirements or a universal pass/fail ratio.

Check stacked and staggered structures separately

For multiple buildup levels, evaluate each microvia and the full interconnect structure. A stack is not qualified simply because every individual hole has an acceptable nominal h/d. Interfaces between levels and the fabrication sequence introduce additional review needs.

Do not describe a tall stack as one ordinary microvia unless the construction and calculation explicitly define it that way. Keep the individual layer spans and the intended reliability evidence visible in the stackup review.

Request measurements that match the drawing

A cross section can show the measured depth, taper, bottom and copper condition at the section location. It does not prove every via across every panel has the same geometry. State the sampling and acceptance requirements along with the dimension definitions.

Ask the report to identify the board revision, stackup, specimen location and measurement stage. If the section is offset from the intended hole center, its apparent opening may not represent the diameter you meant to evaluate.

Release the construction, not just the ratio

Approve the actual layer span, material construction, dimension references, via and pad geometry, and required inspection or reliability evidence together. Keep a change trigger for revised dielectric thickness, laser geometry or interconnect structure.

For a Best Technology HDI review, send the stackup, start and target layers, intended microvia dimensions and product requirements to sales@bestpcbs.com. Ask which diameter and depth the fabricator uses before interpreting a quoted aspect-ratio capability.

FAQ

Is a microvia ratio of 1:0.8 the same as 0.8:1?

It can describe the same geometry if the first notation lists diameter before depth and the second lists depth before diameter. It can also mean something different if the conventions are not stated. Read the definition and convert both to the same h/d expression before comparing.

Should I use the entry diameter or the bottom diameter?

Use the diameter defined by the applicable design rule or supplier agreement. A tapered hole has more than one meaningful diameter, and each produces a different ratio. Do not switch definitions to make a borderline geometry appear compliant; clarify the reference and keep the measured evidence consistent.

Does a ratio below one guarantee reliable plating?

No. Geometry is one input to a fabrication process. Bottom preparation, metallization, copper deposition, interfaces and the required qualification evidence also matter. Check the supplier’s actual process envelope and the applicable inspection requirements rather than treating a numerical threshold as a complete reliability test.

Can I use the full board thickness in the microvia calculation?

Not for an ordinary blind microvia spanning only part of the stack. Use the depth between the stated start and target references. Total board thickness is relevant to other structures, such as a through hole, but it can badly misrepresent a shallow outer buildup connection.

Does increasing the hole diameter solve every aspect-ratio problem?

No. It may reduce h/d, but it also uses more pad and routing area and can affect the escape design. Check the target capture, spacing and finished interconnect requirements. Sometimes a thinner buildup or a different layer connection is a better option, subject to the full stackup review.

Can a material change affect the ratio without changing my drill file?

Yes. A change in laminated buildup thickness can change the distance to the target while the nominal opening data remain the same. Recalculate using the proposed actual construction and confirm whether copper is included in the stated depth. Keep the revised approval with the material change.

Does a microsection establish every hole’s exact diameter?

No. It measures a particular section through a particular specimen, and the cutting plane and preparation affect what is visible. Use the agreed sampling plan and interpret the apparent dimensions against the measurement method. A report should identify the location and construction instead of presenting one image as universal proof.

Can I compare different fabricators using only their aspect-ratio numbers?

Not safely. First align the ratio convention, reference diameter, depth definition, material and via structure. Then compare the relevant fabrication and verification scope. Two similar headline numbers can describe different holes or different evidence, so a dimensioned cross section and stackup are more useful comparison inputs.

PCB Copper Skin Depth Guide: Does Thicker Copper Help?

November 7th, 2026

Copper skin depth describes how far alternating current penetrates into a conductor at a particular frequency. At high frequency, current density falls with depth instead of remaining uniform through the copper. This means thicker PCB copper can reduce DC resistance without producing the same proportional reduction in RF conductor loss.

Copper foil beside the edge of a copper-clad laminate. AI-generated illustration, not a measurement or production record.

Use this guide when comparing copper thickness or foil for an RF line. It explains the calculation, gives a frequency table and separates skin depth from the other effects that determine the loss of the finished transmission line.

What does one skin depth mean?

In the ideal good-conductor model, current-density amplitude falls to 1/e, about 37% of its surface value, at one skin depth. Current does not stop at a sharp boundary. The field and current distribution continue to decay into the metal.

Skin depth is therefore not a layer of copper that can be peeled away or a fixed property independent of frequency. It is a calculated length for stated material properties and excitation conditions.

Which inputs define the copper calculation?

The model uses frequency, conductivity and permeability. For the following teaching calculations, assume smooth bulk copper with conductivity 5.8 × 10^7 S/m, relative permeability approximately 1, and μ0 approximately 4π × 10^-7 H/m. These are illustrative near-room-temperature model inputs, not guaranteed foil specifications.

Here f is frequency in hertz (Hz), σ is conductivity in siemens per meter (S/m), and μ is permeability in henries per meter (H/m). The calculated skin depth δ and conductor thickness t must use the same length unit when comparing t/δ.

Use δ = √[1 ÷ (π f μ σ)]. Conductivity can change with temperature and material condition. If the application depends on a supplier’s actual foil properties, use those values and retain the model assumptions.

Calculate a frequency table before choosing thickness

For the stated smooth-copper assumptions, the calculated values are approximately:

Frequency	Skin depth	Interpretation
1 MHz	66.1 µm	Can exceed thin foil thickness
10 MHz	20.9 µm	Comparable with some PCB foil
100 MHz	6.61 µm	Smaller than 35 µm copper
1 GHz	2.09 µm	Surface effects become prominent
10 GHz	0.661 µm	Surface texture deserves review

These are calculated penetration depths, not insertion-loss predictions. Rogers’ copper-foil technical article provides a corresponding high-frequency skin-depth table and discusses foil surface effects.

Why frequency changes the result by a square-root law

With conductivity and permeability held constant, skin depth is proportional to 1/√f. Raising frequency by a factor of 100 reduces the calculated depth by a factor of 10. Moving from 100 MHz to 10 GHz therefore changes 6.61 µm to approximately 0.661 µm in the example.

Do not extrapolate a linear relationship such as “ten times the frequency means one tenth the depth.” Check the units before calculating: 1 GHz is 10^9 Hz, not 10^6 Hz.

Compare DC resistance with high-frequency conductor loss

DC and high-frequency current distribution lead to different thickness trade-offs.

Question	DC or low frequency	High-frequency line
Used cross-section	More nearly the full thickness	Nonuniform distribution
Extra thickness	Can reduce resistance strongly	Benefit depends on t/δ and geometry
Surface texture	Not a skin-depth issue	Can affect conductor loss
Verification	Resistance and thermal checks	Line model and loss measurement

The comparison does not mean copper thickness becomes irrelevant at RF. It means the DC cross-sectional-area argument cannot be used alone to predict RF improvement.

A worked comparison of 35 and 70 µm copper

At 1 GHz, the example skin depth is 2.09 µm. Copper thicknesses of 35 and 70 µm are roughly 17 and 33 skin depths. Both are well beyond a single penetration depth, so doubling thickness does not justify claiming that conductor loss will be halved.

A real line also changes when thicker copper alters its cross-section. If width and dielectric spacing stay unchanged, impedance may change. Compare the complete line geometry rather than treating copper weight as an isolated loss-control knob.

Microstrip PCB coupon with coaxial connectors at both ends. AI-generated illustration, not a measurement or production record.

Why the current is not spread equally over every surface

The signal and return geometry determines the electromagnetic fields around a PCB trace. Current can concentrate on the face toward a reference plane and near edges; the exact distribution depends on the structure. Do not assume equal current on the top, bottom and sidewalls.

Keysight’s Momentum documentation distinguishes conductor-loss models with different surface-current assumptions. Choose a model appropriate to the line rather than dividing the total copper perimeter into equal current shares by hand.

What copper roughness changes

When texture dimensions become relevant to the field penetration scale, a smooth-conductor model may underpredict loss. But a roughness statistic is not itself a universal loss multiplier. The foil face, treatment, measurement and roughness model must correspond to the real copper-to-dielectric interface.

Do not compare an Rz number directly with an Rq-based model input or a fitted surface parameter without checking the definitions. Keep the foil specification with the stackup and use representative line data when the loss budget is tight.

Why surface finish needs its own model

The exposed copper may carry another conductive layer or finish, while buried copper has a different interface. A plated layer can have different conductivity and magnetic behavior from bulk copper. The effect depends on layer thickness, frequency and current distribution.

Do not apply the bulk-copper table unchanged to every finish stack or assume that all the RF current flows only in a named outermost layer. Use a multilayer conductor model or applicable measured evidence for the actual construction.

Do not confuse skin depth with total transmission loss

A line loses and reflects energy through more than conductor resistance. Dielectric loss, launches, vias, mismatch and radiation can also contribute. A better conductor surface will not necessarily remove a loss dominated by another mechanism.

Keep the observation ports and fixtures consistent when comparing coupons. The BestPCBs fixture-de-embedding guide concerns separating fixture effects from the line under test; it is a measurement step, not a skin-depth correction.

When thicker copper still makes sense

Thicker copper can still be useful for DC current, heat spreading or another mechanical and electrical requirement even when the RF conductor-loss benefit is limited. Balance those needs against the trace geometry, fabrication process and impedance target.

For a mixed power-and-RF board, evaluate the power path and RF path as separate design tasks. A copper change that helps the supply path can require a revised RF line width and a new stackup review.

Verify the proposed foil and geometry together

Compare candidate lines with the same electrical target, operating band and reference conditions. Include actual copper thickness, foil surface, finish and dielectric construction. If the candidates use different dimensions to maintain impedance, preserve those dimensions in the comparison.

For a Best Technology RF stackup review, send the frequency band, impedance and loss targets, proposed foil and finished copper geometry to sales@bestpcbs.com. Use the skin-depth calculation to ask better questions, then verify the complete line rather than treating the table as a production result.

FAQ

Does current flow only within one skin depth?

No. In the ideal model, current-density amplitude decays continuously into the conductor and is about 37% of its surface value at one skin depth. There is no hard cutoff. A one-depth illustration can explain concentration near the surface but should not be mistaken for a boundary containing all current.

Can I use the same table for copper at a different temperature?

Only as an approximation if the change is acceptable for the task. Conductivity changes with temperature, which changes the calculated depth and conductor resistance. Use material properties appropriate to the operating condition when a quantitative loss or thermal decision depends on the result.

Does doubling copper thickness halve RF loss?

Not generally. That simple scaling resembles a DC area argument, whereas high-frequency current is distributed nonuniformly. When thickness is already many skin depths, additional thickness does not produce the same proportional gain. Include the changed trace geometry and impedance when comparing the complete line.

Is skin depth the same as dielectric penetration?

No. Skin depth here describes the decay of current and fields into a conductive metal. Transmission-line fields also occupy the surrounding dielectric, but that is a different part of the model. Keep conductor properties separate from dielectric constant and loss tangent when calculating the PCB line.

Can I apply the copper formula to a nickel-containing finish?

Not by keeping the copper properties unchanged. A finish introduces another material and layer thickness, and its electrical or magnetic behavior may differ. Use the properties and structure of the actual stack in a suitable model rather than labeling the whole conductive path as bulk copper.

Does a thinner skin depth always mean a board will fail?

No. It identifies a frequency-dependent conductor behavior, not a pass/fail limit. The design passes or fails against the applicable impedance, loss, thermal and link requirements. A line can operate successfully with a small skin depth if its complete construction meets those requirements.

Can a DC resistance measurement validate my RF loss model?

It can verify a low-frequency resistance input, but it does not validate the surface-current distribution, roughness correction or high-frequency fixture. Use a suitable line measurement over the relevant band as well. Keep DC resistance evidence and RF insertion-loss evidence as separate checks.

Should I choose the smoothest available foil for every PCB?

Not automatically. Surface profile, adhesion treatment, dielectric compatibility, cost and the actual loss budget all matter. A less demanding line may not need a premium foil. Select the construction against the design requirements and confirm the supplier’s exact foil and process rather than relying on a generic smoothness label.

Glass Weave Skew Guide: Why Equal PCB Lengths Can Differ

November 7th, 2026

Glass weave skew is a difference in arrival time between signals caused by the local glass-and-resin structure of a PCB laminate. Two differential traces can have equal geometric length yet different propagation delay if they sample different dielectric environments. Length matching is therefore necessary for many interfaces but does not, by itself, prove matched electrical delay.

Woven glass reinforcement beside a PCB trace coupon. AI-generated illustration, not a measurement or production record.

This guide explains the mechanism, compares mitigation choices and shows how to include weave effects in a timing review. It focuses on differential-pair delay, not on changing a laminate merely because its published bulk dielectric constant is lower.

What creates glass weave skew?

A woven reinforcement has glass-rich yarn regions and more resin-rich spaces between them. A trace following one region for a long distance can experience a different effective dielectric environment from its partner. Effective permittivity is the combined field-dependent property seen by the transmission line, not simply the bulk value of one ingredient.

The effect depends on the material construction and how the traces align with it. A controlled-impedance stackup describes the nominal line, but small local differences can remain important when the available timing margin is narrow.

What parameters belong in the timing review?

Start with delay and margin at a defined reference plane. Geometric dimensions are inputs; arrival-time difference is the quantity the receiver ultimately sees.

Input	Unit	Purpose
Pair delay difference	ps	Compare with allowed budget
Coupled route length	mm	Identify long exposed regions
Copper length mismatch	mm	Separate geometry contribution
Glass construction	Style and treatment	Identify actual reinforcement
Route to weave angle	Degrees	Assess repeated alignment
Material variant	Full construction	Avoid generic FR-4 assumptions

Do not borrow a skew limit from an unrelated interface. Use the applicable device and link requirements, then allocate margin among the PCB, package, connector and other parts of the path.

Equal length vs equal electrical delay

Equal length removes one source of mismatch but not all of them. In a simplified uniform transmission line, delay per unit length scales approximately with the square root of effective permittivity. A different local effective value can therefore change travel time along two equally long routes.

That approximation is a teaching model. It does not predict a woven laminate’s exact local behavior, because real fields span several materials and the construction is not uniform along the path. Use it to understand why a ruler is not a complete timing instrument.

A worked example of the remaining margin

Suppose a hypothetical link allocates 8 ps to PCB pair mismatch. A simulation or representative measurement already attributes 3 ps to the routed geometry. Only 5 ps remains within that allocation for other PCB contributions under the chosen budgeting method.

You cannot conclude that the weave contribution is zero because the layout tool reports equal length. Also, do not add independent estimates without checking whether they describe the same effect twice. This example is budget arithmetic, not a universal interface limit.

Compare routing and material mitigation choices

Choose a method that addresses how both traces sample the reinforcement, then evaluate its effect on the rest of the layout.

Option	Intended benefit	Trade-off to verify
Route at an angle	Cross multiple yarn regions	Extra length and routing space
Rotate panel image	Change trace-to-weave alignment	Panel use and fabrication agreement
Use spread-glass construction	More uniform local structure	Exact material and stackup availability
Qualified weave-aware stackup	Known construction and evidence	Substitution control and cost

No option guarantees zero skew. The useful question is whether the chosen construction and geometry leave sufficient margin in the actual link.

Why route angle must be relative to the weave

An angle relative to the board edge matters only if the reinforcement orientation is known relative to that edge. A pair drawn diagonally can still align poorly with a rotated material. State the intended relationship in the fabrication discussion rather than relying on the appearance of the layout.

Texas Instruments’ high-speed layout guidance discusses routing and image-rotation approaches. Treat those examples as mitigation guidance; confirm the appropriate construction and geometry for your interface.

Differential trace coupon with coax connectors beside woven glass. AI-generated illustration, not a measurement or production record.

What spread glass changes and what it does not

Spread-glass reinforcement distributes yarns more uniformly than an open, concentrated weave pattern. That can reduce local differences sampled by nearby traces. The designation must still identify a real supplied material construction; “spread glass” is not a complete stackup specification.

It does not remove connector asymmetry, via mismatch or an unsuitable return path. Keep each mechanism distinct during review so a material upgrade is not used to avoid correcting an ordinary layout problem.

Why nominal Dk is not a weave-skew specification

A data-sheet dielectric constant summarizes a material under a stated method and condition. It does not directly state how much two adjacent traces will differ over a particular route. Two constructions with similar nominal Dk can still distribute their reinforcement differently.

Ask for the actual glass styles, resin system and construction relevant to the routing layer. If the supplier proposes a substitute, compare that construction and its evidence rather than approving it solely on the nearest bulk Dk number.

Avoid fixing the wrong kind of mismatch

A connector launch, unequal via transitions or different reference conditions can create delay or mode-conversion problems that resemble a pair imbalance. Review those discontinuities before attributing a measured difference entirely to weave.

The BestPCBs SCD21 mode-conversion guide addresses a related measurement result. Mode conversion can be evidence of imbalance, but it does not identify glass weave as the cause on its own.

Use a coupon that represents the real routing

A useful comparison keeps the stackup, routing layer, geometry, length and reference method under control. Include the proposed orientation or construction change. Keep launch and fixture contributions consistent so their difference is not mistaken for a laminate improvement.

Sampling matters because trace placement relative to the weave can vary. A single favorable coupon is not proof that every route or panel position will behave identically. Agree the evaluation plan with the fabricator and signal-integrity team.

Keep the mitigation in the released fabrication package

Record the approved laminate construction and any agreed image rotation or orientation requirement. Make substitution review explicit. Otherwise, a repeat order can preserve the copper artwork but change the reinforcement arrangement behind the original timing evidence.

Separate a requested process from a verified outcome. A drawing note asking for a particular construction is not a measurement report. Retain both the material identity and the relevant coupon or link evidence with the design revision.

Decide whether the link actually needs a change

A weave-aware review is most useful when the route length, signaling requirements and remaining margin make the effect significant. Do not add routing complexity or an expensive material solely because the mechanism exists. Compare the proposed change against the timing budget and practical verification evidence.

For a Best Technology stackup review, send the interface requirements, layer construction, long pair routes and timing evidence to sales@bestpcbs.com. Ask for construction and orientation confirmation before releasing a material-dependent mitigation.

FAQ

Can glass weave matter when a pair is perfectly length matched?

Yes. Matching copper length addresses geometric mismatch, while local dielectric variation can change delay per unit length. The significance depends on the route and available timing margin. Keep both effects in the review and use representative construction evidence rather than assigning a universal skew value.

Is there a single maximum length below which weave never matters?

No universal cutoff applies to every interface and laminate. Sensitivity depends on route geometry, construction, alignment and the allowed delay difference. A short low-demand link may have ample margin, while a stricter design needs a quantified review. Use the actual budget rather than a general length rule.

Does routing at 45 degrees always solve the problem?

No. The relevant angle is relative to the reinforcement, not just the board outline, and the actual construction still matters. An angled route can help both traces sample different regions, but it also changes route length and space. Verify the resulting link rather than assuming a particular angle guarantees success.

Can I compensate weave skew with a fixed length adjustment?

Be cautious if the underlying local variation is not repeatable across builds. A fixed compensation can correct one measured specimen while worsening another. Distinguish deterministic geometry from material variation and confirm the behavior across the agreed sample set before applying a production adjustment.

Does lower Dk automatically mean lower weave skew?

No. Bulk permittivity and local uniformity are different properties. A material with a lower published Dk can still have a construction that creates unequal local environments for two traces. Compare the actual reinforcement and route conditions, and keep the test method attached to any numeric material data.

Can I infer glass weave from an impedance report alone?

Not reliably. An impedance report can show whether the measured line meets its stated target, but it does not isolate the cause of pair delay mismatch. Use suitable delay or mixed-mode measurements and a controlled comparison if the investigation needs to distinguish weave from launches or other asymmetry.

Should every high-speed board use spread glass?

No. Select it when the construction and link margin justify the change, and verify availability and substitution control. Other design factors may dominate the link. A stackup decision should balance electrical evidence, routing practicality and manufacturing repeatability rather than treating one reinforcement label as a blanket requirement.

Can a repeat order change skew without changing the artwork?

It can if the material construction, orientation or other relevant conditions change. Even with a controlled construction, local alignment can vary. Preserve the approved stackup and process agreements, review substitutions, and use an appropriate sampling plan when timing performance depends strongly on reinforcement behavior.

PDN Antiresonance: Why Adding a Capacitor Can Backfire

November 6th, 2026

PDN antiresonance is an impedance peak caused by interacting paths in a power delivery network. Adding a capacitor can lower impedance at one frequency and raise it at another. Compare the complete impedance curve with the rail’s target band before deciding that a new part has improved decoupling.

Ceramic decoupling capacitors grouped near a PCB device. AI-generated illustration, not a measurement or production record.

Why two capacitors can make a peak

Between the self-resonant frequencies of two capacitor branches, one branch can behave mainly inductively while the other behaves mainly capacitively. Their admittances can partly cancel, leaving less total admittance and therefore higher impedance. Losses in the branches and the rest of the network limit the height of the peak.

What parameters should go into the model?

Use a mounted model at the expected operating conditions. A nominal capacitance list is useful for BOM control but cannot predict the locations of peaks by itself.

Input	Include	Why it matters
Effective capacitance	Part value under rail bias and relevant conditions	Shifts branch behavior
ESR	Frequency-dependent loss where available	Affects damping and peak height
ESL	Package plus mounting path when applicable	Moves resonance and changes high-frequency impedance
Common paths	Shared via, plane and regulator connections	Can dominate after adding more capacitors
Observation port	Load location and reference	Changes what the result represents

Self-resonance vs antiresonance

A capacitor branch’s self-resonance often appears as an impedance minimum. An antiresonance of the combined network appears as an impedance maximum. Treat them as different diagnostic clues. Analog Devices’ decoupling guide explains the ESR and ESL effects on the individual capacitor curve.

Compare three ways to address a peak

Start by asking whether the aim is to remove a troublesome interaction, add damping, or reduce the inductance that limits the bypass path.

Change	When to consider it	What to verify
Repeat an effective capacitor value	The existing value has a useful mounted response and enough sites are available	Shared inductance and remaining peaks
Change the value mix	A separate band still needs support	New peaks between branches and at system interfaces
Add controlled damping	A narrow peak remains above target	Loss, rail transients, and regulator stability
Improve mounting	Capacitors are isolated by long connections or shared vias	Impedance at the actual load port

Set the target before touching the BOM

Use the rail’s allowed voltage deviation and relevant load change to form a first-pass impedance target. The ratio is an engineering starting point, not a guarantee across all frequencies or time scales. Define the relevant frequency band and keep regulator behavior and package effects in view.

A worked example: a lower dip does not mean a better rail

Imagine a preliminary target of 50 mΩ in a defined band. A new capacitor reduces an existing minimum from 25 to 15 mΩ but creates a 75 mΩ peak within that band. The change fails that illustrative check even though the minimum improved. Compare the worst relevant excursion, not the deepest dip.

Populated PCB with coaxial connections for impedance measurement. AI-generated illustration, not a measurement or production record.

Why mounting can matter more than the printed value

Current reaches the capacitor through the pads, vias, and return path. Inductance in that loop changes its mounted response. Moving the part or providing a shorter return can help a different band than changing the nominal capacitance. Use a model or test that represents the actual placement.

What a ferrite bead changes

A bead adds frequency-dependent impedance and can form another resonant network with nearby capacitors. Its response also changes with operating conditions. Analog Devices AN-1368 discusses peaking and damping for bead filters. Do not assume a bead automatically improves a rail that already has a narrow peak.

Compare curves at the same observation point

Measure or model at the same location, with the same reference and configuration, before comparing a change. A curve at the regulator output may look different from one at a device load. An uncontrolled change of port, cables, or fixture can mask the effect of the capacitor.

Confirm an apparent peak before revising the design

Check the fixture and noise floor, then compare the response after a deliberate small change such as removing one suspect branch. A predictable movement of the peak is more informative than a single sweep. Preserve the original and revised traces, model, and operating conditions together.

Check the rail in time as well as frequency

A frequency sweep exposes impedance over a range, while a load transient shows how the rail responds to a particular event. The two are complementary. Verify the response under representative loading and keep the regulator’s permitted capacitance and ESR range in the review.

What to share for a PCB design review

Send the stackup, capacitor placements, rail and return layers, and measurement reference to Best Technology at sales@bestpcbs.com. If the rail budget is not yet defined, start with the BestPCBs PDN target impedance guide, then use this article to check whether any peaks exceed it.

FAQ

Is using several capacitor values always a bad idea?

No. A deliberate value mix can help cover different frequency bands. The risk is assuming that individual impedance minima automatically combine into a smooth curve. Compare the mounted network with the target and verify how the regulator, plane paths, and device interact with the selected capacitors.

Can identical capacitors remove every antiresonance?

No. Repeating the same value may reduce a particular interaction, but other peaks can involve the bulk capacitors, regulator connection, plane inductance, or package. Common mounting inductance can also limit the benefit. Check the complete curve at the load rather than inferring the result from the BOM.

Is a higher peak always a problem?

Its impact depends on whether it falls inside the relevant current spectrum and exceeds the applicable target at the observation point. Also consider the shape and width of the peak. A design decision should include the actual rail budget and a representative load transient check.

Why does the measured peak move when I power the board?

The effective capacitance of some ceramic parts can change with applied voltage, and the regulator and load can change the network response. Verify that the measurement setup is appropriate for the energized rail. Document the bias and operating state before comparing powered and unpowered sweeps.

Does adding ESR always fix the problem?

Loss can reduce a high-Q peak, but the location and amount of damping matter. Added resistance can increase impedance elsewhere or affect regulator behavior. Compare the complete response and respect the regulator’s approved operating range, then verify that both the sweep and the load transient improve.

Can I predict the peak from the two datasheet self-resonances?

The self-resonances indicate where branch behavior changes, but they do not specify the peak of the mounted network by themselves. Layout inductance, capacitance under bias, branch losses, and other connections affect the result. Use mounted models and confirm the important features with a measurement.

Is a rail ripple reading enough to validate decoupling?

A ripple reading is useful for the specific operating condition and probe setup, but it does not reveal every impedance peak or load case. Use a suitable frequency-domain check alongside representative time-domain testing. Keep the measurement point and conditions consistent when comparing revisions.

Should I always replace a mixed network with a single value?

No. Treat a single-value layout as one candidate. Compare it with the existing network and a damped alternative across the required band. Verify the total effective capacitance, regulator stability requirements, mounting constraints, and load response before changing the production bill of materials.

Copper Coin PCB Height: Check the Step at the Pad

November 6th, 2026

On an embedded copper coin PCB, a flat coin can still sit too high or too low relative to the surrounding pads. Specify the signed step at the finished assembly surface and the local flatness separately. The correct limit comes from the actual package, solder or interface requirements and the agreed fabrication process.

Copper coin area beside PCB surface pads. AI-generated illustration, not a measurement or production record.

Define the reference surface first

Measure relative to the pads or other datum specified on the finished drawing. A height referenced to solder mask or bare laminate is not equivalent to height referenced to adjacent finished copper. Use the same construction stage for both measurements.

What the drawing and report must contain

Use signed units and identify the exact points measured.

Field	Unit or basis	Reason
Coin surface height	μm relative to specified datum	Distinguishes protrusion and recess
Local flatness	μm over a stated region	Captures variation on the coin itself
Adjacent pad datum	Finished surface and measured locations	Makes the step repeatable
Side and stage	Top or bottom, before or after finish	Prevents incomparable reports
Assembly interface	Soldered pad or mounted thermal interface	Establishes the functional limit

Calculate a signed step

If the surrounding datum is 0.000 mm and the center of the coin is +0.040 mm, the center protrudes by 40 μm. If another location on the coin measures +0.020 mm, the two sampled heights differ by 20 μm. Those points alone do not establish full-surface flatness.

Compare protrusion, recess and local tilt

Each shape can affect a different part of assembly.

Condition	What it means	What to check
Protrusion	Coin rises above the specified reference	Stencil seating, package or heat-sink contact
Recess	Coin is below the reference	Solder or interface gap and contact
Tilt or local variation	Height changes across the coin	Multiple measurement points and contact footprint

Do not confuse coin flatness with global board flatness

A board bow measurement describes another scale and reference. A good global result cannot rule out a local step. Measure the small region that controls solder or thermal contact and record how the board was supported.

Identify which side sets the assembly limit

The component side may be constrained by solder seating while the other side contacts a thermal interface. Specify the two faces separately. A permitted recess on one face does not define acceptable protrusion on the other.

Copper coin PCB beneath an optical inspection instrument. AI-generated illustration, not a measurement or production record.

Check the interface with the actual package

A package thermal pad and surrounding leads or lands may need to seat together. Compare the worst-case local geometry and the approved solder process. A high-conductivity insert cannot compensate for an unsuitable joint or an unverified assembly gap.

Treat surface residue as a separate check

A surface can meet the height requirement yet still have residue or an unsuitable finish. Check cleanliness and finish over the required contact area in addition to geometry. The PCB copper coin design guide illustrates why dimensional and resin-related requirements are listed separately.

Use multiple points for first-article inspection

Agree on center and perimeter readings or a suitable surface map. Record the datum and instrument method. A single center reading can miss tilt or a localized region outside the functional surface requirement.

Compare readings at the same process stage

Pressing, finishing and any approved planarization can change the measured surface. Specify whether acceptance applies to the completed board and retain intermediate data separately for troubleshooting. Do not compare a pre-finish result with a finished-board limit without agreement.

Investigate contact before claiming thermal benefit

If the component or heat sink does not seat as intended, inspect the actual interface rather than changing the copper grade first. See the BestPCBs copper coin PCB guide for the broader thermal-path and construction context.

Send a complete measurement request

Provide the coin location, side, datum, signed limit, sampling points and the interface drawing. For a construction review, contact Best Technology at sales@bestpcbs.com with the stackup and inspection criteria.

FAQ

Does a flush coin need any tolerance?

Yes. Flush describes the nominal relationship, not the allowable range. Specify how far the surface may sit above or below the datum and where to measure it. Agree those limits with fabrication and assembly before using the word flush as an acceptance criterion.

Can the solder mask surface be my datum?

Only if that is the explicitly defined functional reference for the design. A mask surface and a finished copper pad can differ in height. State the material, location and process stage so the inspector does not substitute an easier but different reference.

Can one reading prove that the coin is flat?

No. It establishes the height at one point. To assess flatness or tilt, inspect enough of the functional area using the agreed method. Record the underlying points or map so a reviewer can distinguish a uniform step from a surface that varies across its width.

Is a protruding coin always worse than a recess?

Neither is universally better. The acceptable direction and magnitude depend on the package, surrounding contacts, interface and process. Evaluate the finished board with its actual mating surface and use signed limits rather than assuming any visible step is automatically unacceptable or harmless.

Can I use the same limit on the top and bottom?

Only if both interfaces support it. The component side and the heat-sink side can have different gap, load and seating requirements. Record the reference and signed limit for each face independently, and confirm how both will be inspected on the finished part.

Does good coin height prove a good thermal joint?

No. Height supports fit, but contact area, solder quality or thermal interface condition also matter. Verify the assembled heat path under the relevant test conditions. Keep geometric inspection and thermal performance evidence separate rather than treating one as a replacement for the other.

Is a microsection sufficient to verify the entire surface?

A section gives detailed information at its cut plane, not a full top-surface map. Use it for the question it can answer and combine it with an appropriate surface measurement where needed. Identify the cut and measurement locations in the report for traceability.

Can I approve a visually flat coin without measurements?

Visual inspection can identify gross defects, but it cannot establish a signed micrometer-scale step. Use the agreed measurement basis when the geometry controls fit or performance. If a report lacks the datum or measurement locations, ask for clarification before releasing the lot.

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AlN Cleaning Guide: Check Water and pH Compatibility

1. Why AlN Cleaning Needs a Compatibility Check

2. Identify Which Form of AlN You Have

3. Detailed Cleaning Parameters to Record

4. What Water-Exposure Research Does and Does Not Prove

5. Why pH Alone Cannot Select a Cleaner

6. AlN vs Alumina: Do Not Transfer a Cleaning Approval

7. Check Metallization and Assembly Materials Too

8. Start with the Residue You Need to Remove

9. Design a Small, Controlled Compatibility Trial

10. Inspect More Than Cosmetic Appearance

11. Common Failures in Cleaning Qualification

12. Release the Process with Clear Boundaries

FAQ

Can I rinse AlN with deionized water?

Is a neutral-pH cleaner automatically safe?

Can an alumina cleaning instruction be reused?

Does a white deposit prove hydrolysis?

Can ultrasonic cleaning be added to an approved wash?

Does an AlN powder study apply to my dense substrate?

Is alcohol a universal alternative to water?

When should a qualified cleaning process be reviewed again?

Sources and Technical Support

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Use the Finished Etched Geometry, Not Only the Artwork

Keep Coatings and Finish Consistent With the Model

Verify the Straight Line and the Launch Separately

Release a Cross-Section, Not Just a 50-Ohm Label

FAQ

Are CPWG, GCPW and CBCPW always different structures?

Does copying a reference-board trace width guarantee 50 ohms?

Can a very short feed ignore the distinction?

Does passing the CAD design-rule check verify the impedance?

Is adding top ground beside microstrip always an improvement?

Can a hatched lower plane be modeled as a solid plane?

Why might two GCPW tools disagree with identical input numbers?

Does good return loss prove low transmission loss?

Discuss the RF Stackup

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Solve Width and Stackup Together

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Even Mode Is Not Another Name for Differential Mode

Recognize Where the Uniform-Line Model Stops

Write the Fabrication Requirement in the Correct Mode

Close the Design with a Reproducible Verification Basis

FAQ

Will a 100-ohm resistor make a 90-ohm pair become 100 ohms?

Why does my multimeter not read 100 ohms between the traces?

Are all high-speed differential interfaces specified at 100 ohms?

Can I double a single-ended TDR result to obtain differential impedance?

Does correct differential impedance guarantee equal propagation delay?

Does a symmetric drawing guarantee no mode conversion?

Can a solder-mask change affect the pair without changing its artwork?

Is impedance the only reason to keep a pair’s spacing consistent?

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