Microvia Reliability: Read the Reflow Resistance Trace

November 10th, 2026

Don’t release an HDI lot on the strength of a cold continuity check alone when the purchase requirements call for reflow-monitored resistance. First verify that the coupon reproduces the critical via structure. Then compare its resistance trace with the agreed reference and temperature profile. A chain can read normally after cooling even if it opened during heating.

Mounted PCB cross-section with copper interconnections and dielectric layers — Illustrative rendering of a cross-section specimen. Use the actual stack drawing and coupon record to identify via geometry.

microvia reliability

Microvias connect adjacent PCB layers in dense layouts. During soldering, the board expands and contracts, stressing these connections. A room-temperature continuity result answers whether the path conducts at that moment. It does not reveal an interruption that occurs only at elevated temperature. Ask for the evidence that matches the anticipated assembly exposure.

stacked vs staggered microvias

A stacked design places one microvia above another. A staggered design offsets them and joins the paths on a shared layer. When the board uses both, identify which geometry each coupon actually represents. A result from a staggered chain should not be used to approve an unrepresented stacked interface. For routing and construction trade-offs, see the BestPCBs comparison guide.

Board feature	Check on the coupon
Stacked microvias	Same layer spans and stacked interface
Staggered microvias	Correct layer spans and offset pattern
Mixed connections	Coverage of each structure required for release

pcb daisy chain

A daisy chain connects many via structures in series so that a change anywhere in the path can appear in the resistance record. Ask for the chain ID, layer pairs, structure count and panel-to-coupon relationship. The resulting trace describes the chain, not the resistance or failure location of an individual via. A chain that includes other structures may require fault isolation.

Bare test coupon and measurement leads on an electronics lab bench — Illustrative rendering of a coupon setup, not a test log or a pass result.

pcb reflow profile

Compare traces only under the approved profile and measurement convention. Record the test method and revision, profile, cycle count, temperature measurement location and reference resistance. For a performance-based evaluation under IPC-TM-650 2.6.27, use the reference and acceptance criteria in the applicable revision and procurement agreement. Do not silently substitute a cold baseline for a specified hot reference.

Report field	Why it matters
Profile and cycle	Matches the specified exposure
Resistance in Ω or mΩ	Identifies the measured chain and reference
Change in %	Shows the result at the specified comparison point
Temperature and time	Locates the event within the cycle

microvia failure

Consider an illustrative chain with a specified hot reference of 0.500 Ω. A comparable point in a later cycle reads 0.530 Ω. The relative rise is (0.530 − 0.500) ÷ 0.500 = 6%. If the project limit were 5%, the reading would exceed it. A normal cold reading afterward does not cancel the event. These values are a worked example, not a test report or a universal limit.

Check whether the event is synchronized with temperature and whether other channels show a simultaneous fixture disturbance. Preserve the original trace and reference coupon. When instrumentation remains a plausible cause, use the documented investigation or retest procedure instead of deleting the event or releasing on the final reading alone.

pcb microsection analysis

Use the electrical record to choose where to section. A section can show a physical discontinuity at a sampled interface, but a clean section elsewhere cannot rule out a hot-only failure in the chain. Ask the lab to correlate the section location with the failed net, stack and panel rather than accepting an unlabeled image.

interconnect stress test pcb

Convection reflow simulation reproduces an agreed assembly heat exposure. DC current-induced thermal cycling is a different test method with a different heating mechanism and protocol. Don’t accept one in place of the other simply because both include resistance readings. Match the report to the contracted exposure, specimen and evaluation method.

pcb thermal cycling test

Specify separately any cycling needed to qualify the board for service. A reflow simulation result alone does not establish lifetime under operational temperature changes. For lot release, verify the approved coupon map, profile, complete trace and disposition of any anomalies. If the controlling geometry or hot record is missing, mark the evidence incomplete rather than treating the omission as a pass.

FAQ

Is the final resistance value enough?

No when the requirement covers behavior during the cycle. Inspect the agreed measurement interval and preserve any anomalous excursion.

Can an unmarked coupon represent every panel?

Not without documented traceability and an agreed sampling plan. Link its identity to the appropriate panel, lot and build.

Does a resistance excursion prove a microvia crack?

No. It locates a suspect time and chain. Check the test setup and use targeted failure analysis before assigning a cause.

Can I compare two chains with different numbers of vias directly?

Not by raw resistance alone. Geometry and chain length affect the value. Use the prescribed baseline and compare equivalent structures where possible.

Does a passed stacked coupon qualify a deeper stack?

Not automatically. Additional interfaces and different layers can change the behavior. Confirm that the evidence represents the intended construction.

Does the oven setpoint equal coupon temperature?

No. Confirm the recorded measurement convention and coupon temperature rather than assuming the displayed setting is the specimen profile.

Can I approve the lot if the report only says pass?

Only if that is sufficient under the agreement. When the purchase requires traces, conditions or specimen details, request the missing evidence before release.

What should I retain for a repeat order?

Keep the approved stack, coupon ID and drawing, reference convention, test profile, original records and disposition together with the production revision.

Sources

IPC-TM-650 2.6.27B: convection reflow assembly simulation; IPC-TM-650 2.6.26A: DC current-induced thermal cycling.

Project Review

For a Best Technology fabrication discussion, send the critical via stack, intended assembly exposure and coupon acceptance requirements to sales@bestpcbs.com.

Tags: HDI PCB, Microvia Reliability, pcb test coupon, Reflow Simulation
Posted in bestpcb | No Comments »

PCB Thermal Relief Troubleshooting: Find the Hot Spot

November 10th, 2026

If a power terminal runs hot, don’t replace its thermal relief with a solid connection until you know where the voltage is lost. Under a controlled load, compare the terminal and joint with the pad-to-plane transition and the downstream copper. Only change the relief when the evidence points to that transition, then retest both solder quality and operation.

Bare PCB showing a through-hole pad connected to a copper area through relief spokes — Illustrative rendering of a relief connection. Use the actual exported copper to count and measure spokes.

what is thermal relief in pcb

Thermal relief leaves a gap between most of the pad perimeter and its same-net copper plane, with short copper spokes bridging that gap. Less copper cross-section slows heat flow out of the pad while soldering. The same restriction remains in service, so easier soldering and lower operating resistance are separate goals.

thermal relief vs direct connect

A direct connection is a useful comparison build when the suspect span is the pad-to-plane transition. Keep the connector, copper build and load the same. Changing the connector and the pad in the same trial makes it hard to tell which part of the current path improved. The general thermal relief design guide covers first-pass layout decisions; this article starts with a board that is already running hot.

Connection	When to consider it	Verify
Relief spokes	Plane slows joint heating	Joint, drop and heat
Direct copper	Spokes limit current path	Joint and copper neck
Revised spoke geometry	Both constraints matter	Actual fill and tests

thermal relief spoke width

Use finished width, length and copper thickness when estimating a spoke path. Increasing width or adding equivalent spokes can lower its resistance but also lets more heat leave the pad during assembly. In an ideal group of equal spokes, their conductances add in parallel. Real current distribution depends on where the plane is fed, so a layout with four spokes drawn does not necessarily share current evenly.

Parameter	What to verify
Spoke width and length, mm	Finished geometry on each connected layer
Remaining spoke count	Connections after zone refill and export
Copper thickness, µm	Applicable layer and fabrication build
Drop and temperature	Named points and defined load conditions

pcb thermal relief gap

The relief gap separates the rest of the pad from the plane. A larger gap can lengthen the copper bridge; a nearby clearance can remove a spoke entirely. Refill the zone after a routing change, run the connection checks and inspect the released copper layer. A net name or a schematic check cannot establish what was fabricated.

pcb thermal relief high current

Use the actual operating load and allowable drop to judge the power pad. In a hypothetical 8 A terminal comparison, suppose a four-wire measurement across matched pad-to-plane points gives 3 mΩ for one build and 1 mΩ for another. The corresponding drops are 24 and 8 mV; calculated dissipation in that measured span is 0.192 and 0.064 W. These values are not ratings or measured results. They show why a milliohm-scale restriction can matter.

Plan accessible, named voltage-sense points before energizing the setup. If the board exposes them, use the terminal metal, the PCB pad and the plane just beyond the relief as three successive references. Put the load-current leads outside the sense span. A large terminal-to-pad drop points to the joint and intervening metal; a large pad-to-plane drop points to the PCB transition. If the pin-to-pad boundary is not accessible, report the combined span instead of assigning the loss to the joint. A distant point on the plane can add the loss of an unrelated narrow region.

Compare like-for-like at the same load and thermal state. If the hot spot remains but all measured local voltage drops are small, check for a nearby heat source or an unsuitable surface for infrared temperature measurement before blaming the spokes. The busbar joint resistance guide shows the same principle of separating a joint from its conductor.

thermal relief soldering

Check the actual assembly method before treating a solid connection as a defect. A joint that is hard to make by hand may be acceptable under a qualified production process. Conversely, a low-resistance layout is not ready if the joint fails the required inspection. Compare the relief and direct options using representative boards and the intended process; don’t compensate with unapproved soldering conditions.

Power terminal on a circuit board with copper areas and nearby through-hole pads — Illustrative rendering of a power terminal. A real comparison requires the same load, assembly process and measurement span.

pcb copper pour

Trace the current from the connector through the pad, spokes or direct entry, layer transitions and the next component. The useful width is the narrowest effective path, not the largest patch of copper in the layout view. Keep unrelated pads on the chosen general rule; apply a documented override only where the individual connection needs it.

pcb thermal relief guidelines

Decide what to change based on the span that failed. For a joint issue, review solder fill and the assembly method. For a PCB transition issue, compare wider spokes or direct copper. For loss downstream, fix the neck or layer transition and leave a sound pad unchanged. Release only after the revised joint, drop and temperature rise meet the agreed limits at the intended load, ambient and enclosure conditions.

FAQ

Are four spokes always better than two?

No. More effective copper can lower resistance, but the result depends on geometry and feeding. It also changes heat flow during soldering.

Does increasing board copper weight fix a missing spoke?

No. First fix or qualify the actual connection. Extra copper cannot replace a segment removed by the pour clearance.

Can I apply the same relief to every ground pad?

Not by default. A signal return, power terminal and heat-dissipating pad may have different connection needs even when they share a net.

Is an exposed package thermal pad the same as thermal relief?

No. A package thermal pad may need to conduct heat away in service. Relief spokes deliberately reduce the copper path around a pad.

Can I use a trace-width calculator as the final acceptance test?

No. It can help screen the layout, but it does not capture every local bottleneck or reproduce the full assembly and load conditions.

Should I measure resistance cold or after loading?

Record both when useful and keep the measurement span fixed. The operating drop and temperature should be checked under the specified load.

Why does my CAD tool report incomplete relief?

A zone rule or nearby clearance can prevent the required number of spokes from connecting. Refill and inspect the actual copper before changing the rule.

Can the same choice be reused after a connector change?

Recheck the pad geometry, copper path, current and assembly conditions. The prior result applies to the tested construction, not automatically to a new footprint.

Sources

KiCad PCB Editor: zone and pad connection settings.

Project Review

For a Best Technology fabrication discussion, send the finished copper thickness, high-current pad geometry, expected load and intended assembly process to sales@bestpcbs.com.

Tags: Copper Pour, High Current PCB, PCB Thermal Relief, solderability
Posted in bestpcb | No Comments »

CAN FD Termination Guide: Check Resistance and Ringing

November 10th, 2026

Start with two matched end terminations on a conventional linear CAN FD bus. With the bus safely de-energized and the applicable network isolated, about 60 Ω across CANH and CANL is a useful check for two nominal 120 Ω ends in parallel. It cannot tell you where those resistors are or whether a long stub is causing ringing. Check the physical ends next, then measure the differential and common-mode waveforms separately.

CAN controller PCB beside a twisted pair connected to a terminal block — Illustrative rendering of a CAN interface, not a validated circuit or a compliance result.

can fd termination

Termination matches the end of a transmission line to reduce reflected edges. The physical ends of the trunk are the ends that matter, not the two nodes with the lowest software addresses. Confirm the bus topology and cable impedance before applying the conventional two-end model. An engineered non-linear network needs its own analysis rather than extra resistors added by trial and error.

can bus termination resistor location

Walk the actual harness and mark both ends, every branch and any switchable termination. A termination at an intermediate node can still contribute the expected DC resistance while leaving a length of cable beyond it unterminated. In a hypothetical controller and sensor harness, a service node is plugged in midway and accidentally has termination enabled. If the far end is also missing its resistor, the meter can still show 60 Ω, yet the far end remains electrically open to an arriving edge.

can bus termination resistor value

For the conventional 120 Ω network, use a nominal 120 Ω differential termination at each physical end. In a split arrangement, two matched nominal 60 Ω resistors form one 120 Ω end. The midpoint capacitor adds a path for common-mode AC energy without adding a DC resistor across the pair.

Parameter	What to verify
Nominal end resistance	120 Ω for the conventional cable
Split pair	Two matched 60 Ω resistors per end
Midpoint capacitor	Value, rating and return for this design
Resistor power	Check fault voltage, duration and part rating

can bus termination resistance

With power removed and the network in the intended measurement state, compare the reading with the expected parallel combination. Two 120 Ω resistors give 60 Ω, one gives 120 Ω and three give 40 Ω in the ideal calculation. Treat those as clues, not acceptance limits: tolerances, other DC paths, internal switches and the connected harness can change the reading. Segment the harness as permitted and identify each termination before concluding that a board needs rework.

can fd split termination

Use a single resistor when the end is correctly matched and the common-mode behavior meets requirements. Consider split termination when the end match is right but common-mode disturbance remains an issue. It adds parts and a return path to review. It does not move a termination to the right place or shorten a stub.

Option	Use when	Verify
Single resistor	End match and emissions are acceptable	Value and physical location
Split pair plus capacitor	Common-mode improvement is needed	Matching, return and EMC result
Topology correction	There is an incorrect end or long stub	Reflection at the affected receiver

can bus split termination capacitor value

Choose the starting value from the transceiver and system guidance. NXP’s FS2400 example lists 4.7 nF as a nominal option, not a universal requirement. In a simplified common-mode model, the two 60 Ω branches act in parallel, so the effective resistance is 30 Ω. Together with 4.7 nF that gives about 1.13 MHz for the ideal RC corner. Cable and return impedances, parasitics and other components change the real response. That number is not a CAN FD data-rate limit and cannot predict compliance.

can bus signal reflections

If errors cluster after edges or at the faster data phase, look for timing and topology clues before changing the capacitor. On the hypothetical service harness, restore termination at the physical far end and disable the misplaced branch termination. Repeat the same capture. If ringing persists at one branch, compare the branch connection and length against the approved network design. A changing common-mode signal alone is not proof of a differential reflection.

can bus oscilloscope waveform

Measure CANH minus CANL for differential behavior and, with a suitable referenced and matched setup, use their average to inspect common mode. Follow the instrument and equipment safety instructions and avoid grounding a floating bus through the probe. Compare the same receiver, harness, traffic and supply conditions before and after changes. Release only when the correct end map, resistance, waveform or timing limits, error behavior and any required system EMC tests meet the project plan.

CAN evaluation board and twisted pair on a bench near an oscilloscope — Illustrative rendering of a scope bench. Use calibrated measurements and the actual receiver location for comparison.

FAQ

Why do I see 60 Ω but still get errors?

The meter cannot locate the resistors or see stubs, receiver timing or interference. Confirm the end map, then capture signals at the failing receiver.

Should every node include an enabled 120 Ω resistor?

No. In a conventional linear trunk, enable termination at the two physical ends. An optional resistor footprint on an intermediate node can remain unpopulated or disabled.

Does split termination change the nominal differential DC resistance?

Not when each end still sums to the specified end resistance and the midpoint capacitor has no DC conduction path under the measurement conditions.

Can I choose capacitor size by looking at the data rate?

Not alone. The midpoint network targets common-mode behavior. Start from the device guidance and verify it against the actual noise and immunity requirements.

Does unplugging a node always leave the resistance unchanged?

No. The unplugged module may contain an end resistor or active termination. Identify what was removed and re-evaluate the expected reading for that configuration.

Should I fit a common-mode choke before changing the layout?

Check the failure mechanism first. A choke may help a specific emissions or immunity issue, but it will not correct an unterminated cable end or an overly long stub.

Is a clean waveform at the transmitting node enough?

No. Check the receiver that sees errors and other electrically distinct points. A reflection that is mild at one location may be significant at another.

What if the conventional 60 Ω rule does not fit this network?

Use the network designer’s topology and expected measurement state. Switched termination, active networks and branches require interpretation beyond the simple parallel model.

Sources

NXP AN14183: CAN components example; TI: TCAN evaluation module termination options; TI: split termination and common-mode behavior.

Project Review

For a PCB fabrication discussion, send Best Technology the board stackup, connector region and proposed termination footprints at sales@bestpcbs.com. If the protocol itself is still being selected, see the CAN bus vs LIN bus guide.

Tags: CAN FD, PCB Layout, Signal Integrity, Split Termination
Posted in bestpcb | No Comments »

USB 2.0 ESD Protection: Where to Put the Diode on a PCB

November 10th, 2026

For a USB 2.0 High-Speed port, start with a low-capacitance ESD diode close to the connector. Route D+ and D− past the protection pads without long branches, and give the diode a short return into the intended reference. Verify both USB signal quality and system ESD behavior: a board can enumerate and still reset during a discharge, or survive a strike and still fail the High-Speed eye test.

USB-C receptacle with small protection components at the edge of an assembled PCB — Illustrative rendering of a connector area, not a reference layout or a test result.

usb 2.0 esd protection

Protect the path from the exposed connector to the USB transceiver. When a transient exceeds the diode’s operating region, the diode conducts current into its return path instead of allowing all of the pulse to continue toward the transceiver. During normal signaling the device should remain off, but its capacitance still loads the pair. The goal is to minimize both the discharge loop and the disturbance seen by the data signals.

usb esd protection circuit

Draw two paths before choosing the footprint: the D+/D− signal path from the connector to the PHY, and the transient current path from each exposed data line through its protector into the designated return. The reference circuit for the selected part determines which pin is the return and whether the device uses a rail reference. A D+/D− protector does not establish protection for VBUS, CC or SuperSpeed pairs. For the rest of the interface, see the USB-C PCB design guide.

usb 2.0 esd protection diode

Choose a device against the PHY and connector requirements, not the largest advertised discharge rating. For example, TI’s USB application note lists ESD122 as a dual-channel D+/D− option with a 3.6 V reverse working voltage and 0.2 pF listed capacitance. Those figures belong to that device; use its current datasheet for test conditions and limits, then check actual layout and system behavior.

Parameter	Decision check
Working voltage, V	Check against normal line voltage
Line capacitance, pF	Use stated test conditions and PHY budget
Clamping voltage, V	Compare only at matching pulse conditions
Channel and package	Confirm pin map and a routable return
Discharge rating, kV	Check method; verify on the complete product

esd diode placement

Put the protector at the first practical point after the connector and keep both the connection to the data pads and the discharge return short. A component can look close in the placement view while its ground trace makes a long trip around a cutout. Check the copper layers and return vias, not just the component outline. Do not route the unprotected connector segment alongside sensitive circuitry if it can be avoided.

Close-up of a board-edge USB-C receptacle and a nearby black leadless component — Illustrative rendering. Verify the chosen footprint and discharge return on the actual PCB.

usb esd protection layout

Prefer flow-through routing when the part and footprint allow the data traces to pass directly through the protection-pad area. The diode remains a shunt element; the name describes the routing, not a series electrical connection. A short branch can be an alternative if the pinout forces it and the implemented design passes both signal and system ESD tests.

Routing option	Use and trade-off
Flow-through	First choice when pad map and return align
Very short branch	Possible when constrained; measure the result
Long branch or remote clamp	Revise: extra stub and transient loop

usb differential pair routing

Keep the two data paths physically similar through the connector, protector and first layer transition. Review reference continuity and avoid adding a long test stub to only one member of the pair. In a hypothetical compact service-port board that resets during cable-side testing, first inspect the discharge route and nearby reset or power circuits. If the same board also shows poor High-Speed signaling, check the diode capacitance, pad discontinuities and pair asymmetry before choosing a different clamp rating.

usb 2.0 differential impedance

The usual High-Speed differential routing target is 90 Ω nominal; confirm the tolerance and stackup requirements for the design. A calculated trace width covers the uniform section, not the pad and via transitions. Review those transitions separately, and include the protection device’s capacitance. The relevant data rate is 480 Mbit/s in High-Speed mode, but edge behavior is not determined by the bit rate alone.

usb 2.0 eye diagram

After a layout revision, verify the applicable High-Speed electrical test separately from the system ESD test. Use the specified USB test mode and fixture for the electrical test; for ESD, record the strike point, polarity, operating mode and allowed recovery behavior under the product test plan. Monitor real data traffic, resets and re-enumeration. Release only when the electrical result meets its applicable limits and the product meets its own ESD performance criterion. Successful charging or idle enumeration is not a substitute for either check.

FAQ

Can one array cover VBUS and the two data lines?

Some products can, but check the channel specifications and routing. VBUS operating voltage and exposure may differ from the data lines.

Is a larger TVS diode always a safer upgrade?

No. A larger part may add capacitance or create a worse return path. Check clamp behavior under comparable pulse conditions as well as link quality.

Can I place the protector on the bottom side?

Sometimes. Compare the complete path including signal vias, return vias and loop geometry. Verify the actual implementation rather than judging it by distance in a top view.

Should the common-mode choke go before the diode?

In TI’s TUSB121x example it follows the ESD protection. Confirm the sequence in the PHY and protector references and qualify it on the actual board.

Does a connector shield replace the data-line protector?

No. Shield bonding and signal-line protection address different paths. Follow the intended chassis and board grounding architecture rather than assuming they are interchangeable.

Why might the port restart even though no diode failed?

A transient can disturb the supply, reset path or reference. Capture the symptom and investigate the current route and nearby sensitive circuits before replacing the diode. The PCB ground bounce guide explains how a changing local reference can show up in a measurement.

Is a device-level rating proof of system compliance?

No. The assembled product adds connector, enclosure, layout and grounding variables. Verify it with the applicable system test and performance criteria.

Does this placement apply unchanged to USB SuperSpeed?

No. Check the separate transmit and receive paths, channel budget and AC coupling architecture. This guide addresses USB 2.0 D+ and D−.

Sources

Texas Instruments: ESD and Surge Protection for USB Interfaces; Texas Instruments: TUSB121x board guidelines; Nexperia: ESD protection for USB 2.0 interfaces.

Project Review

For a PCB fabrication discussion, send Best Technology the proposed stackup, pair geometry and connector-to-protector region at sales@bestpcbs.com.

Tags: Differential Routing, esd protection, Signal Integrity, USB 2.0
Posted in bestpcb | No Comments »

Busbar Joint Resistance: Find the Missing Millivolts

November 10th, 2026

If a thicker PCB busbar does not fix voltage drop, measure the straight copper and each connection separately. A larger cross section lowers the bar’s bulk resistance, but it does not remove contact resistance at bolts, press-fit transitions or board terminals. Fix the segment that consumes the budget, then repeat the hot test.

Copper busbars attached to terminals on a power PCB — Include the attachment and board transitions in the complete path. Illustrative rendering; not a production or test record.

Busbar Joint Resistance

Busbar joint resistance is the electrical resistance of a connection between current-carrying parts, as observed over a defined measurement span. A reading across a joint often includes some adjoining copper. Put the sense points in the drawing so another engineer can reproduce what the number represents.

Consider a hypothetical low-voltage power board that misses an 8 mV path budget at 40 A. The route includes a short copper bar and two connections. The next revision should not add more copper until the test identifies where the drop occurs.

Copper Busbar PCB

A copper busbar can carry current separately from an etched board trace. The feed, contact and exit still need to carry the same current. A press-fit, bolted or soldered connection has its own construction and verification requirements. Do not generalize current or torque limits across connection types.

Draw the path from supply to load and mark the intended measurement spans. If the board uses an embedded busbar, check the transitions into and out of it as well as the main copper. The Best Technology embedded busbar design guide covers related construction choices.

Heavy Copper PCB

Compare a heavy copper PCB path and a busbar by their complete current paths. Heavy copper can avoid a separate mechanical interface over part of the route, but narrow necks, vias and terminals can still dominate. A bar offers a separate copper cross section while adding transitions that need qualification.

Option	Check first
Heavy copper PCB	Narrowest trace, via bank and terminal
Board-mounted busbar	Straight bar and every attachment
Embedded busbar	Copper insert and board transitions

Choose by drop, temperature, assembly and service requirements, not the nominal copper area alone.

Copper Busbar Resistance Calculator

Estimate only the uniform copper section with R = resistivity × length ÷ area. Use matching units. For an illustrative room-temperature copper resistivity of 0.0172 Ω·mm²/m, 0.050 m length and 20 mm² area, the bar is about 0.000043 Ω, or 43 µΩ. The estimate excludes both joints and nearby constrictions.

Use actual material, dimensions and operating temperature when the budget is tight. The calculated 43 µΩ is not a current rating or a measured property of the hypothetical assembly.

Busbar Voltage Drop Calculation

Convert each resistance to voltage drop with V = I × R. In the example, assume two measured-span resistances of 100 µΩ each, excluding the straight segment. At 40 A they account for 8.00 mV together. The 43 µΩ straight section adds 1.72 mV, so the full path is 9.72 mV and exceeds the illustrative 8 mV budget.

Path segment	Resistance used	Drop at 40 A
Straight bar	43 µΩ	1.72 mV
Joint span A	100 µΩ	4.00 mV
Joint span B	100 µΩ	4.00 mV
Full path	243 µΩ	9.72 mV

These are teaching inputs, not field results. Even doubling the bar area would leave about 8.86 mV if the two connections were unchanged.

Four Wire Resistance Measurement

Use separate current and sense connections to reduce the influence of lead resistance. In a qualified low-energy resistance setup, place the sense contacts at the named points and use the instrument’s appropriate method. A two-wire reading can be dominated by test leads and contacts at this resistance scale.

At very small voltages, thermoelectric offsets can matter. Use a suitable measurement method, such as current reversal when the equipment and test procedure support it. Document what copper is inside each span and do not sum overlapping spans as separate resistances.

Bolted copper overlap joint in a bench test fixture — Define the voltage-sense span around the connection. Illustrative rendering; not a production or test record.

Busbar Temperature Rise Test

Repeat the temperature and voltage checks in the approved operating setup. At 40 A and 100 µΩ, each illustrative joint span dissipates I²R = 0.16 W. Whether that creates a hot spot depends on the local heat path, contact area, airflow and enclosure. A room-temperature resistance pass does not establish operating temperature.

Measure at consistent points after the agreed dwell or steady-state condition. Use only a rated, guarded setup under the approved procedure. If the joint heats more than the bar, inspect its construction and nearby constrictions before adding copper to the straight section.

Busbar Joint Resistance Test

Release the design when the assembled path meets the specified voltage and temperature limits and the connection can be built repeatably. Record joint type, materials, assembly instructions, sense locations, current and thermal conditions. For bolted joints, follow the approved hardware and torque specification rather than a general table.

After a correction, rerun the same segment and full-path checks. If voltage drop is still above target, confirm whether the remaining loss moved to a different transition before selecting another design change.

Frequently Asked Questions

Does a thicker copper busbar fix every voltage-drop problem?

No. It lowers the resistance of the uniform copper segment, but contacts, vias and terminal transitions may account for most of the loss. Measure the sections separately and compare them with the path budget. Increase copper only when the measured or modeled bottleneck justifies it.

Where should voltage sense points go?

Place them at repeatable points that bracket the segment you intend to measure. Include the positions on a drawing and note any adjoining copper inside the span. Changing the points can change the apparent joint resistance even when the physical connection has not changed.

Can I use a standard two-wire multimeter for a micro-ohm joint?

A two-wire reading includes lead and contact resistance, which may be larger than the joint itself. Use a suitable four-wire method and instrument for the expected range. Verify the setup and its offset before interpreting small differences between two joints or two assembly revisions.

Can a good cold measurement rule out a hot joint?

No. Temperature, contact condition and the operating environment can change the result. Use the cold measurement to locate and compare segments, then perform the required operating-current thermal test in an approved setup. Check both voltage drop and temperature against their separate limits.

Why can two identical-looking joints read differently?

Contact preparation, hardware, fit, plating and assembly variation can change the interface. First verify that the sense spans and test conditions match. If the difference remains, compare the controlled build records and examine the actual joint rather than assuming the bar dimensions are wrong.

Should I increase bolt torque to lower resistance?

Use only the approved joint specification for that hardware and construction. Extra torque is not a general fix and may damage parts or change the interface. Review the contact surfaces, assembly method and approved limits with the process owner, then verify the corrected build.

Can I compare a press-fit joint directly with a bolted joint?

Compare them against the same product requirements and use equivalent measurement boundaries. The assembly controls and local geometry differ, so document what each reading includes. Check resistance, temperature and mechanical reliability for the actual connection rather than ranking the joining methods by name.

What evidence is useful for a PCB busbar review?

Send the bar and terminal drawings, current and drop limits, stackup, connection method and intended operating conditions. Include a marked sense-point map and any measured segment voltages. That lets the reviewer distinguish copper cross section, board transitions and joint behavior before recommending a change.

References

Discuss Your PCB Requirements

For a Best Technology fabrication review, send the current path drawing, busbar and terminal geometry, and your voltage and temperature limits to sales@bestpcbs.com. If you have measured drop, mark the actual sense points.

Tags: Busbar Joint Resistance, Copper Busbar Drop, Four-Wire Joint Test, High Current PCB Connections
Posted in bestpcb | No Comments »

PCIe AC Coupling Capacitor Placement: Check Both Paths

November 10th, 2026

Place PCIe AC coupling capacitors only after checking which part of the link is responsible for each transmit path. Then place the two parts as a matched pair and verify their pad transitions in the actual stackup. A capacitor can be correct in the schematic and still introduce an avoidable discontinuity on the board.

Pair of ceramic capacitors placed on two differential PCB traces — Check each series part and its placement in the complete lane. Illustrative rendering; not a production or test record.

PCIe AC Coupling Capacitor Placement

Start with the platform’s channel drawing, not a rule such as “always next to the transmitter.” The transmit path tells you which lane needs coupling; physical position depends on the device and topology. Confirm which board or module provides the series parts and whether the device already integrates coupling.

Consider a hypothetical endpoint on an adapter connected to a host through a slot. Mark host transmit and endpoint transmit as separate paths. A placement decision that is correct for one direction does not automatically assign the parts in the reverse direction.

AC Coupling Capacitor for PCIe

A series coupling capacitor blocks DC while allowing the changing signal to reach the receiving path. It is not the same part as a supply bypass capacitor or a capacitor that links reference planes. On a differential lane, the approved coupling arrangement must be implemented on both conductors.

Review item	What to verify
Transmit ownership	Host and endpoint paths traced separately
Existing series parts	On-device, adapter, or host implementation
Placement	Topology-specific vendor guidance
Part geometry	Same approved launch on both conductors

Check the schematic against the actual channel and bill of materials. Do not add a second pair simply because a connector sits between boards.

PCIe AC Coupling Capacitor Value

Choose capacitance from the applicable platform or device documentation. TI’s PCIe Gen 5 layout note discusses a 75–220 nF range and describes 220 nF as typical in its context. Those values do not override requirements for a specific component, topology or implementation.

Check approved value, tolerance, package, voltage and the relevant high-frequency model together. A nominal capacitance match does not prove two components behave the same through their mounting geometry and parasitics.

AC Coupling Capacitor Size

Compare the solder land with the controlled trace before selecting a package. In TI’s illustrative Gen 5 layout, a 12 mil pad is wider than a 5–7 mil trace. At an illustrative 6 mil trace width, the pad is twice as wide. That ratio is a geometry warning, not a formula for the resulting impedance.

Placement option	Potential benefit	What to confirm
Smaller approved package	Smaller pad transition	Assembly and component limits
Existing larger footprint	Established assembly process	Modeled discontinuity is acceptable
Staggered pair	Fits a crowded area	Both paths still have comparable electrical response

Differential Pair Routing Guidelines

Make the two capacitor launches geometrically comparable. Use matching footprints, equivalent approach and exit routes, and comparable vias and reference environments. Avoid adding a jog or changing layers on one conductor just to align both components visually.

If routing forces a stagger, compare the actual two-path electrical response rather than assuming a neat centerline layout compensates for it. Keep nearby copper, neckdowns and return geometry in the model.

Parallel copper routes with corresponding SMD footprints on a test coupon — Compare the two pad transitions and their reference geometry. Illustrative rendering; not a production or test record.

Differential Pair Impedance

A wider mounting pad can create a local impedance dip. The depth of that dip depends on the dielectric, pad, neighboring conductor and reference plane. A small package or an engineered transition can reduce the discontinuity, but neither automatically proves the channel is within budget.

Model the footprint and launch together, and compare the result with the channel’s permitted impedance and loss behavior. Use the final land pattern, not only the package body dimensions or the nominal routed trace impedance.

PCB Return Path

Preserve the intended return path. Some platform notes use a localized reference-plane void under the capacitor launch to reduce excess capacitance. Treat that as a stackup-specific design choice. Do not cut a long slot beneath the pair or transfer the same void to a board with different layers without checking the effect.

Compare an intact reference and the proposed local relief in the actual stackup if the device guidance permits. Include both conductors and surrounding geometry. If local impedance improves but conversion or return-path behavior worsens, revise the transition instead of approving it on a single result.

PCIe Gen 5 Layout Guidelines

Release the design when ownership, capacitance, placement and both electrical paths have been checked against the approved platform. For the hypothetical adapter, verify both transmit directions, then compare the matched footprint against the actual connector and stackup. Save the channel model and the intended verification method with the board revision.

Use the Best Technology PCIe routing guide for the wider channel constraints. A link that trains on one bench sample is useful evidence, but it is not a substitute for the margin or compliance tests required for the product.

Frequently Asked Questions

Do PCIe coupling capacitors belong next to the transmitter?

The transmitter identifies the path that needs the approved coupling arrangement. It does not create a universal physical placement rule. Check the platform topology and device layout guidance. A chip-to-chip path and a chip-to-connector path can have different recommended locations for the same function.

What if both boards already contain series capacitors?

Trace the channel and confirm whether the parts are intended to operate together. Two series capacitors change the effective coupling behavior, so do not leave both simply because each board uses a familiar reference design. Resolve ownership against the approved host, adapter and endpoint requirements.

Can I place one capacitor farther along the pair?

Only if the resulting channel still passes the applicable electrical checks. The location difference can change how the discontinuities interact. Compare the complete launch, return environment and differential response rather than treating matched copper length or identical component values as sufficient evidence.

Is 0201 always the best package?

No. A smaller package can reduce the pad transition, but it must be available in the approved electrical value and suitable for the assembly process. Use the actual mounting land and model. A different package is acceptable only if the electrical and manufacturing requirements are met.

Does a plane void always improve the channel?

No. A controlled local void can help a particular capacitive pad transition, but a larger or poorly placed opening can disturb the return path. Follow the device guidance and compare the geometry in the actual stackup. Do not apply a blanket cutout underneath the entire lane.

Can an AC coupling capacitor repair a bad reference-plane transition?

No. The series component has a different function from managing a signal’s return path. The pad and nearby vias must still have a suitable reference environment. Check the reference-plane transition and coupling launch independently, then evaluate their combined effect in the complete channel.

What should I check after a PCIe link trains successfully?

Confirm the expected lane width and operating speed, then follow the platform’s margin and validation plan across required conditions. Keep the channel model, device settings and assembly revision with the results. One successful training event does not prove every lane and product condition has adequate margin.

What files help with a capacitor placement review?

Send the transmit ownership diagram, schematic, package and land pattern, final stackup, and both conductors around the capacitor. Include connector and via details plus any proposed plane relief. That makes it possible to compare the two launches instead of judging the placement from a cropped image.

References

Discuss Your PCB Requirements

For a Best Technology fabrication review, send the PCIe stackup, capacitor footprint and paired route geometry to sales@bestpcbs.com. Mark the connector transitions and any localized reference-plane voids.

Tags: Differential Pad Symmetry, PCIe AC Coupling Placement, PCIe Channel Verification, Series Capacitor Launch
Posted in bestpcb | No Comments »

Serpentine PCB Trace: Check Delay, Not Just Length

November 10th, 2026

A serpentine PCB trace adds centerline length, but tightly spaced bends can change how much delay the added length produces. Start with the timing error you need to correct, make a straight-trace estimate, and then compare the actual routing shapes on the same stackup. A CAD length match is not the final pass condition.

Bare PCB coupon with a folded copper trace and a straighter reference route — A folded path adds length, but closely spaced legs can couple. Illustrative rendering; not a production or test record.

Serpentine PCB Trace

A serpentine trace folds extra conductor into a limited area. Adjacent turns can couple to each other, so the folded section may not behave like the same length of isolated straight trace. The effect depends on the geometry and signal spectrum rather than the shape name alone.

Consider a hypothetical source-synchronous interface with one signal arriving 24 ps early at the receiver. The designer can use a compact meander or route a more open detour. Both add the same CAD length on the same layer. The decision is which leaves acceptable arrival time and waveform quality.

Trace Length Matching

Use CAD length matching to screen the layout, then compare electrical arrival time at the relevant pins. Include package delay, via transitions and route layers when the interface timing model calls for them. Two equal trace lengths on different layers need not produce equal delays.

For the example, keep the vias and reference planes unchanged in both candidates. Correct only the early signal, and measure against the same reference signal and switching criterion. The Best Technology trace length matching guide covers the broader timing budget.

PCB Trace Propagation Delay

As a first estimate, multiply added length by the straight-trace propagation delay per unit length for the actual layer. If an illustrative straight route has 6 ps/mm of delay, 24 ps ÷ 6 ps/mm suggests 4.0 mm of added centerline. This calculation is a starting target, not the predicted delay of a coupled meander.

Input	Example only
Early arrival	24 ps
Straight trace estimate	6 ps/mm
First added-length target	4.0 mm
Electrical acceptance	Use the interface timing budget

Do not reuse 6 ps/mm across all stackups. Use layer-specific data or a suitable field model and keep the package and board portions of the timing budget distinct.

PCB Trace Spacing

Define spacing between adjacent serpentine legs edge to edge, and note the width and distance to the reference plane. Close parallel runs and long coupled overlap can change both the delay and the impedance behavior. There is no single spacing multiplier that proves the path meets a particular timing budget.

When room is available, compare fewer, more open bends or a gently extended route with the compact geometry. Use a continuous reference plane and avoid creating a new coupling problem with nearby traces to make room for the tune.

PCB Crosstalk Simulation

Model the tuning section with its actual neighbors and return plane, not as a straight segment with the same length. Inspect the simulated transfer response or time-domain arrival, impedance discontinuities and relevant crosstalk. Coupling within one folded signal is a separate concern from coupling to an adjacent aggressor; both can matter.

Candidate	Why try it	What can disqualify it
Tight meander	Fits a narrow corridor	Delay gain or impedance margin is poor
Open meander	Separates neighboring legs	Uses space needed by another route
Longer detour	Avoids tightly packed folds	Adds vias or changes reference path

Compare candidates at the same electrical reference points. An apparently faster waveform caused by unequal fixture or launch models is not evidence about meander spacing.

PCB test structures with tightly and loosely folded copper routes — Compare tuning shapes at the same electrical reference points. Illustrative rendering; not a production or test record.

Differential Pair Skew Compensation

In a differential pair, determine whether the problem is skew within the pair or delay between pairs. Adjusting one conductor can correct intra-pair skew, but a wide detour may also disturb pair coupling and create mode conversion. Routing both conductors together changes pair delay while preserving symmetry better, but does not selectively correct one conductor’s lead.

Keep the interface-specific limits and validate the differential waveform and mode conversion where they matter. Do not transfer a tuning prescription from a single-ended bus directly to a tightly coupled differential pair.

Serpentine Routing Guidelines

Compare both candidate routes against a straight reference and change one tuning variable at a time. Suppose a hypothetical controlled simulation predicts 18 ps added delay for a tight shape and 23 ps for an open shape, each with 4.0 mm added CAD length. The remaining error would be 6 ps or 1 ps, respectively. These values are illustrative, not measured or expected values for any design.

If both pass timing and signal quality, choose the geometry that fits without disturbing adjacent routes. If neither passes, reconsider the placement or route and rerun the analysis. Do not add another fold solely to remove a visual mismatch in CAD.

Time Domain Reflectometry PCB

Use time-domain reflectometry to check impedance changes through the tuning section. A reflection trace is not a direct one-way delay comparison between two receivers. For arrival time, use a suitable through measurement, a correctly referenced transmission model or a calibrated system measurement, depending on the design.

Release when the timing result, discontinuity limits and relevant neighboring-net or differential checks all pass. Keep the route, stackup, reference planes and model or test conditions linked to the verified revision so the result survives the next design change.

Frequently Asked Questions

Does a serpentine always add the expected delay per millimeter?

No. The straight-line estimate is useful for sizing the first candidate, but close folds can change effective delay. Simulate or measure the actual routed section and compare it with the same reference path. Keep the signal bandwidth and the reference planes consistent across candidates.

Is a larger gap always the best solution?

A larger gap can reduce interaction between adjacent legs, but it costs routing area and may push the route toward other signals or a broken reference. Compare the actual alternatives against timing and signal-quality limits. Prefer the one that passes without creating a new layout problem.

Can I tune two traces by matching their length on different layers?

Not without checking layer-specific delay. Different reference spacing and dielectric construction can change propagation, and vias add transitions. Use a timing model that includes those paths. A length report from the layout tool is a geometry check, not proof that the two signals arrive together.

Should I put the whole tune near the receiver?

There is no universal location. For a differential pair, think about where skew is introduced and how much unbalanced routing the correction creates. For a single-ended group, check neighboring signals and the return path. Compare the actual proposed positions in the model rather than relying on a default location.

Can a tightly folded trace be acceptable on a slow signal?

It can be acceptable if the actual edge, timing and noise limits are met. Repetition rate alone does not describe signal bandwidth; a low-rate interface can still use fast edges. Use the driver transition and interface constraints to decide how much validation the geometry needs.

What if the timing model and bench test disagree?

Check the reference planes, launch geometry, stackup and measurement thresholds before blaming the routing. Compare the same edge and operating condition, and account for fixture effects where necessary. Retain both records and resolve the difference before using the model to justify a marginal result.

Is the CAD tool’s differential tuning score enough for release?

No. The tool can show length and rule compliance, but the electrical result depends on stackup, coupling, transitions and the interface budget. Verify the actual differential response and skew where required. A clean length report does not certify that the tuned geometry preserves signal quality.

What files help with a serpentine routing review?

Send the routed section and neighboring nets, stackup and reference layers, trace dimensions, spacing, via details and the timing target. If possible, include both the compact and open alternatives. This gives the reviewer enough information to compare the real geometry rather than just the CAD length.

References

Discuss Your PCB Requirements

For a Best Technology fabrication review, send the stackup, routed tuning geometry and impedance requirements to sales@bestpcbs.com. Include both candidate layouts if you need to compare how the fabrication rules affect them.

Tags: Electrical Length Matching, PCB Meander Spacing, Serpentine Trace Delay, Trace Self Coupling
Posted in bestpcb | No Comments »

Thermal Via Spacing: When a Denser Array Helps

November 10th, 2026

Closer thermal via spacing helps only if the via barrels are a meaningful part of the heat path. Before packing more vias under a QFN pad, compare the two arrays on the same copper and stackup, check that the solder joint still forms correctly, and repeat the temperature test at the same power and airflow.

Regular via array in a bare QFN exposed-pad land — Compare actual via lands and paste windows, not just the centers. Illustrative rendering; not a production or test record.

Thermal Via Spacing

Thermal via spacing is the center-to-center distance between vias that transfer heat through the board. It does not determine temperature on its own. The pad size, via diameter and plating, copper planes, and the path from the board to air or a heatsink all matter.

Consider a hypothetical power QFN with a 3 × 3 via array. The board runs hotter than expected at a steady load. The designer wants to change only the via count. Compare that option with improving copper spreading or the board-to-heatsink interface before assuming pitch is the limiting variable.

Thermal Via Array

Compare arrays that fit in the same usable pad region. In this example, a 3 × 3 array at 1.00 mm pitch and a 4 × 4 array at about 0.667 mm pitch each span 2.00 mm between outer via centers. Neither value includes the via land radii, required edge margin or paste pattern.

Parameter	Array A	Array B
Via count	9	16
Center pitch	1.00 mm	About 0.667 mm
Outer-center span	2.00 mm	2.00 mm
Via barrel and stack	Same assumed geometry	Same assumed geometry

Overlay the copper, drill and stencil data. An array that fits by center points alone may not leave enough room for the actual lands, mask or paste windows.

Thermal Via Diameter

Distinguish the finished hole diameter from the drilled hole and pad diameter. For a simplified barrel with 0.25 mm inner diameter and 0.025 mm wall thickness, the outer barrel diameter is 0.30 mm. The land can be wider. A larger land does not add the same axial copper area as a thicker barrel.

Ask for the approved drill, plating and via construction. Via fill and surface finish also affect the assembly decision. Use the package supplier’s land and stencil guidance for the actual component instead of borrowing a via diameter from a different exposed pad.

Thermal Resistance of PCB Vias

The barrel conducts heat along its copper wall. The cross-sectional area is π ÷ 4 × (outer diameter² − inner diameter²). In the illustrative geometry it is about 0.0216 mm². Do not count the air in an open hole as solid copper.

Assume uniform copper, equal temperature at all top via ends and equal temperature at all bottom ends. This idealization lets the barrel conductances add in parallel. It does not account for how heat spreads across the pad or through the receiving plane.

Thermal Resistance Formula Conduction

For one uniform conduction path, thermal resistance is length divided by conductivity times cross-sectional area: R = L ÷ (k × A). At 1.60 mm length, an illustrative copper conductivity of 390 W/(m·K), and 0.0216 mm² of wall area, one barrel is about 190 K/W. Convert mm and mm² to meters and square meters first.

Under the equal-end-temperature assumption, nine barrels give about 21.1 K/W and sixteen give about 11.9 K/W. This is a barrel-only estimate, not a junction-to-ambient rating. If both arrays connect into a poorly spreading region, the assembled temperature difference may be much smaller.

Thermal Via Solder Wicking

Check the solderable pad before approving a denser pattern. Open holes can draw solder away from the joint. More vias can change available paste area and the joint’s void pattern. Review the package recommendation, assembly process and available via treatments together.

See the Best Technology guide to solder wicking through thermal vias for the joint-side checks. Use the agreed inspection method and joint acceptance criteria; a lower board temperature does not excuse a failed solder joint.

PCB Thermal Resistance

Interpret the temperature result as a system measurement. Hold the copper layout outside the test pad, component, board stackup, heatsink contact, airflow, ambient and actual dissipated power as constant as practical. Measure at the same defined point and after a comparable steady-state condition.

Observation	Decision
Denser array lowers temperature repeatably	Verify joint quality and final conditions
Both arrays run similarly	Investigate spreading, interface and airflow
Denser array harms the joint	Change via treatment or paste plan before release
Power or airflow changed	Repeat the controlled comparison

If the product limit is junction temperature, use an appropriate package method for estimating or measuring it. A board thermocouple at an arbitrary spot is not a direct junction measurement.

PCB mounted on a heat spreader with a temperature sensor — Fix the sensor position and thermal setup for the comparison. Illustrative rendering; not a production or test record.

Thermal Via Design Guidelines

Approve the densest pattern only if it earns its manufacturing cost and passes the real requirements. Check DFM, repeat temperature measurements at the agreed operating conditions, and verify the assembly evidence. If the gain is within measurement scatter, investigate a different bottleneck rather than declaring the denser pitch a fix.

Record via count, construction, dimensions and the validated setup. If the copper stack, heatsink interface or stencil changes later, revisit the result rather than assuming the same spacing still works.

Frequently Asked Questions

Is there one recommended spacing for thermal vias?

No universal pitch fits every package or process. Use the exact component’s land-pattern guidance, the fabricator’s approved drill and copper rules, and the assembler’s paste requirements. Check the outer via margins and then compare temperature on representative hardware before approving a denser array.

Why is the calculated resistance of one via so high?

A plated barrel has a thin conducting wall. Even though copper conducts heat well, the wall area is small relative to the length of a through-board path. Several barrels can reduce that segment’s resistance in parallel, but they do not remove the other limits in the system.

Can I use the pad diameter to calculate barrel area?

No. The pad diameter describes the copper land at a layer, not the cross section of the barrel conducting through the board. Use the wall geometry and the appropriate conductive length for that model. Model any approved conductive fill separately rather than counting the whole pad as axial copper.

Can a solid fill always be treated as copper?

No. Fill materials can have different conductivities, and some fill is used for planarization rather than as a high-conductivity path. Ask for the qualified material and construction. Use its relevant properties in the model, and keep the solderable surface requirement separate from the thermal calculation.

Should every thermal via connect to a ground plane?

Only if the package electrical requirements and board design allow that connection. The exposed pad may have a specified potential. Verify the datasheet and intended planes before adding vias. A good heat path is not acceptable if it shorts nodes or violates the component’s electrical layout rules.

What if a denser array changes the temperature only slightly?

Repeat at the same power and ambient with the same sensor placement. If the change is within normal measurement scatter, do not credit the array. Check the receiving copper, thermal interface and airflow before spending more on via count, fill or additional fabrication operations.

Can I compare an infrared reading with a thermocouple reading?

Only after accounting for what and where each instrument measures. Infrared readings depend on emissivity and spot size; a contact sensor depends on placement and attachment. Define a repeatable point and method for the comparison. Do not combine unrelated readings as if they measured the same temperature.

What should be included in a thermal via fabrication review?

Send the package land pattern, stackup, drill and finished-hole data, plating requirements, pad and stencil layout, and the planned temperature test. Identify the operating power and limit you must meet. That gives the reviewer enough context to compare array geometry with fabrication and assembly constraints.

References

Discuss Your PCB Requirements

For a Best Technology fabrication review, send the component pad drawing, candidate arrays and layer stack to sales@bestpcbs.com. Include the proposed via treatment and the temperature test conditions so the drawing review addresses the actual build.

Tags: PCB Temperature Testing, QFN Via Array, Thermal Via Spacing, Via Barrel Resistance
Posted in bestpcb | No Comments »

Via in Pad vs Dogbone: Does Your BGA Fanout Fit?

November 10th, 2026

Choose a dogbone fanout if the offset via, short connecting trace and remaining escape channels fit the approved fabrication rules. Choose a qualified via-in-pad structure when the offset land blocks the escape, not merely because the BGA pitch looks small. A simple diagonal clearance check shows why an apparently workable 0.5 mm grid can fail before any trace is routed.

Two BGA coupons with flat lands and offset dogbone vias — A filled and capped land and an offset via compete for different space in the footprint. Illustrative rendering; not a production or test record.

Via in Pad vs Dogbone

A dogbone places the via beside the BGA pad and connects them with a short trace. A via-in-pad places the hole within the solder land. Moving the via can recover space on the top layer, but it can also change the assembly, stackup and inspection requirements.

Option	Choose it when	Main constraint
Offset dogbone	Via and routes clear adjacent pads	Needs room between balls
Filled and capped via in pad	Offset via blocks escape and capped process is qualified	Land flatness and fabrication steps
Blind microvia in pad	Approved stackup reaches the needed layer	Target landing and via reliability

Start with the exact package drawing. The worked geometry below is hypothetical and must not replace the component vendor’s layout recommendation.

BGA Pitch 0.5 Mm

Pitch measures center-to-center distance, not the free channel between solder lands. For the example, pitch is 0.50 mm, BGA copper land diameter is 0.28 mm and the chosen offset via land diameter is 0.30 mm. Assume a 0.09 mm copper spacing requirement and a 0.09 mm escape trace, before checking package-specific mask, registration and process rules.

Input	Teaching value
Ball grid pitch	0.50 mm
BGA copper land	0.28 mm diameter
Offset via land	0.30 mm diameter
Trace and spacing	0.09 mm each

Those dimensions are geometry inputs, not recommendations. Use the manufacturer’s actual land pattern and the fabricator’s approved design limits.

Dogbone Fanout BGA

For a via centered in the square between four balls, the center distance to each surrounding land is pitch ÷ √2. At 0.50 mm pitch, that distance is about 0.354 mm. Subtract the 0.140 mm solder-land radius and the 0.150 mm via-land radius. The resulting nominal copper gap to a different-net neighbor is about 0.064 mm.

That is below the hypothetical 0.09 mm clearance. The same-net connection to the chosen pad is allowed, but the adjacent nets still need clearance. If you move the via toward one pad, recheck all other neighbors and the neck trace rather than assuming the shift fixes the entire cell.

BGA Escape Routing

Check the straight escape channel independently. Two 0.28 mm lands on a 0.50 mm row leave 0.22 mm between their edges. One 0.09 mm trace plus two 0.09 mm gaps needs 0.27 mm, so this route also fails on that layer. Moving the offset via into the pad does not make that between-land channel wider.

Decide where signals actually leave the footprint. A blind via can move a net to a different layer, but that layer has its own plane openings, land sizes and routing congestion. Evaluate representative corner and interior pins in the same model before assigning a via technology to the whole package.

Fine traces escaping from a BGA land pattern on a PCB — Check the escape channels separately from the via-to-pad clearance. Illustrative rendering; not a production or test record.

Via in Pad Filled and Capped

If the solderable land contains a through via, specify the agreed fill, cap and surface condition, not just “via in pad.” The finished surface should meet the assembly requirements for the particular footprint. An open or merely tented hole is not equivalent to a qualified filled and plated-over land.

Check the Best Technology VIPPO process guide for construction and inspection details. On the drawing, identify which pad groups need the process and the evidence that will show the finished structure is correct.

Via in Pad Solder Wicking

Open vias in a solder land can draw solder away during reflow. A feature that passes copper clearance can therefore still fail assembly. Ask the assembler to review the land, solder mask, paste and via treatment together. Check whether the available inspection method can detect the relevant joint or via issue.

If only the inner balls need via-in-pad, keep the simpler offset fanout on the outer rows if it passes the checks. Document the two structures separately so the shop does not assume they share the same treatment.

PCB Via Aspect Ratio Calculator

Aspect ratio depends on drilled depth and the diameter definition used by the process owner. For example, a 1.00 mm through depth and a 0.20 mm drilled diameter give 5:1 under that simple convention. Do not use the finished hole in that calculation if the qualified process specifies drilled diameter.

Use the actual layer-to-layer depth and approved diameter for a blind microvia. A through-hole ratio does not predict blind-via landing, dielectric clearance or stacked-via reliability. Confirm the proposed structure with the fabricator before treating it as a viable escape option.

BGA Fanout Guidelines

Release the fanout when the selected package lands, copper and mask rules, via structure and complete layer escape all pass. Verify at least one representative crowded cell, including nonconnected neighbors, and inspect the first article using the evidence specified for the chosen structure.

In the example, the offset via and straight channel both fail. First test a supplier-approved smaller offset geometry or a different routing approach. If neither works, qualify a via-in-pad stackup, verify the receiving layers, and rerun assembly and signal checks before release.

Frequently Asked Questions

Is via in pad required for every 0.5 mm BGA?

No. Pitch alone does not determine the fanout. Land diameters, trace spacing, ball assignment, approved via geometry and stackup all matter. Try the package manufacturer’s recommended land pattern and run the two clearance checks before deciding whether a higher-density fabrication process is necessary.

Can I simply make the BGA pad smaller to fit the dogbone?

Do not shrink a solder land solely to make routing easier. First check the exact package’s recommended footprint, the assembler’s process and the mask design. Changing the pad changes the solder-joint geometry. Consider a different layer escape or qualified via structure if the recommended land does not fit.

Is the via land diameter the same as the drill diameter?

No. The via land is the copper area around the hole. Its outer diameter controls spacing to adjacent copper. The hole diameter and its definition matter for fabrication and aspect ratio. Use the actual land dimensions for the geometric check and the approved drill data for process review.

Can I put dogbones on the outer rows and via in pad inside?

Yes, when each structure fits its own geometry, assembly and electrical constraints. Check that the outer rows still leave escape channels for the signals that need them. Identify which vias are filled and capped so the fabrication drawing and the released drill data remain unambiguous.

Does solder mask prevent solder wicking into a pad via?

A solder mask cover alone is not a substitute for a specified solderable filled and capped surface. Mask registration and opening geometry matter. Use the approved via construction for the assembly and ask the assembler how it will check joints when the via sits inside the solder land.

Will a blind microvia always eliminate an extra routing layer?

No. It changes where a signal can leave the pad. The receiving layer must still have room for the via lands, traces and reference structure. Test a real net assignment and routing pattern before changing the layer count or estimating the savings from an HDI process.

How should I handle a clearance result close to the limit?

Keep the full precision of the geometry and compare it with the fabrication design rules, including the agreed tolerances. Rounding a marginal gap up is not a design fix. Ask for a manufacturing review of a representative cell and include its pad, mask and drill data.

What should I send for a BGA fanout review?

Provide the exact package and land-pattern drawing, routed footprint, net assignments, layer stack, via definitions, and trace and spacing requirements. Identify which pins are difficult to escape and which via-in-pad areas need inspection. This makes it possible to compare real options instead of guessing from the pitch.

References

Discuss Your PCB Requirements

For a Best Technology fabrication review, send the BGA land pattern, proposed via structures and a representative fanout cell to sales@bestpcbs.com. Include the layer stack and the clearance that fails.

Tags: BGA Escape Clearance, BGA Fanout Geometry, Capped Via in Pad, Dogbone Fanout
Posted in bestpcb | No Comments »

Near-Field Probes: Trace PCB EMI to the Cable

November 10th, 2026

A near-field probe helps find where a PCB generates RF noise. It cannot tell you by itself which part of the product radiates enough to fail an emissions test. Start with the troublesome frequency, find the same signature on the board and on the cables, then repeat the system measurement after one controlled change.

Small magnetic loop probe above a populated PCB — A loop probe helps localize a board-level noise source. Illustrative rendering; not a production or test record.

EMI Troubleshooting

Write down the failure frequency and the exact operating mode before scanning. In this hypothetical example, a 72 MHz peak is present in a repeatable emissions setup while a controller is under load. The regulator switches at about 2 MHz, so the peak could be its 36th harmonic. That arithmetic suggests where to look, but another circuit can generate the same frequency.

Capture the product off and on, then document the supply, load, enclosure and cable routing. If the peak is present with the unit off, investigate the ambient signal before trying to fix the board.

Near-Field Probes

Choose the probe for the question. An H-field loop locates magnetic coupling associated with high-frequency current paths. An E-field probe helps find areas with rapidly changing voltage. A clamp-on RF current probe is a separate tool for tracing current on a cable.

Tool	What to look for	Keep fixed in A/B
H-field loop	Current-related board hot spots	Loop angle and height
E-field probe	Strong electric-field regions	Tip distance and position
RF current clamp	Cable current at suspect frequency	Cable routing and clamp location

The largest displayed reading from one probe is not directly comparable with a reading from another probe. Their responses and coupling differ.

Near-Field H Field Probe

Use a larger H-field loop for the first sweep and a smaller one to separate nearby candidates. Rotate the loop and compare at a consistent height. A null at one angle does not show that the circuit is quiet; it can just mean the magnetic field is not passing through the loop.

Once you find a repeatable peak, mark the probe point and use a nonconductive support to keep its height and angle fixed. Use noncontact scanning in a safe setup; do not touch energized conductors or defeat guards.

Near-Field Probe Spectrum Analyzer

Set a span wide enough to recognize the harmonic family, then narrow the display around the failure frequency. Record the center and span, resolution bandwidth, detector, attenuation, gain and cable. Keep these settings identical for before-and-after traces. Changes to the analyzer can look like changes to the product.

If a preamplifier improves sensitivity, also check overload. An apparent peak that disappears when input attenuation is increased may be an instrument artifact. Keep a baseline with the probe in its final position before testing any change.

Switching Regulator EMI

Correlate the peak with the regulator by using an approved operating-mode change. If the fundamental moves from 2.00 MHz to 1.95 MHz in the example, its 36th harmonic moves from 72.0 MHz to 70.2 MHz. A matching shift at the board and in the repeatable system measurement is stronger evidence than one matching frequency.

Hold the board revision and all other settings fixed when possible. If the frequency cannot be changed, compare valid load or enable states and record what else changes with them. A regulator shutoff that also stops the rest of the board cannot isolate the regulator by itself.

Common Mode Current Probe

Clamp around the complete cable bundle to look for net common-mode current. With a forward and return conductor inside the same aperture, equal and opposite currents ideally cancel. Clamping only one conductor measures a different quantity and can make normal differential current look like the suspected path.

Check multiple repeatable positions and then mark the one used for comparison. Keep the cable length and route fixed. Apply one approved reversible path change and check whether both the cable-current peak and the system peak move. For absolute current, use the probe’s transfer impedance and calibration; relative comparison can use a fixed setup.

Clamp-style RF current probe around a cable on an electronics bench — Use the cable measurement to check whether the same noise signature leaves the board. Illustrative rendering; not a production or test record.

Near-Field vs Far Field

A near-field scan identifies local sources and coupling clues; a radiated test measures the complete product at a defined antenna geometry. The strongest local source may be well contained, while a smaller one couples effectively onto a cable or enclosure seam.

Observation	Next step
Board peak only	Check other sources and coupling paths
Board and cable peaks track	Test one reversible cable-path change
Cable peak drops but system does not	Check other cables, seams or the setup
All three track	Repeat the fix in the final configuration

If a seam becomes the likely path, consult the board-level shielding guide. Do not select a new shield solely because the probe reading above the circuit is high.

EMI Pre-Compliance Testing

Use a bench comparison to decide whether a change deserves a formal retest. Repeat the original setup with the final enclosure, representative harness and required operating modes. Record baseline and changed traces and repeat the comparison to distinguish the change from normal setup scatter.

A drop at the fixed probe is not the release criterion. Use the applicable radiated or conducted test, detector, geometry and product limit for acceptance. Retain the configuration and evidence so the production revision can be checked against the design that passed.

Frequently Asked Questions

Can I use a near-field probe with an oscilloscope instead of an analyzer?

Yes, if its bandwidth, sensitivity and available frequency-domain tools suit the signal. Some scopes help correlate a spectrum with time-domain activity. Check the probe and input termination, avoid overload and keep acquisition settings fixed. A scope trace at the bench is not a regulatory measurement.

Why is the probe reading much higher when I tilt it?

The loop responds to magnetic flux through its area, which changes with orientation. Tilting can also alter the distance from the board. Scan several angles to locate a source, but fix the angle and height when you compare baseline and modified hardware.

Is the strongest near-field peak always the emission failure?

No. Radiation depends on the source, coupling path and structure that radiates. A strong local field may never reach the antenna efficiently. Compare the failure frequency and changes at the board, cable and system levels before choosing which component or layout to modify.

What if the spectrum changes when I move the cable?

Cable placement may change coupling or radiation, which is useful evidence but also a source of measurement variation. Mark the baseline route and clamp position, then repeat one deliberate routing change. Do not compare two board revisions with different cable positions and attribute the entire difference to the PCB.

Do I need a calibrated probe to compare two revisions?

A fixed relative comparison can be useful without absolute calibration if the probe, geometry, gain and operating conditions remain unchanged. Calibration and specified corrections matter when reporting absolute field or cable current. Record the setup so another engineer can reproduce the comparison.

Can I try a clip-on ferrite during the diagnosis?

A suitable temporary ferrite can help test whether cable common-mode current contributes, when used safely within the approved bench setup. Its behavior depends on material, frequency and placement. Compare cable and system results before considering a permanent filter, and revalidate the final design.

How can I distinguish a clock harmonic from a switching harmonic?

List their fundamentals and expected multiples, then vary one approved mode at a time. Look for the corresponding frequency shift or a time-domain correlation. If the candidates overlap and cannot be varied independently, treat the attribution as unresolved and take another measurement rather than naming a source.

Does an EMI pre-compliance improvement prove the board now passes?

No. A repeatable bench reduction supports the decision to retest. Final acceptance depends on the applicable method, limits, operating modes, enclosure and harness configuration. A local probe or quick bench antenna measurement cannot substitute for the required whole-product test under the specified conditions.

References

Discuss Your PCB Requirements

For a Best Technology PCB fabrication review, send your stackup, copper layout and the suspected coupling region to sales@bestpcbs.com. Include the test configuration and failure frequency so the drawing review addresses the right part of the board.

Tags: Cable Common Mode, EMC Troubleshooting, Near-Field Probing, Switching Regulator EMI
Posted in bestpcb | No Comments »

Cookie	Duration	Description
cookielawinfo-checkbox-analytics	11 months	This cookie is set by GDPR Cookie Consent plugin. The cookie is used to store the user consent for the cookies in the category "Analytics".
cookielawinfo-checkbox-functional	11 months	The cookie is set by GDPR cookie consent to record the user consent for the cookies in the category "Functional".
cookielawinfo-checkbox-necessary	11 months	This cookie is set by GDPR Cookie Consent plugin. The cookies is used to store the user consent for the cookies in the category "Necessary".
cookielawinfo-checkbox-others	11 months	This cookie is set by GDPR Cookie Consent plugin. The cookie is used to store the user consent for the cookies in the category "Other.
cookielawinfo-checkbox-performance	11 months	This cookie is set by GDPR Cookie Consent plugin. The cookie is used to store the user consent for the cookies in the category "Performance".
viewed_cookie_policy	11 months	The cookie is set by the GDPR Cookie Consent plugin and is used to store whether or not user has consented to the use of cookies. It does not store any personal data.