LED Thermal Transient Test: Is the Aluminum PCB at Fault?

November 13th, 2026

If an LED runs too hot on an aluminum PCB, change the board-to-heatsink interface while keeping the board, LED, and test power the same. Compare the junction-temperature response. If the response changes, the interface is a useful place to investigate before ordering a different substrate. If it does not, first check test sensitivity and repeatability; two matching curves do not prove the board is at fault.

Consider a hypothetical industrial inspection lamp: a new aluminum-core PCB and LED meet the electrical requirements, but the estimated junction temperature exceeds the design target in the closed housing. The team must decide whether to improve the board or correct its contact with the heatsink. A controlled thermal transient test can narrow that decision without treating the heatsink temperature as the junction temperature.

Round aluminum-core LED board on a finned black heatsink — An aluminum-core LED board and heatsink. Illustrative setup, not a measured sample.

Thermal Transient Testing: Start With the Heat Path

A thermal transient is the temperature change after heating power changes. In this lamp, heat flows mainly from the LED junction through the package and solder joint, then through the board, interface material and heatsink. Some heat also leaves by other paths. Measuring how the junction cools after power is reduced gives more information than a single final temperature.

Draw the suspected main path before testing. Mark where the junction temperature is inferred, where a thermocouple can go, and which interface can be changed without disturbing the rest. If the module has several powered LEDs, hold their operating states fixed or measure them separately. Neighbor heating can otherwise look like a change in the board under test.

LED Junction Temperature Measurement: Choose the Right Reference

Use a calibrated forward-voltage method when you need the junction cooling curve. Establish the relationship between forward voltage and temperature at a low sensing current for the device or qualified sample group. After the heating phase, switch to the sensing current and record voltage versus time. Log the switching delay: the earliest part of a fast transient can be obscured by electrical settling.

A thermocouple at the manufacturer-defined solder point serves a different purpose. It can support a steady-state junction estimate using the exact datasheet thermal parameter and power convention. It does not capture the fast junction transient. A temperature taken on the shiny aluminum back or heat sink is farther away and cannot be substituted for the specified point. For probe placement, see the Cree LED solder-point temperature note.

LED Thermal Resistance: Check the Endpoints and Power Basis

Thermal resistance in K/W is a temperature difference divided by the power used by the stated method. The endpoints matter: junction-to-solder-point is not junction-to-ambient. For heat-flow calculations, heat from the LED is electrical input minus emitted optical power. Some manufacturer data instead uses an electrical-input convention; pair the power term with the definition in the same datasheet or test report.

Report field	What to check	Why it matters
Temperature endpoints	Junction, solder point, case or ambient	Different endpoints include different parts of the heat path.
Power basis	Electrical input or heat after accounting for light	The denominator must match the thermal resistance convention.
Mounting and boundary conditions	Board construction, interface, clamping, airflow	Assembly values do not transfer unchanged to another fixture.
Acquisition and repeatability	Sense current, delay, thermal baseline, run-to-run spread	Small differences can be measurement artifacts.

Thermal Resistance vs. Thermal Impedance

Use steady thermal resistance for an equilibrium temperature rise at fixed power and boundary conditions. Use transient thermal impedance, Z_th(t), for the time-dependent response to a defined heating step. For an appropriate linear approximation, the rise after a heat step is the step power multiplied by Z_th(t). The curve approaches the steady resistance if the same thermal endpoints and conditions apply.

That distinction changes the test. A long continuous run checks the lamp’s final temperature in its enclosure. A pulse may end before the full assembly warms; using only average power can hide junction peaks. Conversely, a single-pulse curve starting cold does not represent repetitive pulses starting from a warm baseline. Validate the actual waveform and operating state.

Transient Thermal Impedance Curve: What a Split Can Tell You

Run the same LED board twice with two controlled interface conditions. Keep the heatsink, power, sensor calibration and ambient fixed; document each mount. Compare repeat runs before comparing the two conditions. If early responses agree within repeatability but later responses differ, the changed boundary affected the later response. This supports investigating the interface or related heat path. It does not make every bend in a curve the location of a named layer.

In a hypothetical steady-state comparison, both runs dissipate 4.0 W of LED heat. With the existing mount the late impedance approaches 3.0 K/W; with the comparison mount it approaches 2.5 K/W. The difference is 0.5 K/W, equivalent to a 2 °C steady junction-rise difference at the same heat load. If repeat runs vary by roughly that much, the experiment cannot separate the mounts confidently. These are illustrative values, not a measurement or a product limit.

Two aluminum-core LED boards with samples of thermal interface pads — For a mount comparison, document the interface material, its installed thickness and the clamp condition. Illustrative components.

Thermal Interface Material: Change One Thing at a Time

Compare a production mount with a controlled reference mount on the same board first. Differences in compressed thickness, wetting, flatness and clamp load can outweigh a catalog conductivity figure. Do not treat a grease reference as a drop-in production substitute: the design may require electrical isolation, gap accommodation, or mechanical retention that the reference cannot provide.

Controlled comparison	Signal to look for	Next decision
Same board, different interface	Repeatable change larger than remounting spread	Investigate interface, clamp and flatness before changing the PCB.
Same interface and package, two board constructions	Consistent difference after controlling the solder attach and mount	Review dielectric thickness, construction and spreading before attributing the difference to the metal core.
Same assembly, different airflow	Late response changes with airflow	Check enclosure cooling and repeat in the intended operating orientation.

For the mechanical checks that precede this comparison, see the aluminum PCB enclosure and thermal pad gap guide.

Transient Thermal Impedance Measurement: Know the Limits of Layer Attribution

Use a qualified transient dual-interface method when the goal is a package-level thermal resistance. The method uses a controlled change at an interface and evaluates where two responses separate, under its specified assumptions. A structure function represents the distributed thermal response; it is not a cross-section image. Parallel heat paths, calibration errors and noisy early data can undermine a one-layer-per-feature interpretation.

For the lamp, a practical mount A/B test supports a redesign decision, but it is not automatically a JESD51-14 package characterization. If the interface comparison is inconclusive, keep it fixed and compare a second board construction with the same LED and documented solder attach. If that change is inconclusive too, check the baseline, power normalization and whether the instrument resolves the temperature difference you need to see.

LED Maximum Junction Temperature: Set the Release Limit Before Testing

Start from the exact LED’s datasheet and the product’s lifetime and optical requirements. An absolute maximum is not a normal target. Agree on an operating ceiling that leaves margin for ambient variation, assembly spread and measurement uncertainty. Then define the duty cycle, orientation, enclosure, warm-up condition and worst-case neighboring heat load for the acceptance run.

For example, if the lamp’s engineering ceiling is a hypothetical 95 °C and the corrected build estimates 94 °C with ±3 °C measurement uncertainty, the result cannot demonstrate compliance with a conservative upper-bound rule. Improve the thermal margin or the measurement before release. Repeat on production-representative assemblies and record the actual stackup, interface condition and acceptance calculation.

Frequently Asked Questions

Does a cool heatsink mean the LED is safe?

No. A high resistance upstream can leave the heatsink cool while the junction runs hot. Measure or estimate the junction using the specified temperature reference.

Can a thermal camera measure LED junction temperature?

It observes accessible surfaces, not the buried junction. Surface emissivity and reflections also affect a reading, especially on bare metal.

Do I always subtract optical power from the electrical input?

Subtract it when calculating heat power for a heat-based method. When using a vendor thermal value, first check whether it was defined with heat power or electrical input.

Does a larger aluminum core always improve the curve?

No. The bottleneck might be the dielectric, solder joint, mount or heatsink. Use controlled comparisons to see whether a board change affects the target condition.

Should I use grease instead of a thermal pad?

Not automatically. Compare installed behavior and keep the product’s isolation, mechanical and aging requirements. A lab reference interface need not be suitable for production.

Can I find the faulty layer from one transient trace?

Usually not. Use controlled changes, repeat runs and construction evidence; a bend alone is not proof of a particular layer.

What if the curves separate only near the end?

Check mounting or cooling changes and confirm the difference is larger than run-to-run spread. Late separation is useful evidence about the boundary condition, not a unique diagnosis.

Can I qualify the board with the housing open?

An open test can help isolate a cooling problem. Use the intended closed configuration for release if that is how the lamp operates.

References

Discuss an Aluminum PCB Review

If the comparison points to the board, send the LED part number, PCB stackup, mounting drawing, heat load and temperature traces to sales@bestpcbs.com. Best Technology can review the proposed board construction with those inputs; the final assembly still needs to pass its own thermal validation.

Tags: aluminum pcb, LED Thermal Testing, Metal Core PCB, Thermal Impedance
Posted in bestpcb | No Comments »

Oscilloscope Probe Loading: Is the Ringing on Your PCB?

November 13th, 2026

Oscilloscope probe loading occurs when the probe changes the signal at the point you are measuring. Before changing a PCB that appears to have clock ringing, repeat the capture at the same node with a shorter, appropriate ground connection and then compare a suitable lower-capacitance probe. A change in the waveform is evidence that the setup matters; it is not proof that the original PCB waveform was clean.

Consider a hypothetical low-voltage controller whose clock shows overshoot near the receiver. The task is to tell apart three possibilities: the circuit actually rings, the probe changes the circuit, or the measurement connection adds an artifact. Each calls for a different next step.

Oscilloscope probe resting beside an unpowered digital PCB — Illustrative probe and PCB. No connection or measured waveform is shown.

Oscilloscope Probe Loading Effect: What Changes?

A probe is an electrical load. Its resistance draws some current, and its capacitance draws additional current as the voltage changes. The connection to the reference node also has inductance. On a fast edge, the load can slow or reshape the actual node voltage, while the probe loop may introduce ringing in the displayed waveform.

Keep those effects separate. If connecting a second probe changes what a fixed reference probe sees, it supports the hypothesis that the circuit is being disturbed. If only the probe with a long ground connection shows strong ringing, the connection may be contributing an artifact. Neither result identifies every source of error; use the same signal event and comparable bandwidth for both captures.

Oscilloscope Probe Input Impedance: Check More Than Megohms

The resistance printed on a probe is not its complete impedance at high frequency. The input capacitance presents a lower impedance as frequency rises, so a nominally high-resistance probe can still load a fast or high-impedance node. Read the probe specifications at the tip and with the actual accessory, not just the oscilloscope’s front-panel input rating.

Check whether the probe expects a 1 MΩ or 50 Ω instrument input and whether the selected attenuation is supported. Connecting a scope’s 50 Ω input directly to a node that cannot drive that load changes the circuit. Use a suitable buffered or engineered measurement interface when the node cannot tolerate the proposed load.

Oscilloscope Probe Capacitance: A Worked Loading Estimate

In a hypothetical lumped circuit with a 50 Ω source resistance, 12 pF of added probe capacitance gives an RC time constant of 0.60 ns; 2 pF gives 0.10 ns. For an ideal voltage step into this first-order model, the respective 10–90% rise times due to that pole alone are about 1.32 ns and 0.22 ns. These are not actual probe specifications or measured PCB results.

Assumed tip capacitance	Calculated effect with 50 Ω
12 pF	50 × 12 pF = 0.60 ns; 2.197 × RC ≈ 1.32 ns.
2 pF	50 × 2 pF = 0.10 ns; 2.197 × RC ≈ 0.22 ns.

Use the estimate to screen for sensitivity, not to subtract time from a real waveform. The true driver has a finite edge, and PCB traces and probe leads may behave as distributed structures. This RC model cannot predict ground-loop ringing or diagnose reflections. Tektronix’s probe-loading note illustrates why capacitance can matter even when resistance looks high.

Oscilloscope Probe Compensation: Check the Instrument First

For a compatible adjustable passive probe, use the scope’s compensation output and the probe maker’s procedure. Under- or over-compensation can round the edge or add a leading bump. Correct that behavior before comparing board captures.

Compensation aligns the probe with the instrument input; it does not remove capacitance from the circuit or repair an unsuitable ground lead. Repeat the check after changing channels or attenuation when the equipment instructions call for it.

Oscilloscope Probe Ground Spring: Shorten the Loop

On a low-voltage ground-referenced PCB where the connection is safe, use a short spring or other recommended local ground connection. Compare the same clock pad with the long lead and short connection without changing the stimulus. If ringing amplitude or frequency shifts substantially, suspect the measurement loop and investigate before touching the board design.

Bench-scope ground clips are commonly earth referenced. Do not connect one to a switching node, floating rail or isolated return that must not be grounded; never defeat protective earth. Choose a suitably rated differential or isolated measurement arrangement when needed. See the Tektronix probe primer for why the ground lead and tip capacitance can form a resonant circuit.

Two oscilloscope probe heads and accessories beside an unpowered PCB coupon — Illustrative probe options. Check the specifications for the exact probe, tip and connection.

Active vs Passive Oscilloscope Probes

Choose the probe by allowed loading, bandwidth, amplitude and reference conditions, not by the active or passive label alone. A low-capacitance active probe can preserve a fast node better, but an active probe may have a narrower input range or tighter common-mode limits. A compatible low-capacitance passive probe can be adequate on the same node if its loading is acceptable.

Option	What to verify
Passive voltage probe	Tip capacitance, compensation, safe ground and short connection.
Active single-ended probe	Tip loading, dynamic range, offset and local reference compatibility.
Differential probe	Input and common-mode ranges, bandwidth and balanced connection.

Oscilloscope Probe Bandwidth: Compare Like With Like

Use the bandwidth of the complete scope, probe and connection. A lower bandwidth limit can make overshoot or fast ringing look smaller by filtering it. That may help when the measurement specification calls for a limited band; it does not show that the PCB physically improved.

Record the settings, sampling, probe accessory and approximate node reference. Compare the suspected ringing with the same bandwidth setting where possible. If one probe cannot cover the required band, do not accept a cleaner plot from it as proof of the fix.

Oscilloscope Probe Noise: Prove the PCB Fix Separately

If the suspected ringing remains under a validated setup, compare the driver and receiver relative to appropriate local references, with the intended load connected. Persistent ringing or incorrect receiver timing can justify reviewing termination, return geometry or the test pad’s own branch. The BestPCBs eye diagram guide covers related receiver-level evidence.

Change one board variable only after fixing the measurement method. Then repeat the same observation and check functional operation against the receiver’s actual limits. Save before-and-after captures with the point, probe, ground, bandwidth and board revision. A quieter plot alone is not a pass if the receiver still violates its timing or voltage requirements.

Frequently Asked Questions

Does 10× always mean low capacitance?

No. Check the specifications for the probe model, switch setting and accessory. Attenuation alone does not specify tip loading.

Can two probes on the same pad change the result?

Yes. Both contribute load, and ground connections can introduce additional paths. Use the second probe only as a controlled check and document what changed.

Should I probe the source or the receiver?

Start where the decision is made. For receiver margin, observe the receiver relative to its reference; compare the driver separately to investigate the source of the disturbance.

Can a solder-in probe tip solve every ringing problem?

No. It can shorten the connection but still has loading, bandwidth and voltage limits. It cannot fix a real board discontinuity.

Does a high sample rate replace probe bandwidth?

No. Sampling a filtered or distorted signal more often does not recover information lost in the analog measurement path.

Can the test pad itself cause reflections?

Yes. A branch to a test pad can become a discontinuity on a fast net. Include the pad and branch in the interconnect review, even if no probe is attached.

Does changing the vertical scale correct probe loading?

No. It changes how the acquired waveform is displayed or acquired, not the electrical impedance presented by the probe at the node.

What if the board only fails when I attach the probe?

Treat the probe as a possible cause. Compare supported lower-loading access and monitor function without the suspect connection before concluding the board fails on its own.

Prepare the PCB Measurement Review

For a Best Technology PCB fabrication discussion, send the board revision, stackup and test-access geometry to sales@bestpcbs.com. Include any controlled coupon requirements and keep the scope setup and receiver acceptance conditions with the design validation record.

Tags: clock ringing, oscilloscope probe loading, PCB signal integrity, probe capacitance
Posted in bestpcb | No Comments »

Ceramic Substrate Partial Discharge: Read the Test Report

November 13th, 2026

A ceramic substrate can pass a dielectric withstand test and still show partial discharge under a separate test. The withstand result answers whether the sample survived the specified exposure. The partial discharge report answers whether localized discharges were detected under a defined waveform, electrode arrangement and detection criterion. Check those conditions before comparing any two numbers.

Consider a hypothetical inverter module. A supplier offers a direct-bonded copper (DBC) ceramic coupon report, while the design team needs evidence for the finished, encapsulated module. The same ceramic grade is used in both. Can the team accept the coupon report? Use it to screen the substrate construction, but do not use it to qualify the finished module without evidence that the test object and conditions represent the required insulation system.

Copper islands on light ceramic substrate samples — Illustrative copper-clad ceramic samples. No test result or verified material grade is shown.

Partial Discharge Testing on Ceramic Substrates

Partial discharge is a localized electrical discharge that bridges only part of the insulation between conductors. The insulation can remain intact enough to prevent a complete breakdown during the test. A partial discharge (PD) measurement asks whether the configured instrument detects discharge activity from the test object above an agreed criterion.

For the inverter, first name the insulation path: top copper to back copper or baseplate, or between two top-side copper islands. A test across one of these paths does not automatically cover the other. Record which electrodes are driven, returned, connected together or left open. For context on substrate construction, see the DBC ceramic substrate overview.

Partial Discharge Causes at the Copper Edge

Look for local field concentration and interfaces, not just ceramic thickness. Near a copper edge, metal, ceramic and a surrounding medium such as air or gel can meet at a triple junction. Edge shape, opposing copper layout and the surrounding dielectric can change the electric field there. Voids in encapsulation or defects elsewhere can produce similar electrical indications, so a report should distinguish suspected locations from confirmed ones.

A published study on DBC bottom copper examined how that layer affects discharge performance in power modules. Its implication for procurement is to compare the actual copper geometry and test configuration, not to copy an edge dimension or inception voltage into another drawing.

Partial Discharge vs Hipot

Ask for separate evidence when the specification requires both. A hipot or withstand test evaluates survival at the stated voltage and duration under its acceptance conditions. A charge-based PD test measures discharge-related pulses, typically reported as apparent charge, under its own conditions. The two methods can be combined in a defined program, but a simple withstand pass is not a PD result.

Evidence	What it answers and what it does not
Withstand report	Did the sample meet the stated withstand criteria? It does not quantify PD unless the test also measured and reported it.
Charge-based PD report	What activity was detected at stated conditions? It does not establish unrestricted working voltage or service life.
Material dielectric strength	How did a material specimen perform under its breakdown method? It does not qualify the module’s edges, interfaces or encapsulation.

Partial Discharge Measurement Unit: What Does pC Mean?

A picocoulomb (pC) is 10⁻¹² coulomb. In a charge-based report it typically expresses apparent charge, a calibrated equivalent at the terminals, not the actual charge moved at an internal defect. Ask for the specified statistic, the measurement sensitivity, and the observed background under the stated test configuration.

A line that says “no PD detected” is only meaningful against a method, a voltage and a detection criterion. If the background prevents reliable discrimination at the agreed level, the result is inconclusive for that requirement, not a pass. A reading from a different sensor or method is not automatically interchangeable with a charge-based value.

Partial Discharge Inception and Extinction Voltage

Inception voltage (PDIV) identifies the voltage on the rising part of the agreed test sequence where activity meets the specified inception criterion. Extinction voltage (PDEV) refers to the falling part and the specified extinction criterion. Record how each was determined and whether the voltage is RMS, peak or DC. Neither value alone sets the continuous voltage rating.

For unit checking only, a 1.00 kV RMS sinusoid has a peak of approximately 1.41 kV because the peak is RMS × √2. That is not a suggested test level. The conversion does not make a sine-wave result comparable to a pulse or DC result, and it does not change the test object or its field distribution.

Partial Discharge Test Voltage: Match the Waveform and Object

Read the waveform and frequency before comparing values. IEC 60270:2025 covers charge-based measurements with AC up to 500 Hz or DC within its scope. IEC TS 61934:2024 addresses offline electrical measurements under repetitive impulses from power electronics; the two documents do not define interchangeable measurement methods.

The qualified lab and product requirements should determine the actual procedure, voltage sequence and limits. Do not improvise a high-voltage setup from a report. For the inverter, document whether the object was a bare coupon, metallized substrate or complete module and whether the result was measured before or after relevant conditioning. A bare sample tested in air does not include all of the interfaces found in a gel-filled module.

Unpowered copper-clad ceramic module sample beside a laboratory enclosure — Illustrative sample context. It does not show an energized fixture or prescribe a test setup.

Partial Discharge Test Results: Separate Noise From Evidence

Ask what the lab did to separate discharge from the fixture, leads and external interference. A pattern may help form a hypothesis but does not by itself locate the defect. Have the lab document the background, calibration or sensitivity check appropriate to the method, and any repeats or reference measurements used to support the interpretation.

Do not reject the ceramic merely because one pulse appeared, and do not discard a repeatable signal as noise without a documented basis. If activity changes with fixture configuration rather than with the sample, investigate that difference before comparing lots. If the signal tracks a production geometry change across comparable samples, narrow the investigation to the relevant insulation path and confirm the result.

Partial Discharge Test Report: Decide What Is Fit for Release

Compare two reports only after the test object, insulation path, waveform and detection rules match the decision you need to make. For the inverter, request finished-module evidence when that is the specified acceptance object. Use the coupon data for material or process screening, with its limitations recorded.

Report field	What to verify
Object and construction	Drawing revision, ceramic grade and thickness, copper geometry, and encapsulation state.
Insulation path	Electrode identities and any connection to the back copper or baseplate.
Exposure	Waveform, frequency or pulse definition, voltage units, sequence and conditioning.
Detection and decision	Method, calibration or sensitivity, background, result, applicable acceptance criterion and sample IDs.

Hold the decision if the report cannot identify the production construction or cannot resolve the specified criterion above background. Agree on a repeat or a representative sample rather than adjusting a vendor result with a thickness ratio.

Frequently Asked Questions

Does a thicker ceramic always give a higher inception voltage?

No. Thickness changes one part of the field distribution. The edges, opposing metallization, surrounding dielectric and test connections can determine where activity starts. Compare production-intent geometries under the same method.

Can a larger copper setback replace a PD test?

No. A setback can change the local field and is worth reviewing, but a drawing dimension alone does not account for all interfaces, materials and process variation.

Is a low apparent-charge value proof that a void is small?

No. Apparent charge depends on how the discharge couples to the measurement terminals. Do not infer void dimensions from that value alone.

Can I compare DBC and AMB reports from different suppliers?

Only for decisions the evidence actually supports. Request comparable objects, electrode connections, conditioning, waveforms and acceptance criteria before attributing differences to the bonding process.

Does PD always lead immediately to breakdown?

No. Activity can occur without a complete conductive path at the time of the test. The potential effect on insulation depends on the materials, repetition and service conditions.

Can a PD report identify which lot a module came from?

Only if the test record links the sample ID to the relevant lot and drawing revision. A graph with no specimen identifier is not lot evidence.

Is there one pC limit for all ceramic substrates?

No. Use the product requirement and agreed test method. A threshold from a different type of equipment or sample is not a default limit for an inverter module.

When should I ask for a conditioned sample?

When the qualification plan requires evidence after a specified environmental or production exposure. Record the conditioning sequence and do not compare it directly with an unconditioned sample without noting the difference.

Prepare the Ceramic Substrate Review

For a Best Technology drawing and fabrication review, send the ceramic and copper stack, geometry, insulation paths and agreed evidence requirements to sales@bestpcbs.com. Confirm the scope of any requested test separately; a substrate fabrication review does not qualify the finished power module.

Tags: ceramic substrate, dbc substrate, insulation testing, partial discharge
Posted in bestpcb | No Comments »

Remote Sense Power Supply Guide: Get the Load Voltage Right

November 13th, 2026

A remote sense power supply regulates the voltage at the point its feedback wires or PCB traces monitor, rather than only at the regulator output. Use remote sensing when the measured steady voltage drop to a critical load consumes its voltage budget and the regulator explicitly supports the connection. If the rail is only out of tolerance during fast load changes, first investigate the transient response instead of moving the feedback point.

Consider an FPGA board with a nominal 1.000 V core rail. The regulator output looks correct on the meter, but the voltage at the FPGA drops at high load. The decision is whether to move the sensing point, improve the copper path, or put regulation closer to the load. The example values below are hypothetical; use the actual device limits for acceptance.

FPGA-style circuit board with power inductors near a large logic package — Illustrative board layout, not a tested circuit or production sample.

Remote Sense Power Supply: What Voltage Is Controlled?

The feedback loop controls the difference between its designated sense points. In local sensing, those points are near the regulator output and return. In remote sensing, they represent the load supply and its return. The power path still carries load current; the separate feedback connections tell the regulator what voltage reaches the load.

Mark two node pairs on the schematic: regulator output and its nearby return, then load supply and its nearby return. Measure each pair at steady load. Measuring the load supply against regulator ground mixes two locations and can hide the voltage lost in the ground path. Texas Instruments’ PMIC remote-sense guide shows how the sensed voltage relates to the board connection.

PCB Trace Voltage Drop: Count the Supply and Return

In this teaching example, 6 A through 4 mΩ of supply copper and 2 mΩ of return copper produces a 36 mV round-trip DC drop. With 1.000 V at the source, the load sees about 0.964 V. If the design has allocated only 20 mV to distribution loss, local sensing alone misses that allowance by 16 mV.

Illustrative input	Value and consequence
Supply path	4 mΩ × 6 A = 24 mV drop
Return path	2 mΩ × 6 A = 12 mV drop
Combined path	6 mΩ; 36 mV drop and 216 mW of distribution loss at 6 A
Maximum path resistance for a 20 mV allowance	20 mV ÷ 6 A = 3.33 mΩ, before other margins

Use resistance at the relevant operating temperature, including vias, neck-downs and connectors in the current path. Remote sense can compensate voltage at one node pair, but it cannot remove the 216 mW dissipated in the example copper path. If heating or connector loss is already unacceptable, fix the path even if the regulator can compensate the voltage.

Remote Sense vs Local Sense: Choose the Feedback Point

Prefer local sensing if the load stays within budget across the operating range. Use supported remote sensing for a critical point when distribution drop is the limiting error. If multiple loads need tight regulation or the power path overheats, reduce its resistance or regulate closer to the load rather than raising the source voltage indefinitely.

Option	When to choose it and what to check
Local sense	Use if path loss fits the budget. Check DC and transient limits at the load.
Differential remote sense	Use for tighter DC accuracy at one point. Check source headroom, sense input limits, and other loads.
Better copper or local regulation	Use if heat, multiple loads or limited correction rule out remote sense. Check space, current and transient behavior.

In the example, local sense could meet the DC allowance if the path is reduced below 3.33 mΩ with sufficient margin. Remote sense could instead raise the source to roughly 1.036 V at 6 A to deliver 1.000 V to the FPGA, but that value is only an ideal steady-state estimate. An upstream branch on the same rail might then see close to the higher source voltage.

Differential Remote Sensing: Land Both Connections at the Load

Take the positive sense point from the intended load supply location and the negative sense point from its corresponding return. If the device exposes dedicated package sense pins, follow the device and regulator instructions for using them. A connection at a distant ground via can leave part of the return-path drop outside the loop.

The TPS7H4011 datasheet, section 9.3.3, illustrates a differential connection for an FPGA and accounts separately for resistance in the power and ground paths. This is an architecture example, not a recommendation to copy the pin connections onto another controller. Confirm which input connects directly to the load, which uses a divider, and where that divider returns.

Buck Converter Layout Guidelines for Sense Traces

Route the differential sense traces together through a quiet part of the board. Keep them away from the switch node, inductor and high-current switching loops, and follow the device’s feedback-component placement guidance. The sense traces are feedback inputs, not a controlled-impedance data link; adding a differential impedance constraint is not the main design task.

Mark the sense pickoffs separately from the force copper in the schematic and layout. Where practical, include accessible measurement points at the source and load, but do not add long stubs to the feedback pins just to probe them. At review, follow both paths on the actual board artwork, including layer transitions and shared reference copper.

Populated regulator board with inductors and disconnected test probes on a bench — Illustrative regulator bench setup. The probes are not connected and no measurement is shown.

Remote Sensing Compensation: Check Headroom and Fault Behavior

Check how much additional output voltage the exact regulator or supply can provide while meeting its limits. The source may reach a duty-cycle or output limit before the load voltage is restored. Check the feedback input range, maximum correction, overvoltage behavior, startup sequence, and any limits imposed by the source-side capacitors or nearby loads.

A removable connector makes the feedback path a fault concern as well as a routing concern. Determine from the device documentation what happens if either sense path opens, is reversed, or is present before the power path. Do not assume the controller falls back to local sense. For prototypes, verify the documented behavior with a controlled setup that protects the actual load; do not unplug feedback from a live production board to find out.

Buck Converter Feedback Loop Design With Remote Sense

Moving the sensing point can include more interconnect and load-side capacitance in the regulated path. The response then depends on the controller, board parasitics, local and remote output capacitors, and the specific compensation scheme. Do not add a filter or copy a capacitor value from another regulator unless the manufacturer supports the arrangement.

Check the permitted output capacitance and layout, then evaluate the loop by the manufacturer’s recommended method. A stable response with an electronic load at the regulator terminals does not prove stable regulation with the production load at the far end. For the FPGA example, keep the load-side decoupling and the real power/return connection in the validation setup.

Load Transient Response: Measure Both Ends Before Release

Measure the source and load node pairs under the same repeatable current step. Record the starting and ending current, slew rate, probe setup and operating conditions. A DC correction that reaches 1.000 V after settling can still leave an initial dip below the FPGA’s limit or overshoot after a rapid load release.

First verify steady voltage at minimum and maximum load. Then check startup, step-up, step-down and recovery at the expected operating limits. Use representative load capacitance and compare both source and load readings to their own limits. If the load shows an early dip but steady voltage is correct, investigate local decoupling and interconnect inductance; if both ends ring after moving the feedback point, review loop stability. See Analog Devices’ transient-testing guidance and the PCB target impedance guide for the related dynamic budget.

Frequently Asked Questions

Can a bench supply’s remote sense validate my onboard regulator?

It can help regulate the external power at the chosen bench-supply sense point. It does not demonstrate that the onboard regulator’s own feedback loop or local load transient response will pass.

Can I use one sense lead and the existing ground copper?

Only if the regulator supports that sensing topology and the return error is acceptable. A single-ended measurement does not automatically cancel voltage differences across current-carrying ground copper.

Can remote sense reduce heating in a PCB connector?

No. It can compensate voltage drop at the selected load while the connector still dissipates power. Evaluate connector current and temperature on their own.

Should I simply raise a locally sensed setpoint instead?

A fixed offset can correct the voltage at one load current but overcompensate at another. Compare the lowest and highest load voltages and check all branches before adopting a fixed offset.

What if two devices share the rail but need different voltage margins?

One feedback pair directly regulates one location. Measure both loads under their actual current combinations. Consider reducing path resistance or splitting the rail if the required voltage windows cannot both be maintained.

Will measuring against chassis ground give the right load voltage?

Not necessarily. Measure between the load’s supply and its intended local return using a suitable setup; chassis ground can be a different electrical point. Do not short an isolated or offset return with a grounded instrument lead.

Can I run the sense pair through a detachable connector?

Use the connector only when the regulator and system design account for contact sequencing, continuity faults and the resulting output behavior. A voltage pass with the connector fully seated is not a fault test.

What is the quickest way to tell DC loss from a fast transient?

Compare the two node pairs at settled loads, then record the same pairs across a current step. A difference that persists at steady current is distinct from a brief dip or ringing that recovers.

Prepare the Power Path for Fabrication Review

For a Best Technology fabrication review, send the board revision, stackup, current path and sense-point locations, copper requirements and any required test structures to sales@bestpcbs.com. Keep the regulator limits and load-side acceptance criteria with the electrical validation plan; a fabrication review does not qualify the regulator loop.

Tags: differential remote sensing, PCB Power Integrity, PCB trace voltage drop, remote sense power supply
Posted in bestpcb | No Comments »

Aluminum PCB Enclosure: Check the Thermal Pad Gap

November 13th, 2026

Open aluminum electronics enclosure with a populated board and a thermal interface pad — Illustrative rendering; not a production sample or measurement.

Choose a thermal gap pad for a PCB in an aluminum enclosure by checking the smallest and largest assembled gap. At one extreme the pad may not touch; at the other it may bend the board or overload the component. A higher conductivity rating cannot fix either problem.

Consider a hypothetical sealed industrial controller that transfers heat from a component to a machined aluminum boss through a compliant pad. The example shows how to convert the gap tolerance into a compression window, compare interface options, and decide what measurements are needed before releasing the assembly.

Aluminum PCB enclosure

An aluminum enclosure only helps cool a device when there is a usable heat path into the metal and from the metal to the environment. Start by marking the source, contact footprint, enclosure wall and exterior heat rejection. The enclosure and an aluminum-core PCB are different things; either may appear in the same assembly.

For the controller, the intended path is through the top of a component whose manufacturer allows that cooling arrangement. Check the drawing and applicable package guidance. If a component is designed to transfer most heat through an exposed underside pad, compare the board-to-case route rather than assuming the top case is a suitable contact.

PCB enclosure design guidelines

Define the gap between the actual mating surfaces with the PCB mounted on its production supports. Include component height, solder standoff, PCB position, boss location, relevant flatness and fastening tolerances. A dimension from the lid to the bare board is not the gap from the lid to the mounted component.

Input	How to define it	Why it changes the decision
Gap, mm	Smallest and largest local separation in the closed build.	Determines contact and compression.
Pad thickness, mm	Nominal thickness and supplier tolerance.	Determines free height and assembled deflection.
Pressure and load	Supplier compression curve, loaded area and approved force limits.	Controls stress on package, board and fasteners.
Temperature limits	Component and enclosure limits under the specified duty and ambient.	Defines the actual release condition.

Thermal pad thickness

With an illustrative 0.70–0.95 mm assembled gap and a 1.00 ± 0.05 mm free pad thickness, the least compression occurs with the thinnest pad at the largest gap. Here those dimensions are both 0.95 mm: there is no nominal squeeze in that worst-case combination. A build at the center of tolerance can look acceptable and still hide this failure.

Compare thickness options against both extremes and document the assumed tolerances. A nominal 1.20 mm pad with the same assumed ±0.05 mm thickness tolerance increases the minimum squeeze, but may increase load at the smallest gap. Do not choose it until the pressure and temperature evidence is available.

Thermal pad compression ratio

Compression ratio is (free thickness − assembled gap) divided by free thickness, expressed as a percentage when contact is achieved. For the 1.00 ± 0.05 mm example, the geometric envelope is 0% at 0.95 mm against a 0.95 mm gap and about 33% at 1.05 mm against a 0.70 mm gap.

For the 1.20 ± 0.05 mm option, the corresponding values are about 17% and 44%. These numbers are not recommended limits. Use the selected grade’s compression and loading data, and verify actual force and deflection if pad area or surface variation makes a uniform-pressure assumption unreliable. A metal stop or tighter tolerance may solve the problem more cleanly than another pad thickness.

Thermal gap pad on a machined aluminum contact surface beside feeler gauges — Illustrative rendering; not a production sample or measurement.

Thermal pad vs thermal paste

Use a compliant pad when the assembly needs to bridge a designed gap. Consider paste for a thin, mechanically controlled interface between suitable mating surfaces; do not assume paste will bridge the controller’s millimeter-scale tolerance stack. A change of interface type also changes the manufacturing and rework plan.

Option	Suitable condition	Verify before use
Gap pad	Variable gap with limited package or board load.	Compression window, contact area and pressure.
Thin paste interface	Close, controlled mating surfaces with defined clamping.	Application, bond line and service stability.
Revised boss or support	No pad can satisfy contact and load simultaneously.	Updated gap envelope and mechanical assembly fit.

Thermal interface resistance

Use conductivity to estimate the bulk material contribution, not the complete interface. A simplified uniform layer has resistance equal to compressed thickness divided by conductivity times area. Using 0.80 mm, a 20 × 20 mm contact area and 3.0 W/(m·K), the bulk estimate is about 0.67 K/W. Henkel lists 3.0 W/(m·K) for one named gap-pad grade; the thickness and area here are hypothetical.

Contact resistance at both surfaces, uneven pressure and lateral spreading are excluded. Compare measured or supplier-characterized interface resistance at representative thickness and pressure. Even if a thicker pad guarantees contact, the added bulk resistance or higher force can make it the wrong choice.

Enclosure thermal analysis

Use the full path to decide whether improving the interface will reduce the temperature that matters. The package, pad, housing and outside environment can each limit performance, with some heat leaving by parallel paths. A cold enclosure alongside a hot component is a reason to check contact; a hot enclosure may indicate the system cannot reject enough heat externally.

For the controller, log actual dissipation, orientation and surrounding conditions rather than extrapolating from one open-bench test. Compare a poor-contact build and a verified-contact build with the same power and enclosure. See the aluminum enclosure and PCB integration guide for the broader fit and grounding questions.

PCB thermal testing

Verify the installed pad and the assembled thermal result independently. Inspect contact coverage by a method approved for the materials and build, record assembly settings, and measure the relevant component and enclosure temperatures under the specified operating modes. If using infrared measurements, account for emissivity and avoid inferring a junction temperature directly from a shiny enclosure reading.

Release only when representative builds cover the gap and load extremes, and the closed product satisfies the agreed temperature and mechanical limits. Retest if the support, pad grade, boss height or tightening sequence changes. Keep the insulation and grounding requirements separate: a thermal result cannot establish electrical safety.

FAQ

Should the pad thickness equal the measured gap?

Not by default. At that nominal condition there may be little or no compression. Check both thickness and gap tolerances and apply the selected material’s recommended conditions.

Can two thin pads replace one thick pad?

Do not assume equivalence. A stacked interface adds another contact boundary and may shift during assembly. Test the intended construction and obtain approval before changing it.

Does a soft pad guarantee low board stress?

No. The load also depends on deflection, area and support geometry. A large pad at a high compression can still create enough force to bend the board.

Can mounting torque tell me the pad’s contact pressure?

Not reliably by itself. Fastener friction, stops, enclosure stiffness and the force paths matter. Use a validated mechanical model or measurement when load is critical.

Does pad color identify its conductivity?

No. Use the supplier’s exact grade and current data rather than judging by color or appearance. Keep the part and thickness identifiers on the assembly record.

Is every thermal pad an approved electrical insulator?

No. Check the actual dielectric data and the complete insulation construction under the applicable requirements. Do not credit thermal material as a safety barrier by default.

Can I approve a build using one temperature snapshot?

Only if the accepted test plan calls for that observation and covers the relevant conditions. Otherwise record warm-up, equilibrium or duty-cycle behavior and the measurement locations.

What should I send to the board supplier?

Provide the board drawing, component and enclosure stack, contact location, permitted flatness and supporting assembly details. Keep the approved pad and load criteria with the product records.

References

Discuss the board-to-enclosure interface

For a Best Technology PCB or assembly review, send the board stack, contact geometry and inspection requirements to sales@bestpcbs.com.

Tags: aluminum pcb, PCB enclosure, thermal management, thermal pads
Posted in bestpcb | No Comments »

EMI Shielding Failures in Small Medical Devices

November 13th, 2026

Open handheld instrument enclosure with a PCB and metal shield lid — Illustrative rendering; not a tested medical device or measurement record.

When EMI shielding fails in a compact medical device, first determine whether the disturbance bypasses the shield through a cable, leaks through a seam or enters the sensitive circuit by another path. A larger metal cover will not fix every mechanism. Compare one controlled change at a time and verify both the electromagnetic result and the device function.

Consider a hypothetical handheld monitor that behaves normally on its bench supply but occasionally produces a sensor error during immunity evaluation with its intended cable attached. The goal is to localize the coupling path, decide what to change and confirm the fix on the assembled device. This example is not a compliance procedure or a record of a tested product.

Board level shielding

Use a board shield to enclose a defined source or protect a defined victim. The can, its connection to the board reference and the return path underneath form one enclosure. A shield that covers a regulator while leaving the connector return outside the boundary may reduce a local field without changing the disturbance that reaches the sensor.

Mark three features on the layout: the suspected source, the sensitive circuit and each conductor crossing the shield boundary. Include flex tails and test leads. If the error occurs only with the external cable attached, investigate that path before changing the can. If a local source couples directly into the analog input, inspect where those circuits share geometry or return impedance.

PCB shield can

Choose a one-piece can or a removable lid according to the required RF continuity, assembly process and service access. A two-piece part can simplify inspection and rework, but the lid-to-frame interface becomes a separate contact to verify. A one-piece part still depends on how it is attached and on what passes underneath it.

Option	Use when	Verify on the build
One-piece board shield	The region does not need routine access.	Attachment, coplanarity and inspection of required joints.
Frame with removable lid	Parts must remain accessible during build or service.	Lid seating and repeatability after approved reassembly.
Conductive enclosure and gasket	The coupling path crosses a case seam or port.	Mating surfaces, contact continuity and the approved boundary design.

Use the chosen part’s drawing for footprint, flatness and height. After assembly, check that the lid does not contact tall components and that it seats with the actual board thickness and enclosure tolerances. Do not rely on a supplier shielding figure for the behavior of an assembled medical device.

Removable metal shield beside its PCB mounting frame — Illustrative rendering; not a tested medical device or measurement record.

EMI gasket

A conductive gasket is useful only when it provides a repeatable contact across the seam it is intended to close. Inspect the actual mating surfaces for paint, gaps, pressure variation and housing distortion. A gasket that touches at the screws but loses contact between them can leave an RF leakage path even if a continuity meter beeps.

On the monitor, compare the baseline with a reversible engineering change applied to one suspected seam. Keep cable position and operating mode unchanged. Use only changes approved for the test unit: a diagnostic bond must not bypass patient isolation, protective barriers or other safety features. If the improvement depends on hand pressure, treat that as a clue about contact repeatability rather than a production fix.

Common mode current

Look for cable common-mode current when a change in cable orientation, accessory or connector bond shifts the response more than a change to the can. A clamp around all conductors in a cable can help compare net current under repeatable conditions. The measurement is a diagnostic proxy; it does not by itself establish how much of the disturbance reaches a sensitive node.

Compare only configurations allowed by the test plan. For the example monitor, log whether the cable is attached, its routing and termination, and the operating mode. If the error follows a cable change, examine the port protection and return path. Do not copy a chassis-bonding recommendation from another product where it could change leakage current or isolation.

Near field probes

Use a probe to compare local RF activity at the shield edge, connector and nearby circuits. Keep probe orientation, distance and analyzer settings fixed. When the lid is installed, the geometry changes; use the same accessible comparison points and do not compare readings taken at different distances as if they were equivalent.

A quieter regulator region with no change at the cable entry suggests that the local shield changed one path but not necessarily the one responsible for the error. Check the cable-current trend and the device log under the same conditions. The near-field probe troubleshooting guide explains the bench comparison in more detail.

Shielding effectiveness measurement

State what was compared before reporting a shielding change in decibels. A material coupon, local probe and full assembly test measure different quantities. A local result can guide a design change but cannot be transferred directly to the installed device or to a different frequency band.

Observation	Likely next check	What it does not prove
Local peak drops after lid installation.	Check cable behavior and device response.	That the final product meets emissions or immunity criteria.
Error changes with documented cable movement.	Investigate the connector and common-mode path.	That the shield lid is defective.
Result changes when the seam is pressed.	Check lid seating, gasket pressure and repeatability.	That an operator-dependent improvement is suitable for production.

For example, a receiver reading that changes from 55 to 47 dBµV in an unchanged bench setup shows an 8 dB drop for that observation. These are hypothetical readings. Do not call the difference enclosure shielding effectiveness unless the measurement method and geometry support that claim.

EMC immunity testing

Judge immunity by how the device performs under the specified disturbance, not by how quiet its spectrum looks. Log the observable product function, disturbance and configuration together. A lower local RF reading does not prove that a sensor reading, alarm or recovery behavior stays within its approved criterion.

For the hypothetical monitor, engineering should identify the sensor error or degradation that matters, how it is logged and how normal operation is assessed after exposure. The qualified product team defines the acceptance criteria from the intended use and applicable requirements. The FDA’s EMC guidance discusses device functions, intended environments, accessories and test evidence; it does not provide a universal shield design.

EMC test plan

Freeze the released assembly and record exactly what is being verified. Include the board revision, shield and gasket parts, housing, harness, supported accessories, operating modes and approved criteria. Before the formal evaluation, repeat the baseline and the proposed change in representative configurations so a result can be traced to the actual design difference.

In the example, release the fix only after the error is absent under the agreed conditions, the change is repeatable across the planned units and assemblies, and applicable safety and performance checks remain satisfied. If the result depends on one prototype, one cable position or one lid, keep the investigation open. Formal evaluation belongs with the product team and qualified lab.

FAQ

Why can a board pass emissions but fail immunity?

Emissions and immunity ask different questions: what the device produces and how it behaves when disturbed. A shield or filter may improve one path without protecting every affected function.

Does DC continuity prove good shielding?

No. It can reveal an open bond, but it does not characterize RF impedance around the whole seam or connector. Check contact geometry and compare performance under repeatable conditions.

Can removing a shield reduce one measured peak?

Yes. Changing the cover can change coupling, resonance or current paths. Compare the complete band and required operating configurations before accepting the result.

Why does a replacement lid need its own review?

Contact geometry, coatings and fit may change even if the outer dimensions match. Compare the drawing and the assembled contact condition, then repeat the affected verification.

Should the device always be tested while charging?

Include charging or other connected modes when they are part of intended use and the applicable plan. Keep the charger and cable identification with the configuration record.

Can a clip-on ferrite prove the cable is the only problem?

No. An improvement indicates that modifying the cable path affected the outcome. Other paths can still be present. Retest the affected modes and confirm the production solution separately.

Does a shield require rechecking thermal behavior?

Consider it if the change affects ventilation, heat transfer or component clearance. Compare temperatures in the assembled unit under the specified operating conditions rather than assuming a metal cover always improves cooling.

What belongs in the supplier package?

Include the shield land pattern, part and revision, height envelope, assembly constraints and inspection points. Keep product-level immunity acceptance with the device verification plan.

References

Discuss shield and board integration

For a Best Technology fabrication or assembly review, send the PCB revision, shield drawing and inspection requirements to sales@bestpcbs.com. Keep the complete-device EMC verification plan with the product team.

Tags: board level emi shielding, EMC, emc test, pcb design
Posted in bestpcb | No Comments »

PCB EMI Simulation Software: Choose the Right Model

November 13th, 2026

Controller PCB and cable next to a simulated field map on a laboratory monitor — Illustrative rendering; not a measurement or lab record.

Choose EMI simulation software by the decision you need to make. A circuit model can help explain which source drives a disturbance; a board field solver can show where current flows or couples; a system model can test whether a cable or enclosure changes radiation. None of these replaces an emissions test on the actual product.

Use this guide when a PCB design is still editable and you need to choose what to model before committing to another prototype. The running example is a hypothetical controller with a fast clock and an external coax connection. The question is whether to revise the board return path or investigate current on the outside of the cable shield first.

EMI simulation software

Start with the simplest model that includes the relevant source, coupling path and observation point. The useful output may be a port current, a relative field map or a predicted field at a specified location. Choose that output before picking a tool: an attractive field image is not a substitute for the quantity your decision requires.

Model type	Decision it supports	What it may miss
Circuit model	Compare source spectra, termination and damping.	Distributed geometry or radiation unless represented explicitly.
Board field solver	Locate return-current detours and compare layout changes.	Cables or chassis features omitted from the model.
3D assembly model	Compare coupling through connectors, cable and enclosure.	Operating modes or test arrangements not included in the model.

For the controller, first determine which clock harmonics need investigation. Ansys documents both board-level network extraction and near-field analysis in SIwave. These are distinct outputs, not interchangeable labels for an emissions prediction.

PCB EMI simulation

Define the source, return and measurable quantity in the same setup. Import the actual board revision and stack-up, then verify reference planes, plane cuts, vias and connector bonds. A model with a missing plane opening can be numerically stable and still represent a different board.

Set each excitation between the relevant conductors rather than connecting everything to a single ideal ground. Use a measured or documented source spectrum when amplitude matters. If a unit current is used to compare paths, label the result as a transfer comparison. It cannot be interpreted as the absolute noise generated by the operating controller.

PCB field solver

Use a board-focused solver for a predominantly planar path; use a 3D model when the return path runs through connector contacts, shielding or enclosure features not represented by the board model. Start with the suspected region and expand it when the result changes with the boundary or cutout.

For the controller, preserve the copper between the clock source and the connector, including the connector ground contacts and local return path. Compare the as-built board with a version where that return remains continuous. If the two cases give nearly the same connector current, don’t assume the detour is irrelevant; first check whether the excitation and the connector model are capable of revealing the difference.

Mesh convergence study

Refine the mesh until the quantity used for the decision stops changing materially between passes. A stable overall scattering-parameter result is helpful, but a local current at the connector can still be sensitive to how a narrow gap, via or port is modeled. Track the chosen observable as well as the solver’s convergence flag.

Suppose the project uses a 1 dB refinement tolerance for connector-current magnitude at a suspected harmonic. If successive passes change the magnitude by 0.4 dB but move the peak to a different part of the band, the model is not yet adequate for choosing a frequency-specific fix. The 1 dB is a teaching assumption, not a compliance limit. Recheck the sweep, refinement frequencies and port before proceeding.

Magnetic loop probe held above a PCB on a lab bench — Illustrative rendering; not a measurement or lab record.

Near field simulation

Use near-field simulation to compare where energy is concentrated close to the board, not to infer a chamber reading. Record the field component, sampling plane, distance from the board and frequency. Compare maps using the same color scale; automatically normalized pictures can make two very different amplitudes look identical.

On the first prototype, use repeatable probe height, orientation and fixture position to look for the predicted hotspot. A magnetic loop responds to field components according to its orientation. A relative hotspot check is useful even when the instrument or model is not calibrated for absolute field strength. The near-field probe guide covers the bench technique in more detail.

Common mode current in coaxial cable

Current on the exterior of a coax shield can take a different return path from the intended center-conductor and inner-shield current. Include the connector bond and the external path when the predicted board hotspot does not explain why emissions change as the cable is moved.

Compare two controlled configurations: same board and operating mode, but different documented cable placement or shield bond. Measure the outside-current proxy with a suitable RF current probe around the entire cable. If the cable-current peak shifts while the nearby board hotspot stays fixed, investigate cable and chassis coupling before widening traces or replacing the clock.

Radiated emissions simulation

A radiated-emissions model needs a defined assembly, source level, observation distance and orientation. Keep track of what geometry and modes it excludes. A board-only model may be adequate to rank layout options; an absolute prediction for the final assembly needs a model of the relevant return and radiating structures.

Comparison	Keep fixed	What to do with disagreement
Modeled versus measured peak frequency	Clock mode, workload and frequency axis	Check source spectrum and resonance geometry.
Modeled versus measured hotspot	Scan height, location and field component	Check probe orientation, local mesh and return path.
Modeled versus measured cable trend	Cable termination and repeatable routing	Review shield bond and omitted chassis paths.

EMC pre compliance testing

Use a physical pre-compliance scan to test the model’s predictions. Save baseline and changed configurations, record operating modes and fixture geometry, and compare the same frequencies and observables. Set aside any model whose claimed improvement does not survive a repeated measurement.

For the controller, make the smallest change that separates the two hypotheses: improve the board return with the cable unchanged, then repeat with only the cable arrangement changed. If the result follows one change, update the model accordingly. Close the design review when the predicted direction is reproduced and the remaining margins are understood; formal conformity still depends on the applicable test procedure and actual assembly.

FAQ

Can a schematic-only simulator find the radiating cable?

Not unless the cable and its coupling are represented in the model. A schematic can establish the likely noise source and spectrum, but two circuits with the same connectivity can radiate differently if the geometry, return path or shield termination changes.

Do I need the complete PCB database to start?

A representative region can be enough to evaluate a local hypothesis. Document the model cutout and terminations, then enlarge it if predicted currents depend on a boundary or if the return path leaves the cropped region.

Can I use one harmonic to validate the whole model?

No. Agreement at one frequency can be coincidental. Compare additional bands and changes in geometry or excitation; a model that reproduces those trends is more useful for deciding which design change to make.

Is a stronger near-field hotspot always worse?

No. Local concentration is not the same as efficient coupling into a radiator. Check whether the hotspot couples into a cable, enclosure feature or another structure that can carry or radiate the energy.

What should I export from the PCB layout?

Use a format supported by the chosen solver, then check the imported stack-up, copper geometry, via spans, plane boundaries and net mapping. Save the source revision and the model’s simplifications so the comparison can be reproduced.

How should I model an uncertain connector bond?

Compare plausible cases rather than assigning a precise value without evidence. If your conclusion reverses across those cases, measure or characterize the actual connection before treating the simulation as a design decision.

Is the best solver the one with the most detailed 3D model?

Not necessarily. A higher-detail model is helpful if those details control the observable. A simpler model with verified ports and geometry can be more useful than a complete-looking assembly with unverified excitation and material inputs.

What is the minimum evidence for a recommended layout change?

Retain the baseline, one controlled layout change, the convergence check and a matching prototype observation. State which frequencies and configurations the result covers. Do not generalize the finding to another board or enclosure without checking the relevant coupling path.

References

Discuss the PCB build

For a Best Technology PCB fabrication review, send the layout revision, intended stack-up and critical connector or return-path geometry to sales@bestpcbs.com.

Tags: board level emi shielding, EMC, emc test, pcb design
Posted in bestpcb | No Comments »

DC-DC EMI Filter Design: From Noise Mode to Validation

November 13th, 2026

DC-DC converter board on an electronics bench — Illustrative rendering; not a photograph of a production or test setup.

For DC-DC EMI filter design, first measure which frequencies miss the conducted-emissions limit and determine how the noise returns. Use a differential-mode LC stage for noise between supply and return, and investigate common-mode paths when both wires carry noise in the same direction. Then check that the filter improves emissions without destabilizing the converter.

Consider a hypothetical 24 V industrial controller with a 400 kHz buck regulator. The engineering question is not how to build the largest filter. It is how to reduce noise on the power harness while preserving startup and load-step behavior. The numerical examples below are calculations, not measurements or compliance results.

EMI filter design for DC-DC converter

Start at the converter input and trace the switching current through its local bypass capacitor, switches and return. In a buck converter, the input current is pulsed. A capacitor beside the switching stage supplies much of that pulse locally; a filter at the input connector then reduces the part that reaches the power harness. Keep the unfiltered switching-side copper away from the connector-side copper so coupling does not bypass the filter.

Keep the local bypass in place while measuring the baseline. Removing it changes the circuit being evaluated. For this controller, identify the worst operating input and load, mark the first harmonic or frequency band that fails, and save the setup before changing any components.

Conducted emissions test setup

Use the line impedance stabilization network (LISN), detector, bandwidth, grounding and harness specified for the product. A LISN makes the input impedance seen by the device more repeatable and couples the measured RF disturbance into the instrument. A bench supply and a long clip lead alone do not reproduce that measurement.

For a meaningful before-and-after check, hold the harness and load constant, measure the ambient floor, and capture the same operating modes with the same detector settings. Check that the measurement chain is not overloaded and that the setup follows the lab procedure. A pre-compliance scan is useful for design iteration; it is not a compliance claim.

Power supply conducted-emissions bench and DC-DC test board — Illustrative rendering; not a photograph of a production or test setup.

Common mode vs differential mode noise

Differential-mode current flows out on one power conductor and back on the other. Common-mode current travels in the same direction on both conductors and closes through another path, such as capacitance to chassis. A clamp around both power conductors together largely cancels equal and opposite differential current; a remaining signal suggests common-mode current if the probe arrangement and bandwidth support the measurement.

Observed clue	Candidate path	Change to test
Strong switching harmonic on individual lines, weaker with both inside the clamp	Differential	Test a damped LC stage and verify the local input bypass loop.
Peak remains with both lines in the clamp and shifts with chassis or cable placement	Common mode	Investigate coupling to chassis and trial a common-mode choke.
One band falls while another barely moves	Mixed or frequency-dependent	Test each band separately and check for bypass coupling.

Common mode choke filter

A common-mode choke uses coupled windings so equal and opposite load currents ideally cancel their flux, while common-mode currents see higher impedance. Select it using the impedance curve at the failing frequencies, continuous current and temperature rise. Leakage inductance adds some differential impedance, but it is not a controlled substitute for a separate differential stage unless characterized.

Before selecting a larger choke, inspect the alternative return path and the coupling from the switch node to chassis or a heat spreader. Changes to chassis capacitors may affect leakage current or isolation and must follow the product’s safety requirements. Recheck both noise modes because a layout change can alter how they couple.

EMI filter design calculation

An ideal 10 µH and 10 µF LC pair has an undamped resonant frequency of about 15.9 kHz, using 1/(2π√(LC)). If effective capacitance at the operating bias is 4 µF instead, it is about 25.2 kHz. Neither result is the attenuation at 400 kHz.

Input	Illustrative value	How to validate
Filter inductance	10 µH	Check inductance versus current and impedance versus frequency.
Effective capacitance	10 µF nominal; 4 µF in bias example	Use the selected part’s voltage and temperature curves.
Attenuation need	14 dB over limit + 6 dB chosen margin = 20 dB	Recheck the failing frequency with the actual source, load and harness.

Inductor parasitics, capacitor ESR and ESL, source impedance, and converter input behavior all affect the real result. Use the calculation to choose parts for a prototype. Use the spectrum and stability checks to accept or reject that prototype.

EMI filter damping

Damp the input filter if its impedance peak can interact with the regulated converter. A converter drawing approximately constant input power can present a negative incremental input resistance over part of its operating frequency range: a small input voltage dip can make it draw more current. An undamped high-Q filter can amplify the resulting disturbance.

One candidate is a resistor in series with an auxiliary capacitor, placed across the filter output. The capacitor blocks continuous DC current through that resistor, while the branch can dissipate energy near resonance. Compare the filter output impedance with converter input impedance in the interaction region using the converter vendor’s method. Then measure startup and load steps across input voltage and load. Check that input ringing decays and voltage stays inside the converter’s operating limits.

EMI filter insertion loss

Insertion loss describes how much the signal falls when the filter is inserted in a specified fixture. A vendor curve obtained with standardized source and load impedances helps compare parts, but the supply, harness and operating converter do not necessarily match that fixture.

Compare the prototype and the baseline at each failing frequency under the same setup. Save the margin to the limit, not just the largest peak reduction. A filter that reduces a 400 kHz peak but raises a different band above the limit has not solved the release problem.

Conducted emission test failure reasons

When a filter does not improve the failing band, first confirm the mode, the fixture and the board’s operating state. If adding differential inductance does nothing while the paired-wire clamp still sees the peak, investigate common-mode coupling rather than continuing to increase inductance. If filter input and output run beside each other, move or shield the coupling path before changing values again.

Release the design only after meeting the applicable emissions limit across defined modes with the chosen margin, preserving startup and load-transient behavior, and recording the exact tested BOM and layout revision. For a separate introduction to passbands and cutoff, see the low-pass filter circuit guide.

FAQ

Can the same filter be used on a boost converter?

Not by default. Recheck which port has discontinuous current and where the failing noise is measured.

Will a ferrite bead replace the filter inductor?

Only if its impedance under bias covers the failing band without creating an unacceptable resonance or voltage drop.

Why did the circuit reboot after adding the filter?

Capture converter-pin voltage during startup. Inrush drop, source current limiting and filter resonance can look similar at the output.

Should an input TVS be treated as the EMI filter?

No. A TVS limits transient voltage; it does not provide predictable continuous attenuation for switching noise.

Can spread spectrum replace the filter?

It can redistribute narrowband energy, but the final detector results, other frequency bands and operating modes must still pass.

Can I use the same scan for every harness length?

Only if the test plan allows it. Cable placement and length can change common-mode paths and resonances.

Why can a part with low DC resistance still perform poorly?

DC resistance does not show its high-frequency impedance or how that impedance changes near self-resonance.

What should be retained for a design review?

Save baseline and final traces, the limit and detector settings, input and load conditions, harness photos, startup waveforms and the board revision.

References

Discuss a PCB design for manufacture

For a layout or fabrication review, send the connector and filter area, stack-up and board revision to sales@bestpcbs.com.

Tags: board level emi shielding, EMC, emc test, pcb design
Posted in bestpcb | No Comments »

Copper Core PCB Manufacturer | Custom Insulated & DTP Boards

November 13th, 2026

Work with a copper core PCB manufacturer that can match your board construction to both the thermal requirement and the production budget. EBest Circuit supplies custom insulated copper-base boards and direct thermal path (DTP) boards for projects that need effective heat transfer, defined electrical isolation and a practical route into manufacturing.

Our service brings copper-base PCB fabrication, custom thermal structures and PCB assembly into the same project. From a compact MCPCB LED board to an assembled lighting module, we help connect the board specification with the finished product. Send your design to sales@bestpcbs.com to discuss an insulated or DTP build and receive a quotation for your required quantity.

Insulated or DTP Copper Core PCB: Which Fits Your Project?

An insulated copper core PCB is a strong starting point when the circuit needs electrical separation from the metal base. A DTP copper core PCB is worth considering when concentrated heat beneath a compatible component makes the dielectric under its thermal pad a significant limitation.

Both constructions use a copper base, but they move heat into that base differently. In an insulated board, heat passes through a thermally conductive dielectric. In a DTP construction, a designated thermal pad connects to a copper pedestal without that conventional dielectric directly beneath the contact.

Feature	Insulated copper core PCB	DTP copper core PCB
Path into the base	Through the dielectric	Through a direct thermal contact
Isolation at the thermal pad	Dielectric barrier	Direct base connection; package-dependent
Typical heat pattern	Distributed heat sources	Concentrated heat beneath a pad
Key fabrication work	Dielectric selection and lamination	Pedestal forming and alignment
Cost tendency*	Simpler fabrication	Added pedestal processing

For otherwise comparable designs. Both structures need a suitable mounting interface and external heat rejection.

If an insulated design already meets its temperature target, adding a custom pedestal may buy little useful improvement. When the dielectric beneath a small thermal pad is the limiting part of the path, DTP can be a more productive investment than simply increasing the copper-base thickness.

The cost difference is design-dependent. A large board with an expensive dielectric can cost more than a small, simple DTP board. Board area, panel utilization, copper thickness, pedestal count, finish and order quantity all affect the quotation. Where both structures are technically suitable, we can review the alternatives on the same dimensions and quantity basis.

The package matters as much as the board. A thermal pad connected internally to an electrical terminal cannot automatically share a copper base with other devices. DTP removes a particular thermal barrier; it does not make the complete board electrically isolated or the complete cooling system resistance-free.

Applications for Custom Insulated and DTP Copper Core PCBs

Insulated copper core PCBs combine heat spreading with circuit-to-base isolation. DTP copper core PCBs provide a more direct heat path beneath compatible component thermal pads.

Insulated copper core PCB applications

Multi-emitter lighting modules. Spread heat from several LEDs across a shared copper base while keeping their circuitry electrically isolated from it.
Pool and architectural lighting. Transfer heat toward the lamp’s mounting surface. Water protection comes from the enclosure, seals and connections—not the copper board itself.
Lighting boards with control circuitry. Accommodate emitters and associated circuitry where electrical separation from the metal base is required.
Power-electronic assemblies. Support heat spreading where the design requires a dielectric barrier between the circuit and the copper base.

DTP copper core PCB applications

High-power LED spotlights. Connect a compatible emitter’s thermal pad to the copper pedestal, bypassing the dielectric directly beneath that contact.
Stage-lighting emitters. Address concentrated heat in a compact emitter area through a package-matched thermal contact.
Inspection lighting and compact optical modules. Provide a direct pad-to-base heat path where a small light source concentrates heat into a limited footprint.

For custom DTP builds, we match the pedestal to the component footprint and thermal-pad electrical potential. Both board types still need a suitable mounting interface and cooling arrangement; the application name or LED wattage alone does not determine the construction.

Top 10 China Copper Core PCB Manufacturers

The following ten China copper core PCB manufacturers offer different combinations of copper-base fabrication, special thermal structures and assembly services. This is an editorial comparison of service scope, not a measured ranking of company size or product quality.

Manufacturer	Copper-board capabilities	Service focus
EBest Circuit / Best Technology	Insulated copper, SinkPAD/DTP, PCBA	Custom boards through assembly
PCBONLINE	Multilayer, hybrid, thermoelectric-separation boards; PCBA	Specialized structures and assembly
Jiubao / JBPCB	Single-sided, two-layer, direct-contact thermal pads; PCBA	Copper-base LED boards
NextPCB	Copper-core, pedestals, controlled-depth cavities	Thermal contacts and machining
RAYPCB	Insulated copper, DTP, assembly	Construction review and custom builds
Hitech Circuits	Copper-base LED boards, countersunk features	LED boards with mounting details
PCBELEC	Single-sided, double-sided, multilayer; pedestals	Bare-board fabrication and machining
ALCANTA Technology	Copper-core, copper-base, metal-core cavities	Specialized cavity constructions
QuickPCB	Copper-core prototypes and production	High-mix, low-to-medium volumes
Geyuan Electronics	Copper/aluminum MCPCB, electronics manufacturing	Boards within broader manufacturing projects

Hitech’s copper-base LED product includes a one-layer, 3 mm board with 1 oz circuit copper and countersunk features. This is a product configuration, not a universal capability limit.

For projects involving China copper core PCB manufacture, the most useful distinction is the required construction. A supplier offering copper-base boards does not necessarily offer every DTP geometry, cavity or multilayer combination. Equally, a broad PCB service portfolio does not make its smallest trace, thickest copper and highest layer count available together in one metal-core design.

EBest Circuit focuses this discussion on the actual board and assembly. If your project needs both a custom thermal structure and populated boards, we can review those requirements together before the fabrication specification is released.

EBest Circuit’s Custom Copper Core PCB Manufacturing Capabilities

We support insulated copper-base PCB projects and custom SinkPAD/DTP constructions. Our copper core PCB manufacture service covers the thermal structure, circuit pattern, mechanical outline and surface finish, with assembly available when populated boards are required.

For our SinkPAD/DTP product family, the following parameters provide a concrete basis for a manufacturing discussion.

Manufacturing item	SinkPAD/DTP reference capability
Copper-base thickness options	0.8, 1.0, 1.2, 1.4 and 1.5 mm
Finished board thickness	1.0–2.0 mm
Standard circuit copper	0.5, 1 and 2 oz
Special circuit copper	3–10 oz, subject to review
Maximum panel size	600 × 500 mm
Outline processing	Routing, punching and V-cut
Surface finishes	Immersion gold, ENEPIG, immersion tin and OSP
Solder-mask options	White, black, blue, green and red
Single-sided structures	One or two circuit layers on one side
Double-sided structures	SinkPAD configurations with circuitry on both sides

These values apply to the named product family. The finished stackup, feature combination and panel layout determine the available process window. Copper-base thickness in millimeters and circuit copper weight in ounces describe different parts of the board.

The DTP manufacturing work begins with two distinct features—the electrical circuit and the copper thermal contact. Our process separates their manufacturing data, forms the circuit layer and copper pedestal, and brings them together during alignment and lamination. The pedestal must meet the component’s thermal pad while remaining correctly positioned relative to the surrounding circuit.

This is why the copper bump, circuit opening and finished surface relationship matter. A generic copper-board specification does not fully define a DTP board. For insulated constructions, the dielectric remains part of the heat path and the electrical isolation system, so its thickness and properties also belong in the stackup.

We can extend the build into component sourcing and assembly. Copper-base boards draw heat differently from ordinary FR-4 boards during soldering, making the board construction and component limits relevant to assembly planning. Fabrication and PCBA can therefore be addressed as connected parts of the order.

Copper Core PCB Case Study: Board Selection and Manufacturing

An EBest Circuit pool-lighting project combined a two-layer copper core PCB with downstream assembly. The requirement was an assembled lighting board, so the thermal material, mechanical thickness and solderable finish had to be considered together.

Project item	Build specification
Application	Pool lighting
Board construction	Two-layer copper core PCB
Finished thickness	1.60 mm ±10%
Circuit copper	1 oz
Thermal material conductivity	3 W/(m·K)
Surface finish	OSP
Manufacturing scope	PCB fabrication and PCBA

Three details defined the build. The thermal-material specification described the insulating material, not the conductivity of the copper base. The finished thickness controlled the board’s mechanical fit. OSP formed part of the fabrication-to-soldering process.

We coordinated fabrication and assembly within the same project, giving the customer one manufacturing interface for the board and its populated assembly. The case demonstrates a complete copper-board supply scope without assuming that every lighting project needs a DTP structure.

Why Choose EBest Circuit as Your Copper Core PCB Manufacturer?

Choose EBest Circuit when the copper board, thermal construction and assembly need to be developed into one manufacturable order. Our offer combines specialty-board experience with the ability to carry the project beyond a bare PCB.

20 years of PCB industry experience. Founded in 2006, EBest Circuit brings two decades of experience across PCB fabrication, metal-core structures and assembly services to custom copper-board projects.
Quality certifications supporting supplier qualification. Our certification portfolio includes ISO 9001:2015, ISO 13485:2016, IATF 16949 and AS9100D. These quality systems support manufacturing control and customer qualification requirements, with the applicable certification and site scope matched to each project.
A choice of thermal structures. Insulated copper-base and SinkPAD/DTP options allow the discussion to start with the product requirement, rather than forcing every design into one board type.
Experience with the actual DTP fabrication route. Separating circuit and thermal-contact data, forming the copper pedestal and aligning the laminated structure are specific manufacturing tasks behind the service.
Mechanical customization tied to the board. Outline processing, thickness and surface finish can be reviewed alongside the mounting arrangement instead of being treated as afterthoughts.
Fabrication and assembly in one project. Our PCB and PCBA services let customers source a populated thermal board with fewer separate supplier interfaces.

For a product containing both a thermal board and a separate control board, our wider PCB manufacturing range also supports the different constructions within the same sourcing discussion. The result is a service organized around the product’s boards, rather than copper material alone.

Get a Custom Copper Core PCB Quote

Send your Gerber files, fabrication drawing and required quantities to sales@bestpcbs.com. Include the copper-base thickness, circuit copper and required finish. For DTP, add the component part number or package drawing and the intended thermal-pad connection; for assembled boards, include the BOM and placement data.

If the structure is still open, tell us the application, available board space and cooling arrangement. We can review which constructions are manufacturable and quote the appropriate scope. Prototype and production quantities can be quoted separately so you can see the effect of setup and batch size on the order.

FAQs About Copper Core PCB Orders

What is the minimum order quantity for a custom copper core PCB?

Prototype and small-batch requirements can be reviewed. The accepted quantity and price depend on the material, panel layout and any special tooling; there is no single minimum that applies to every insulated and DTP construction.

How long does a custom DTP board take to manufacture?

Our SinkPAD reference schedule is approximately 1.5–2.5 weeks for samples and 2.5–3.5 weeks for production. The confirmed schedule depends on material availability, engineering release, quantity and process complexity. Assembly and shipping require their own scheduling allowance.

Can you supply bare boards first and assembled boards later?

Yes, both fabrication and assembly can be included in the project scope. Planning the later PCBA stage early helps align the surface finish, component availability and handling requirements with the prototype build.

Can a copper core PCB have components on both sides?

Suitable double-sided constructions are available. Their interconnection route and heat-sink access differ from single-sided boards, so a two-sided component layout needs its own stackup and mounting review.

Can I reuse the artwork from an aluminum PCB?

Some circuit artwork may be reusable, but a material substitution still affects the stackup, machining and assembly conditions. A change to DTP additionally requires the thermal-contact geometry to be incorporated into the design.

Does ordering more boards always lower the unit price?

Larger quantities can spread setup and tooling costs over more boards. The saving depends on panel utilization, material purchasing and the production process; it is not a fixed percentage for every quantity increase.

Can you manufacture replacement copper boards from an existing sample?

A sample can support a manufacturing discussion, but the outline and visible circuit do not reveal every material or insulation requirement. Available drawings, electrical data and component information help define a replacement that matches the intended construction.

Bring your next copper core PCB project to sales@bestpcbs.com. As your copper core PCB manufacturer, EBest Circuit can review the insulated or DTP construction and quote fabrication or an assembled-board supply scope for your product.

Tags: copper core pcb, Copper core pcb manufacturer, Insulated Copper Core PCB
Posted in Metal Core PCB | Comments Closed

ADC Anti-Aliasing Filter Guide: From Bandwidth to Bench Test

November 13th, 2026

An ADC anti-aliasing filter attenuates unwanted analog frequencies before the analog-to-digital converter samples them. Choose it using two requirements: how much of the wanted signal must pass, and how small an unwanted signal must be after it folds into that band. Setting the cutoff below half the sampling rate is not enough by itself.

Follow a hypothetical sensor channel that measures DC to 1 kHz at 10 kS/s. A switching tone appears at 9.4 kHz. The challenge is to preserve the sensor signal, suppress the false reading caused by that tone, and still let the ADC input settle before each conversion.

Small data acquisition evaluation board on a laboratory bench — Illustrative rendering. The analog filter and the ADC input must be designed and verified together.

Why use an anti aliasing filter before ADC sampling?

Once sampling folds an interfering tone onto a wanted frequency, the samples alone cannot tell which analog signal produced it. A digital filter can remove unwanted frequencies that remain outside the wanted digital band. It cannot separate two signals that now occupy the same frequency there.

For a baseband sensor, define the highest frequency you need to keep, then identify likely interferers, including switching clocks, motor drives or nearby signals. The analog filter goes before the sampling point. For general circuit behavior and topology background, see the low-pass filter circuit guide.

How to use the aliasing frequency formula

At 10 kS/s, a 9.4 kHz input tone appears at 600 Hz, inside this sensor’s 0–1 kHz band. For a single real tone, calculate the folded frequency as |f_in − kf_s|, choosing the integer k that puts the result between zero and f_s/2. Use the same frequency units for both inputs.

Here k = 1, so |9.4 − 10| kHz = 0.6 kHz. A tone above Nyquist does not always land inside the wanted band. For example, at the same sample rate a 6 kHz tone lands at 4 kHz. A digital low-pass filter can reject that component, provided the analog input has not overloaded and no other unwanted products land in band. Check the spectrum around multiples of the actual sampling rate, not just the region immediately above Nyquist.

How to choose an anti aliasing filter cutoff frequency

Choose the cutoff by testing both the allowed loss at the passband edge and the required attenuation at the interfering frequency. In this teaching example, the wanted signal may lose at most 0.5 dB at 1 kHz. A 100 mV RMS interferer at 9.4 kHz must be reduced to at most 1 mV RMS: the filter therefore needs at least 40 dB of attenuation there, assuming no downstream gain change or overload.

Design input	Example	Where to confirm it
Wanted band and allowed loss	DC–1 kHz; ≤0.5 dB loss at 1 kHz	Sensor and system accuracy budget
Actual sample rate	10 kS/s	Converter clock and firmware configuration
Interferer and permitted residual	100 mV RMS at 9.4 kHz; ≤1 mV RMS	Input spectrum and allowable in-band error
Acquisition window	Device and configuration specific	ADC timing table and input model

For a single tone, required attenuation in decibels is 20 log₁₀(input amplitude ÷ allowed residual amplitude). Use matching units and amplitude conventions. For broadband noise, one spot-frequency check is not enough: evaluate the filtered noise that folds into the measurement band.

Choosing the low pass filter order

In the 10 kS/s example, a single ideal RC pole cannot meet both limits. Solving the one-pole equation for each limit gives incompatible cutoff ranges: at least 2.86 kHz to preserve the 1 kHz signal, but no more than about 94 Hz to reject the 9.4 kHz tone by 40 dB. Simply swapping the capacitor cannot fix this trade-off. At a 1.5 kHz cutoff, a single pole loses about 1.60 dB at 1 kHz and gives only 16.05 dB of attenuation at 9.4 kHz.

An ideal third-order Butterworth response at the same 1.5 kHz cutoff gives about 0.37 dB loss at 1 kHz and 47.8 dB attenuation at 9.4 kHz. These are calculated values, not a measured circuit. For an ideal Butterworth response of order n, positive attenuation at frequency f is 10 log₁₀[1 + (f/f_c)²ⁿ]. The ratios are unitless; f_c is the −3 dB frequency. Three identical unbuffered RC sections do not automatically give this response.

Approach	Use when	Verify
Single passive RC	Measured interference and the transition band allow gentle roll-off	Passband loss, stopband and source/load effects
Higher-order analog filter	One pole cannot meet both limits at the available sample rate	Component tolerances, amplifier behavior and step settling
Oversample and digitally filter	The converter and processor have throughput headroom	Analog alias bands at the higher sample rate and rejection before decimation

SAR ADC anti aliasing filter: Check acquisition settling

A successive approximation register (SAR) ADC often connects an internal sampling capacitor to the input during acquisition. The driver must restore the input to within the allocated error before that window closes. An RC network next to the input may reduce sampling transients, but its bandwidth can be too high to provide the required anti-alias attenuation.

Find the acquisition time, source-drive guidance and input model in the exact ADC data sheet. Then check the driver, isolation resistor, external capacitor and sampling switch together for the largest expected step, including a channel change if the input is multiplexed. As a simple first-order screening calculation, a full-scale step settling to half an ideal LSB on a 12-bit ADC takes at least ln(8,192), or about 9.01 time constants. This calculation assumes exponential settling and gives no allowance for noise or other errors. It is not a substitute for the converter’s switched input model.

Small surface mount passives next to an integrated circuit on an evaluation board — Illustrative rendering. Use the converter’s input circuit and timing table to check settling, not the appearance of the passive components.

Sigma delta ADC anti aliasing filter: Which rate matters?

Start with the internal modulator sampling rate and the data sheet’s combined analog and digital response, not just the output data rate. A sigma-delta converter may oversample internally and use digital filtering to reject much of the unwanted content before reducing its output rate. Interference near vulnerable analog sampling bands still needs attention.

Read the frequency-response plot and note the selected filter mode, output data rate and any rejection holes or repeated response near the modulator rate. For multiplexed sensors, also check digital filter settling after a channel change. A mode that offers excellent steady-state rejection may take too long to settle for your channel scan.

Anti aliasing filter example: When a higher sample rate changes the choice

Change only one condition in the sensor example: sample at 20 kS/s rather than 10 kS/s. The 9.4 kHz tone now lies below the new 10 kHz Nyquist limit and remains at 9.4 kHz in the initial samples. If the ADC and analog driver tolerate it without overload or distortion, the digital filter can reject it before a lower-rate output is produced.

That change does not make the analog filter optional. A different tone at 19.4 kHz would now fold to 600 Hz. Measure or bound interference near the new alias bands and recalculate the analog rejection requirement. If the ADC cannot support the higher sample rate with adequate acquisition time, keep the lower rate and evaluate the higher-order analog option instead.

How to verify an ADC anti aliasing filter design

Run two separate bench checks: one for frequency rejection, another for settling. Apply a known tone at the passband edge and then an out-of-band tone predicted to fold into the wanted band. Compare the raw ADC spectra against the loss and residual limits. In the example, the checks are 0.5 dB maximum loss at 1 kHz and no more than 1 mV RMS equivalent at 600 Hz for the specified 9.4 kHz injection.

Next, apply the largest expected input or channel step and verify the first accepted conversion against the allocated error. Record source amplitude and impedance, sample rate, gain, test window and channel sequence. If the alias test passes but the step fails, review acquisition and driver settling rather than adding more filtering. If the step passes but a tone folds into band, inspect the source spectrum and actual analog attenuation. Repeat under the operating conditions that matter to the product.

Evaluation board beside signal generation and measurement equipment — Illustrative rendering. Measure both out-of-band rejection and the ADC’s response after an input step.

FAQ

Is an anti-aliasing filter the same as a noise filter?

Not always. A noise filter may target any unwanted band. An anti-aliasing filter specifically attenuates analog signals that would fold into a band you need to measure. One circuit can do both if its response meets both sets of requirements.

Is the Nyquist frequency a good cutoff setting?

Not by itself. At the cutoff, a standard Butterworth response attenuates the signal by only about 3 dB. Decide which interferers can fold into your measurement band and calculate the attenuation needed at their original frequencies.

Can I fix an aliased reading by averaging more samples?

Not reliably. Averaging may reduce some noise, but an interfering tone that has already folded onto a frequency you need cannot be separated from a real signal there merely by averaging.

Why do two RC pairs with the same cutoff behave differently?

The same RC product gives the same ideal unloaded pole, but different resistor and capacitor values change source loading, thermal noise, amplifier drive and sampling recovery. Check the actual connected circuit rather than assuming equal cutoff means equal performance.

Can a passing sine sweep prove the ADC input settles?

No. A frequency sweep checks a steady-state response. A large step or channel change can expose acquisition errors even when the sweep meets the passband and stopband targets.

Can software replace the filter before I decimate?

Software can reject frequencies that were captured without already folding into the wanted band. Apply the appropriate digital filter before downsampling, but first verify what aliases at the original analog sample rate.

Why does a suspected alias move when I change the sample rate?

A folded tone depends on the sampling rate as well as its original frequency. A small controlled change in sample rate can help distinguish it from a genuine baseband tone. Confirm the result by checking the analog input spectrum; a moving line alone does not identify the source.

What should I include in an ADC board review?

Include the converter and driver part numbers, schematic, actual sampling and acquisition timing, desired signal band, measured or bounded interferers, error budget and test results. Flag whether a problem is spectral rejection, step settling or both.

Technical references

Tags: Filter Circuit, Low Pass Filter, pcb design, Signal Integrity
Posted in bestpcb | No Comments »

Cookie	Duration	Description
cookielawinfo-checkbox-analytics	11 months	This cookie is set by GDPR Cookie Consent plugin. The cookie is used to store the user consent for the cookies in the category "Analytics".
cookielawinfo-checkbox-functional	11 months	The cookie is set by GDPR cookie consent to record the user consent for the cookies in the category "Functional".
cookielawinfo-checkbox-necessary	11 months	This cookie is set by GDPR Cookie Consent plugin. The cookies is used to store the user consent for the cookies in the category "Necessary".
cookielawinfo-checkbox-others	11 months	This cookie is set by GDPR Cookie Consent plugin. The cookie is used to store the user consent for the cookies in the category "Other.
cookielawinfo-checkbox-performance	11 months	This cookie is set by GDPR Cookie Consent plugin. The cookie is used to store the user consent for the cookies in the category "Performance".
viewed_cookie_policy	11 months	The cookie is set by the GDPR Cookie Consent plugin and is used to store whether or not user has consented to the use of cookies. It does not store any personal data.