Ceramic Thermal Shock: What Makes a Test Comparable?

November 14th, 2026

A ceramic thermal shock report is comparable only if you know which substrate was tested, how its temperature changed, and what counted as failure. The same chamber endpoints and cycle count can produce different stresses in two tests. Before releasing a copper-clad ceramic board, match the test to the service load and review what changed at the copper edges, ceramic and bonded interfaces.

Ceramic and copper-clad substrate samples near an environmental test chamber — Illustrative laboratory setup, not a qualified chamber or a recorded test result.

Ceramic thermal shock

When part of a ceramic heats or cools faster than the rest, the resulting temperature gradient can generate stress. On a copper-clad substrate, copper and ceramic also try to expand by different amounts even if the specimen temperature is fairly uniform. The bonded layers constrain each other. Changes in copper pattern, ceramic thickness and support can therefore change where the first damage appears.

Consider a converter with an unpowered copper-clad ceramic tile mounted to a baseplate. An abrupt change in its surroundings can load the tile differently from normal operation, when heat starts at the devices. Even a coupon made of the same ceramic does not reproduce both loads. Define which situation the qualification is supposed to represent.

Thermal shock resistance of ceramic materials

There is no universal temperature jump that all ceramic substrates can withstand. A bare-material result depends on the grade, geometry, flaw population and test environment. A metallized construction adds copper thickness, pad shape and interface effects. Start with the material type, but test the intended construction if it is the construction you will buy.

Rogers’ substrate reliability note explains why ceramic and copper thickness affect cycling behavior. A candidate with a promising bare-ceramic strength result still needs evidence from the actual patterned build. The ceramic flexural strength guide covers that separate material test.

Thermal shock vs thermal cycling

Compare the sample temperature history, not just the names of the tests. A rapid transition can stress the surface while the interior lags. Repeated temperature cycling can drive cumulative damage from differential expansion even when the sample changes temperature more gradually. Some specifications use different terminology, so look at the test method and actual exposure before assuming one is more severe.

Thermal shock vs. temperature cycling vs. power cycling
Test approach	What applies the load	When its evidence matters
Thermal shock	Rapid change of the external environment.	Evaluating a defined fast transition and associated gradients.
Temperature cycling	Repeated external hot and cold exposure under a controlled profile.	Evaluating repeated expansion mismatch in the specified assembly.
Power cycling	Repeated internal heating from active devices followed by cooling.	Evaluating load histories driven by operation of the device and its cooling path.

Thermal shock test chamber

Record the medium and whether the test moves a specimen between zones or changes the environment around it. Air and liquid generally transfer heat to a specimen at different rates. Chamber setpoint, chamber air temperature and actual sample temperature are not interchangeable. Fixture mass, spacing and location can also change a sample’s response within the same chamber.

If the production tile sits on a baseplate, use a temperature measurement plan that can distinguish the ceramic assembly response from a nearby chamber probe. Confirm that sensors and their attachment do not materially change the accessible measurement or the thermal path being investigated. Compare reports only when their sensor positions and definitions of dwell are compatible.

Thermal shock test standard

IEC 60068-2-14 addresses change-of-temperature testing. Refer to the applicable revision and the selected procedure in the purchase or qualification documents. Do not take an example condition from a component specification and apply it automatically to a metallized PCB substrate.

Ask whether the contract governs a bare substrate, metallized tile or assembled module. Record the permitted interface change, crack criteria and any electrical or thermal checks required after test. The method and exposure do not decide acceptance on their own.

Thermal shock test procedure

Before the test, document the specimen revision, ceramic and copper thicknesses, pattern, supports and baseline condition. During the test, log chamber and sample readings separately where relevant. Record extremes, transition time, soak definition, cycle count and inspection intervals. A sample without enough time to approach its intended temperature can see a smaller swing than the chamber displays.

What to compare between two supplier reports
Field	Record	Hold the comparison if
Specimen	Ceramic grade, metal pattern and thickness, support, and sample count.	A bare coupon is compared with a mounted tile as if they were the same.
Exposure	Medium, temperatures, sensor locations, transition and dwell, cycles.	Only the endpoints or cycle count are shown.
Outcome	Initial and final checks, locations, inspection sensitivity and agreed limits.	One lab checked only visible cracks while the other also inspected hidden interfaces.

Power cycling test

Power cycling heats the assembly from within. The differences between the device, attach layers, ceramic and cooling boundary may not match those in an unpowered chamber. Use load and cooling conditions appropriate to the module and document what temperature swing the device or assembly actually experienced.

A published DBC substrate experiment used a SiC micro-heater in a specific assembly to investigate heat dissipation and stability. Its construction and loading are part of the result. For the converter example, an unpowered chamber pass does not qualify the device attach or the assembled module under normal power cycles.

Thermal shock resistance formula

Thermal shock criteria depend on the model and boundary conditions. For a first look at copper-to-ceramic expansion mismatch, estimate their difference in free thermal strain as Δα × ΔT. With illustrative coefficients of 17 and 7 ppm/K over a uniform 100 K swing, the free-strain difference is 1,000 microstrain, or 0.10%. This is not interfacial stress, a maximum safe temperature swing or a life prediction.

To interpret a failed sample, compare the copper edge pattern, the pre-test inspection and the first location where a change appeared. A surface crack, a separated interface and a change in thermal resistance require different follow-up evidence. Confirm suspected hidden damage with a suitable inspection or targeted section, and use the contract’s pre-agreed limit. A visible pass alone does not prove a bonded interface is unchanged.

Copper-clad ceramic substrate edge positioned for inspection — Illustrative inspection view. It does not show a crack or prove interface integrity.

FAQ

Can two tests with the same cycle count be compared?

Only when the specimens, sample exposure, inspection and failure criteria are comparable. Count alone tells you how often a defined cycle was repeated.

Does a larger temperature range always make the test harsher?

Not by itself. The actual sample ramp, gradients, dwell and load history affect the stress and damage.

Does a bare ceramic pass qualify an AMB or DBC tile?

No. Joining, copper geometry and interfaces introduce stresses and failure modes absent from a bare coupon.

Can room-temperature bend strength replace thermal shock testing?

No. It describes failure under a defined mechanical fixture, not the damage caused by a temperature history.

Why inspect before the first cycle?

A baseline helps distinguish pre-existing edge or interface indications from changes during exposure.

Does a continuity pass rule out delamination?

No. An electrically intact conductor can remain connected while the bonded area beneath it changes.

Will an air test and a liquid test give the same result?

Do not assume so. Confirm that the sample temperature histories and stress conditions actually support the comparison.

Can a single coupon release every construction from the same supplier?

No. Establish the qualified scope in advance; changes in pattern, thickness or support can require new evidence.

Prepare a ceramic substrate qualification review

Send Best Technology the ceramic grade, copper layout, substrate dimensions and intended support at sales@bestpcbs.com. Include the service temperature history and what you need inspected so the scope of material and assembly evidence can be agreed separately.

Tags: ceramic PCB, ceramic substrates, thermal cycling, Thermal Shock
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Ceramic Flexural Strength: What a Bend Test Proves

November 14th, 2026

A ceramic flexural strength result tells you the nominal stress at which a tested specimen broke in bending. It does not tell you how much force a finished ceramic PCB can take under a clamp. If two material reports use different fixtures, specimen sizes or edge finishes, settle those differences before ranking their MPa values. Then verify the actual load path on the metallized substrate or assembly.

Ceramic test bar positioned between rounded supports in a laboratory bend fixture — Illustrative bend-test fixture, not a test report or an acceptance specimen.

Ceramic flexural strength

Flexural strength, usually reported in MPa, is a calculated failure stress under a defined bending test. As a flat specimen bends, one surface experiences tension and the opposite surface compression. A flaw on the tensile side can open and start a crack. The reported result describes the tested population: material grade, surface, edges, geometry, loading and environment. There is no universal value for a ceramic circuit board.

Consider a power module on a thin ceramic tile supported at the base. The material supplier tests clean unmetalized bars; the finished tile has copper, routed edges and a different load path. The bar report helps compare material candidates, but it does not prove that the tile can tolerate installation or temperature cycling.

Three point bending test

A three-point fixture supports the test bar at two locations and loads it midway between them. For a symmetric ideal setup, the bending moment peaks near the middle and drops toward the supports. The peak tensile stress is confined to a smaller region than in a comparable four-point arrangement. Ask for the outer span, width, thickness, loading condition and failure location. A break associated with a fixture contact deserves investigation rather than automatic treatment as normal material failure.

Four point bending test

A four-point fixture uses two supports and two loading points. Under symmetric loading, the ideal bending moment is constant between the inner loading points. More surface can experience the peak stress, exposing more potential flaw sites; that can lower the reported strength for an otherwise comparable material. Do not convert three-point and four-point means using a fixed multiplier.

Three-point vs. four-point flexure vs. an assembly test
Test	What it can establish	What to check before comparing
Three-point flexure	Failure stress for a bar loaded at its center.	Outer span, surface under tension and fracture location.
Four-point flexure	Failure stress with an extended region under maximum bending moment.	Inner and outer spans, load convention and specimen preparation.
Representative assembly test	Whether a finished part survives the agreed loading and support.	Metallization, contact footprint, loading sequence and post-test checks.

ASTM C1161 covers ambient-temperature flexural strength testing of advanced ceramics. Ask which revision and configuration the lab followed and whether the reported specimen meets that configuration. A supplier’s three-point material comparison is not automatically a C1161 report.

Flexural strength formula

For a rectangular beam in ideal three-point bending, the nominal outer-fiber stress at failure is 3FL/(2bt²). Here F is the total center load at break, L is the support span, b is width and t is thickness. Using N and mm gives N/mm², equivalent to MPa. This expression does not apply unchanged to four-point loading, unusual specimen shapes or a tile resting on a compliant pad.

For a hypothetical specimen with F = 80 N, L = 20 mm, b = 4 mm and t = 1.50 mm, the nominal stress is 267 MPa. If the width, span and failure force were unchanged but thickness were measured as 1.45 mm, the reported value would be about 285 MPa. This isolates a thickness-input effect; it is not a prediction of how the second bar would actually break. Check the measured thickness before treating a small change in reported strength as a material improvement.

Flexural strength test specimen

Compare specimens before comparing averages. Specify grade and lot, test temperature, dimensions and spans, surface finish, tensile face, edge preparation, sample count and the spread of results. A polished bar and an as-fired or cut production specimen can contain different flaw populations. Mixing bars from different machining batches can conceal variation that follows a particular edge process.

Start a supplier comparison with matching configurations and obtain individual results when the decision turns on low values, not just the mean. Where a statistical reliability model is needed, ASTM C1239 provides a practice for reporting strength data and estimating Weibull parameters for brittle advanced ceramics. A small first-article sample can identify a process problem; it is not proof of a low field failure rate.

Ceramic electronics substrate coupons with different surface finishes on a laboratory bench — Illustrative specimens. Grade, finish and edge preparation must be identified before comparing the results.

Alumina flexural strength

Alumina is a practical baseline for many electronics substrates, but use a grade-level result rather than applying a catalogue value to all alumina. A Kyocera ceramic substrate data sheet explicitly labels its flexural strength row as a three-point result. A higher value from a different supplier cannot be judged superior without checking the method, test specimen and reporting basis.

For the example module, rank candidate alumina grades only after confirming the thermal path and the geometry likely to carry bending load. If the application requires a thin substrate, material strength alone does not cancel the increase in bending stress from the thinner section.

Silicon nitride flexural strength

Silicon nitride is worth evaluating when mechanical robustness constrains the layout. Aluminum nitride may instead be attractive when conduction through the substrate dominates. The grade comparison should include thermal conductivity, flexural method and the ability to reproduce the intended thickness and finish. CeramTec’s substrate data illustrates how one supplier differentiates these properties across specific materials.

Alumina vs. aluminum nitride vs. silicon nitride
Candidate	Why consider it	What to verify before switching
Alumina	Baseline where thermal and mechanical requirements can both be met.	Actual grade, thickness and edge quality on production geometry.
Aluminum nitride	Heat transport through the ceramic is a governing design requirement.	Grade-specific conductivity and mechanical results on compatible specimens.
Silicon nitride	Bending and crack resistance are central to the package choice.	Grade, metallization route, thickness and the complete thermal path.

Ceramic fracture toughness

Fracture toughness characterizes resistance to growth of a crack under the specified mode and test method. It is not another name for flexural strength. If finished substrates crack from a chipped edge while polished coupon strength stays stable, investigate the origin of the fracture and the production edge before raising the minimum coupon MPa. That distinction helps separate a change in the material from a change in the flaws the process introduces.

For the finished module, verify a representative metallized part with the actual enclosure support and contact conditions. Specify the load case, inspection before and after, and any required electrical or thermal checks. The ceramic substrate mounting guide addresses the separate question of how the installation creates the load. Keep the bar test and assembly evidence in different acceptance fields.

FAQ

Is ceramic flexural strength the same as compressive strength?

No. The bending result generally reflects fracture under tensile stress at one face. A compression value does not substitute for it.

Does a thinner bar necessarily have lower reported MPa?

No. Thickness affects calculated stress and the force required to cause it. The measured result also depends on the flaw population and test configuration.

Can a laser-cut edge and a polished edge be compared directly?

Not as evidence of the same process. Record the edge condition and use specimens representative of the question under review.

Can I specify only a minimum supplier average?

You can specify an agreed statistic, but a mean alone does not control how low individual results can be. Define the sample plan and minimum or statistical criterion needed for the decision.

Is copper on a ceramic coupon irrelevant to bending?

No. Copper can change stiffness, stress distribution and residual stress. Identify whether the result refers to bare ceramic or a metallized construction.

What if a fracture starts outside the intended region?

Check alignment, contact effects and the test method’s validity criteria. Keep the observation documented rather than removing it silently.

Does a room-temperature bend test prove thermal-cycle life?

No. Use a representative thermal or combined-load qualification when the application requires it.

Which detail should I ask for first when two results differ?

Start with the bend configuration and specimen geometry, then check edge and surface preparation. These details can explain a difference even before the material grade changes.

Prepare a ceramic substrate review

Send Best Technology the ceramic grade, thickness, metallization and support drawing at sales@bestpcbs.com. Include the test report and mark the areas where the finished part will be loaded so the material evidence and part-level checks can be reviewed separately.

Tags: Bend Testing, ceramic PCB, ceramic substrates, Flexural Strength
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Laminated Busbar Inductance: Where the Loop Gets Longer

November 14th, 2026

A laminated busbar lowers inductance when the outgoing and return currents follow closely spaced, overlapping copper plates. It helps less if the current must separate at the capacitor terminals, mounting tabs or switching module. Before choosing a laminated busbar over a heavy copper PCB, trace the complete switching current loop and compare the inductance of the assembled paths, not just the copper weight or the busbar by itself.

Overlapping copper plates with a thin insulating layer on a power electronics bench — Illustrative unpowered busbar assembly; not a tested product or a verified installation.

Laminated busbar inductance

Inductance describes the voltage associated with changing current. In a laminated pair, close parallel plates carrying equal currents in opposite directions confine much of the magnetic field between them. The loop usually has less inductance than two conductors routed far apart. Thick copper lowers DC resistance, but it does not by itself bring the return path closer. In a heavy copper PCB, closely spaced power and return planes can use the same principle.

Keep two numbers separate: the inductance between the busbar’s defined terminals and the effective inductance of the assembled switching loop. A low first number does not guarantee a low second one. Infineon’s PrimePACK application note shows how a laminated DC-link connection is arranged at a module.

DC link busbar

The DC-link busbar connects the DC source and capacitor network to the switches. The path carrying average supply current need not be the path carrying the fastest current change. For a half-bridge, trace the loop from the effective local DC-link capacitor through the switch positions and back to the opposite capacitor terminal. Include the capacitor’s terminal and internal inductance, the busbar or board conductors, the joints and the module package. Clearly identify which external paths are outside this loop.

For example, an inverter layout may have a long DC feed and a short, well-coupled path to the nearest film capacitor. Shortening the feed does not necessarily fix switching overshoot. Conversely, moving a capacitor closer by straight-line distance may not help if its terminal geometry forces the positive and negative connections apart.

Commutation loop inductance

As a first-pass estimate, the inductive voltage contribution is L × |di/dt|. If the design allocates 40 V to this contribution and the applicable current slope is 4 A/ns, the effective loop budget is 10 nH. This is an illustrative allocation, not a device limit. An estimated 15 nH at the same slope contributes approximately 60 V. Do not add that number directly to a measured peak as if ringing, device capacitance and observation point did not matter.

The useful quantity belongs to a defined loop under the conditions of interest. Changes in current distribution and mutual coupling can make a schematic sum of isolated conductor values misleading. The published study on SiC converter busbar design separates the busbar, capacitor, connector and package contributions and shows why the terminals belong in the analysis.

DC link capacitor busbar

Review both capacitor terminals with the return route visible. A large remote capacitor bank can support stored energy and slower ripple while a nearby low-inductance path supplies fast switching current. Parallel capacitors do not automatically share high-frequency current equally: different placement, terminations and parasitic inductances change the current distribution. A short broad path is only helpful if it remains paired with its return close to the capacitor and at the module.

In the inverter example, if the positive tab is on the near edge and the negative tab returns around a mechanical opening, the loop can be dominated by that opening rather than by the flat overlap. Ask for the assembled geometry and compare alternative terminal orientations before paying for a thicker pair of plates.

Laminated busbar design guide

Choose a laminated assembly when separate formed conductors better meet current, mechanical or terminal constraints. Choose a heavy copper PCB when closely paired layers meet the same loop budget and integration is more important. Use separate conductors only when the fast switching loop is controlled elsewhere or when measured inductance still meets the requirement.

Laminated busbar vs. heavy copper PCB vs. separate bars
Construction	When it fits	What to verify
Laminated busbar	Broad paired conductors are possible, with heavy terminal loads.	Plate overlap at the tabs, assembly alignment and the insulation system.
Heavy copper PCB	A layered return path and integrated routing fit on one board.	Layer spacing, via and terminal transitions, current distribution and temperature rise.
Separate bars	The conductors carry feed current and a separate compact path closes the fast loop.	The location of the actual switching loop and measured switching stress.

A busbar’s dielectric spacing cannot be chosen from inductance alone. For products where IEC 60664-1 applies, coordinate the insulation design with the responsible compliance engineer and the applicable product standard. Close spacing does not waive separate checks at exposed edges, cutouts and terminals.

Busbar inductance calculator

Use a parallel-plate estimate only to compare the straight, broad overlap regions with the same assumptions. In its wide-plate limit the estimate is μ₀ times overlap length times plate separation divided by width, for a nonmagnetic spacer. For a 100 mm long overlap, 50 mm wide, with 0.50 mm separation, this gives about 1.26 nH. Doubling separation gives about 2.51 nH with the other inputs unchanged. These are idealized straight-section estimates, not assembled loop values or measured data.

The estimate assumes closely spaced plates, approximately opposing currents and width much greater than separation. It omits end effects, joints, apertures and curved tabs, and does not predict current crowding or resonant impedance. Use field extraction or a supplier model with the actual geometry and frequency band if a transition can dominate. Record the port pair on every result so that two nominally identical values are comparable.

Close view of overlapping copper busbar plates separated by an insulating sheet — Illustrative plates and spacer. The visible overlap does not include the complete current path.

Laminated busbar manufacturing process

Manufacturing must reproduce the conductor spacing and alignment used in the electrical review. Do not approve a busbar from a front-view drawing alone. Specify the plate stack, terminal datums, allowed misalignment and the insulating construction at holes, edges and bends. A nominal spacing that looks favorable in a field model is not enough if the assembled tabs must splay apart to reach the module.

For the related heavy copper board, define the board stackup and joint geometry that form the same current path. The Best Technology busbar PCB design article covers broader board integration. The product drawing and contract should identify the applicable board performance requirements, for example IPC-6012 for qualifying a rigid board where specified; that does not qualify the separate busbar insulation or the assembled loop.

Double pulse test waveforms

On a qualified laboratory setup, compare turn-off voltage and current at the same reference points under comparable DC-link voltage, current, device temperature and gate-drive conditions. An apparent improvement can come from a slower current edge, a different measurement loop or probe error. Log the current slope, peak voltage, ringing and exact setup with each trace. A bench switching waveform by itself does not certify insulation, thermal performance or behavior over all operating points.

Verification evidence before design release
Evidence	What it answers	What to hold constant or record
Simplified overlap estimate	How the straight section responds to geometry changes.	Plate length, width and separation; model omissions.
Field extraction or impedance measurement	Whether termination and connection geometry dominate the path.	Port locations, fixture treatment and frequency range.
Switching waveforms	Whether peak stress meets the design budget on a representative assembly.	Switch, gate drive, DC-link voltage, current, temperature and probe reference.

Release the change only after representative switching conditions meet the project’s documented voltage margin. If the model improves but the waveform does not, revisit the capacitor path, the terminal transition and measurement setup before another copper revision.

FAQ

Does thicker copper automatically lower the switching-loop inductance?

No. It can lower resistance, but the proximity and continuity of the opposing current paths drive much of the geometric inductance.

Why can the nearest capacitor still behave as if it is far away?

Its effective path includes both terminals and the complete return. A short positive lead with a long negative return can still produce a large loop.

Can a busbar have low DC resistance and high switching overshoot?

Yes. Voltage drop in steady operation and inductive voltage during fast current change are different measurements.

Is a low supplier inductance number enough to release the assembly?

No. Ask where it was measured and whether it includes the joints, module and capacitor path used in the final assembly.

Can I fix poor geometry by adding more bulk capacitance?

Not necessarily. If the extra capacitor is coupled through the same high-inductance path, it may affect slower ripple more than the switching edge.

Does a tighter laminated stack always help?

It can reduce the straight-section inductance, but an insulation or assembly constraint may set the minimum spacing. The tabs can still dominate.

Is busbar inductance the same as gate-loop inductance?

No. The gate-drive loop is a separate path with its own reference and geometry. Improving the power path does not automatically correct gate ringing.

What belongs in a fabrication review package?

Send the assembly drawing with terminals, board stack, current-loop sketch, any insulation constraints and the switching conditions used for your limit.

Prepare a heavy copper PCB review

Contact Best Technology at sales@bestpcbs.com with your stackup, terminal drawing and current-loop sketch. Identify whether you need a board-based current path or an external busbar interface so the mechanical and board constraints can be reviewed together.

Tags: Commutation Loop Inductance, heavy copper pcb, Laminated Busbar, Power Electronics
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Power Rail Ripple: Is the Noise on the Board?

November 14th, 2026

Before changing a capacitor to fix an apparent power-rail spike, capture the same rail with a short probe return and measure the setup’s own noise. If the spike changes when you move the probe loop but the board and load stay the same, investigate pickup first. If the measured ripple is close to the instrument floor, report the result as unresolved until a suitable measurement can separate them.

Oscilloscope and low-voltage PCB on an electronics bench — Keep the board operating conditions fixed while testing the measurement setup. Illustrative bench scene.

Power Rail Ripple: Identify the Size and Time Scale

Ripple is a periodic variation riding on a DC rail. A switched converter can also show fast switching spikes, a slower burst envelope and unrelated broadband noise. These features need different measurement windows. First ask whether the requirement limits periodic ripple, all noise within a specified bandwidth, or movement during a load change.

For this guide, consider an earth-compatible 3.3 V rail on a low-voltage converter board. The task is to judge its running ripple at the load, not probe its switching node or a mains-referenced circuit. The Best Technology DC-DC converter test guide covers the separate startup, regulation and transient checks.

Power Supply Ripple Measurement: Fix the Test Boundary

Choose a rail-to-local-return point based on the product requirement. The converter output capacitor and the load pins can see different ripple because current flows through traces and vias. If both matter, record both as separate measurements. Hold input, load, operating mode and temperature constant during probe comparisons.

Save the coupling, bandwidth, attenuation, sample rate, acquisition mode and duration with the raw waveform. Use a window long enough to include the slow behavior of interest without sacrificing the sampling needed for fast edges. A different burst mode, scope setting or measurement location can change the result even when the board is unchanged.

Oscilloscope Ground Spring: Test for Pickup

Oscilloscope probe and short ground contact beside PCB output capacitors — A short, local return reduces measurement loop area. Illustrative detail, not a wiring instruction.

A long return lead adds loop area and inductance. It can pick up fields from the switch node or create ringing in the measurement. Compare the original setup with an approved low-loop-area connection at the same pads. TI SNVA871 includes an example of probe-connection effects. A smaller spike after the swap does not prove that all remaining noise belongs to the board.

Check the return potential before connecting a ground spring. On an earth-referenced oscilloscope the probe ground can tie the circuit to protective earth. Never defeat protective earth or attach the return to a floating or switching node without a rated, appropriate measurement arrangement.

Power Rail Probe: Choose the Setup for the Signal

Use a probe with adequate offset, sensitivity, loading and bandwidth for the rail. A large attenuation ratio can make small signals harder to resolve. A direct 50 Ω termination is not a default: it can draw current, shift the DC rail or exceed the input rating. Follow the probe and instrument documentation.

Ground spring vs rail probe vs rated differential measurement
Setup	Use when	Verify first
Passive probe with local spring	The return is earth-compatible and signals are comfortably above the setup floor.	Loop area, attenuation and tip position.
Dedicated rail probe	Small AC variation rides on DC and offset or loading limits the passive setup.	Offset and input limits, noise floor and loading.
Rated differential or isolated arrangement	The reference cannot safely be tied to earth.	Common-mode range, ratings and rejection at frequency.

Oscilloscope Noise Floor: Save Two Control Traces

First capture an input-referred baseline with the probe input connected to its return according to the instrument’s instructions, away from the switching field. Use the same vertical scale, coupling and bandwidth as the live trace. Then, where the fixture and equipment allow it safely, capture a local same-node null near the operating board with both contacts on the permitted reference. It can reveal pickup present near the board even when no intended differential signal is applied.

Do not subtract peak-to-peak values. As a separate RMS example, a 4.0 mV RMS reading and 3.0 mV RMS baseline would imply about 2.65 mV RMS for uncorrelated contributions with the same bandwidth, using √(4² − 3²). This cannot remove coherent switching pickup, recover an overlapped signal reliably or justify release near a limit. These are assumed readings. A lower-noise setup is preferable when the difference is small. See Keysight’s power-rail measurement note.

Oscilloscope Bandwidth Limit: Report Two Captures When Needed

Use the bandwidth specified by the acceptance requirement. If the requirement says 20 MHz, make the comparable capture at that setting. A wider-band screenshot can help investigate spikes but does not have the same pass/fail limit. Conversely, a bandwidth-limited trace cannot establish that troublesome high-frequency content is absent.

AC vs DC Coupling Oscilloscope Settings for Ripple

AC coupling removes DC, but the input high-pass response can distort slow envelope changes and load droop. DC coupling with suitable offset preserves the DC level and slow variation if the signal fits the input range. For this 3.3 V rail, record both the steady ripple view and a DC-coupled view if the question includes burst behavior or absolute rail limits.

Peak to Peak Noise: Decide What Can Be Reported

Peak-to-peak is the difference between the largest and smallest captured values. A longer acquisition can include a rare transient that a shorter one misses. Make a comparison with the same capture length and bandwidth, then keep unusual events as separate evidence. Report RMS and peak-to-peak separately, not as interchangeable values.

Match the observation to the next measurement
Observation	Next check	What to report
Spike tracks probe orientation or appears on the local null.	Reduce loop area and repeat the controls.	Pickup suspected; no board conclusion yet.
Live trace nearly matches the setup baseline.	Improve sensitivity or use a lower-noise measurement chain.	Not resolved at the current settings.
Feature repeats with verified connections and tracks converter operation.	Compare against the specified test condition and limit.	Report waveform, settings and evidence of a repeatable board feature.

FAQ

Is a triangular waveform required for a buck converter?

No. Operating mode, output network and measurement settings can change its shape.

What is the first check when a spike looks too large?

Check the return geometry and capture a suitable null before changing the board.

Can I subtract the baseline peak-to-peak value?

No. The maxima and minima generally do not occur at the same times.

Is 20 MHz the right bandwidth for every rail?

No. Match the product or instrumented test requirement, and label any wider diagnostic capture separately.

Why does the ripple disappear with AC coupling?

Slow variation can be filtered out. Verify the lower cutoff and use a supported DC-coupled setup if needed.

Can a multimeter establish absence of ripple?

Not by itself. Its measurement bandwidth and function may not capture the events you need to measure.

Should I measure at the converter or at the load?

Use the specified point. If both matter, label and compare them separately.

What should I put in a ripple test report?

Include the test points, load and mode, probe connection, settings, baseline, waveform and limits.

Discuss Your PCB Power Integrity Review

For a Best Technology fabrication or assembly discussion, send the board revision, stackup, probe-point photos and test requirements to sales@bestpcbs.com. Include both the live and control traces if you are comparing a layout change.

Tags: Oscilloscope, Power Integrity, Power Rail Ripple
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PCB Thermal Spreading Resistance: A Practical Guide

November 14th, 2026

Before adding copper to a hot PCB, measure where the temperature drops. A hot region beside the device and a much cooler region on the same plate suggest a spreading bottleneck. A large drop across the mounting interface points to contact or interface material. If the whole heat sink is hot relative to the incoming air, work on heat rejection first. These problems can coexist, so hold the dissipated power constant while you compare changes.

Power circuit board, copper spreader plate and finned heat sink on a bench — The board, spreader and heat sink can address different parts of one heat path. Illustrative hardware.

Thermal Spreading Resistance: Why the Source Footprint Matters

Thermal spreading resistance is the extra resistance associated with heat flowing from a small source into a larger body instead of travelling straight through a uniform cross-section. Heat near the source must turn sideways to reach more of the plate. The source footprint, its position, the plate thickness and the cooling boundary all affect that flow. A high-conductivity plate can still have a local hot spot.

When a board uses an insulated metal substrate, the component, solder, foil, dielectric and baseplate each influence the path. A large aluminum base does not help as much if heat cannot reach it through the small area where it enters the board. The University of Waterloo spreading-resistance research explains why the source and boundary conditions are part of the result.

Thermal Resistance Calculation Example: Separate the Drops

In a hypothetical steady-state 6 W power-board test, assume most of the heat exits through the base. Readings are 82 °C near the source on the plate, 70 °C on the plate at a specified transfer region, 65 °C on the sink side of that region, and 40 °C in the incoming air. The 12 °C plate gradient is about 2.0 K/W when divided by the total 6 W. It is a diagnostic indicator, not the analytical spreading resistance of the material.

Temperature drops in the same assumed 6 W test
Measured region	Drop	First area to investigate
Near-source plate to transfer region	12 °C	Footprint, plate continuity and spreading geometry.
Across corresponding mounting faces	5 °C	Interface compression, flatness and contact.
Sink base to incoming air	25 °C	Heat-sink size, orientation and airflow.

None of those points is the semiconductor junction. If a second route through the package or PCB carries significant power, dividing by total power does not isolate a segment resistance. Nor should you add lateral and through-interface temperature differences from arbitrary points as if they were all on one series path. Mark the sensor locations in the report.

Heat Spreader vs Heat Sink: Choose the Part That Changes the Right Drop

A spreader distributes heat over a wider area. A heat sink helps release heat to air or another cooling medium. A finned sink can perform both roles at its base, but the mechanisms respond to different changes.

Heat spreader vs heat sink vs mounting correction
Change	Choose it when	Check the trade-off
Improve the spreader	The hot region is concentrated while unused plate area stays cooler.	More metal adds mass and may not improve the component-to-plate entry path.
Improve the heat sink or airflow	The sink is broadly hot relative to incoming air.	Size, orientation, fouling and enclosure pressure loss affect cooling.
Improve contact	A temperature drop concentrates across the mounting joint.	Pad thickness, pressure, isolation and mechanical tolerances must all work together.

PCB Copper Thickness: Check the Continuous Path

Additional copper can improve lateral conduction only where it stays connected to the source and reaches a useful cooling area. A large plane fed through a narrow neck, split by a clearance or reached through poorly coupled layers may offer less benefit than its area suggests. Review the as-built conductor width, copper thickness and dielectric separation together. onsemi AND8432 discusses the influence of uninterrupted spreader area and thickness.

For a powered copper path, IPC-2152 informs conductor sizing for the allowable temperature rise. It does not quantify the device-to-spreader temperature drop. Do not connect extra copper to a switching node merely to gain thermal area; verify the electrical, isolation and EMI consequences.

Thermal Interface Material: Check the Installed Joint

The material’s conductivity is only one variable. Thickness after compression, actual contact area, flatness and local pressure change the mounted result. A thicker pad may bridge a real gap, yet add more through-thickness resistance than a thinner material in a flat joint. Use the specified bond line and do not remove an electrical insulating layer without an approved isolation design.

For the 6 W example, a mounting change is meaningful if the temperature on the source side falls while the heat sink, workload and cooling conditions stay comparable. A cold sink alone is ambiguous: it can indicate effective cooling or a poor path preventing heat from reaching it.

Heat Sink Thermal Resistance: Use the Real Air Boundary

Use the incoming air temperature near the installed sink instead of a distant room measurement. The enclosure may recirculate warm exhaust. Compare installation orientation and airflow with the datasheet condition, and account for nearby heat sources. The apparent sink-to-air value in the example is 25 °C ÷ 6 W, about 4.2 K/W, only under the assumption that essentially all 6 W reaches that sink.

PCB Thermal Simulation: Model the Bottlenecks Explicitly

Start with the real heat-entry footprint, layer geometry, material properties, contact thickness and cooling boundary. A one-dimensional estimate through a uniform layer can give a useful reference, but it does not capture spreading from a small device. Change one input at a time to see whether a thicker spreader, a better interface or stronger convection offers the greatest improvement. Correlate temperatures at multiple locations before using the model to approve a new design.

Keep package metrics separate from board results. The TI thermal metrics guide explains why the quoted junction-to-ambient value depends on the test setup. Use an applicable characterization method when estimating junction temperature.

PCB Thermal Testing: Verify the Change at the Same Power

Circuit board mounted to a plate with thermocouple leads and a thermal camera nearby — Repeat measurements at fixed locations and under the same load. Illustrative bench, not a test record.

Run the baseline and revision to the same steady-state criterion. Record actual component loss, air temperature, mounting torque where specified, and the point and method of each measurement. For infrared readings, account for emissivity and reflections, particularly on bare copper or aluminum. Confirm critical temperatures with suitable independent sensors or the device’s validated temperature proxy.

In the example, approve a spreader change only if it improves the required device or local margin without creating another hot spot or violating electrical constraints. Record the base construction and interface so the result can be reproduced on production hardware. The BestPCBs thermal pad MCPCB guide covers board construction choices for the next design review.

FAQ

Is a copper spreader always better than aluminum?

No. Conductivity helps, but footprint, geometry, mounting and downstream cooling control the overall result.

Is spreading resistance the same as junction-to-ambient resistance?

No. It refers to a local heat-flow mechanism; junction-to-ambient includes the larger assembly and test environment.

Can more thermal vias fix every hotspot?

No. Vias improve a vertical path only when they connect usable spreading layers and a downstream cooling route.

Does a cooler heat sink prove the board runs cooler?

No. It may receive less heat because of poor contact. Compare the source and both interface sides.

Does a larger plate always reduce thermal resistance?

No. Extra area helps only if heat can reach it and leave through a useful cooling boundary.

Can I measure bare copper directly with an infrared camera?

Validate the measurement first. Reflections and low emissivity can make an uncorrected reading misleading.

Can I compare two builds at different power levels?

Use matched power whenever possible. Changing operating point can also change losses, airflow and heat partition.

What should I send for a thermal layout review?

Send the stackup, source footprint and dissipation, contact construction, operating conditions and marked temperature locations.

Discuss Your Metal Core PCB Heat Path

For a Best Technology manufacturing review, send the approved PCB revision, metal base and dielectric requirements, mounting drawing and thermal observations to sales@bestpcbs.com. Identify the temperature drop the board change is intended to reduce.

Tags: MCPCB, PCB Thermal Testing, Thermal Spreading Resistance
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MCPCB Solder Voids: Why the Same 15% Can Differ

November 14th, 2026

Two power assemblies can both show 15% projected solder voiding and still need different decisions. A single void beneath the main heat-transfer area can interrupt a larger share of that local path than several small voids near its edges. First confirm that both images used the same pad boundary. Then compare void location and size, and verify temperature under the same operating conditions. The percentage alone does not prove a thermal pass.

Surface-mounted power package on an aluminum-backed circuit board — The solder joint under the exposed package pad is hidden after assembly. Illustrative bench scene.

Metal Core PCB Stackup: Trace the Heat Path First

On a typical insulated metal substrate, heat flows from the package through its exposed pad and solder, then through the upper conductor and insulating dielectric into the metal base. The base may then transfer heat into a housing through a separate interface. A direct-thermal-path design can bypass the dielectric locally, but it still depends on the solder joint where the component meets the board.

In the motor-controller example below, assume the device is electrically and thermally connected at its exposed pad. Verify that requirement with the device drawing: depending on the part, the pad may be connected to ground, a power node or another specified potential. The metal base must not be treated as that net unless the approved construction makes the connection intentional. The thermal pad MCPCB guide explains those stackup choices.

Exposed Pad Soldering: Separate the Three Interfaces

The exposed package pad is not a soft thermal gap pad, and the solder underneath it is not the board-to-housing interface. A hot device can result from poor solder contact, the board dielectric, or uneven enclosure contact. Changing stencil openings will not fix an uneven heatsink fit. When troubleshooting, record device power and mounting conditions before comparing X-rays from two assemblies.

Use the exact package drawing and the supplier’s attachment guidance to define the required soldered region and net connection. Board copper outside the intended joint does not belong in the void calculation. An edge fillet or a good visual inspection does not establish coverage beneath the package.

Solder Void X Ray: Read the Projection

A top-down 2D X-ray combines attenuation along the beam. The inspection software can outline regions with less solder within a specified joint area. The resulting image is useful for screening, but does not locate a void in depth or prove that the two solder interfaces are fully wetted. Copper, features on the opposite side, and the metal base can change contrast.

Use the same orientation, magnification and segmentation settings when comparing units. Save the unannotated image plus the measured overlay. If bright spots track vias or repeat in features outside the pad, review the board data and image settings before counting them as voids. Document what the image could not separate rather than forcing a percentage for an unreadable region.

Solder Void Percentage: Use the Same Denominator

If the agreed evaluation region covers 20 mm² and the combined projected void area covers 3 mm², the total is 15%. Count overlapping projections only once in that total. It is an area fraction, not a volume fraction, and it cannot simply be multiplied by junction-to-ambient thermal resistance.

For a hypothetical central region of 6 mm², one 3 mm² void entirely inside it would cover 50% of that region. Six voids of 0.5 mm² outside the same region also give 15% overall but 0% inside the defined region. These assumed values show why the denominator and location matter; they are not factory data or acceptance criteria. Define a critical region using the package’s actual heat path or other approved evidence, not an arbitrary center circle.

Projected void percentage vs location in two example units
Finding	Unit A	Unit B
Total projected void area	3 of 20 mm² (15%)	3 of 20 mm² (15%)
Largest single void	3 mm²	0.5 mm²
Overlap with defined heat-transfer region	3 of 6 mm² (50%)	0 of 6 mm² (0%)
Next investigation	Verify central coverage and temperature margin.	Check edge wetting and confirm thermal performance.

QFN Thermal Pad Voiding: Check the Actual Heat-Transfer Area

A large central void may be of greater concern if heat enters the pad mainly there. But an edge void can matter if it overlaps a critical portion of the electrical termination, disrupts solder wetting, or is subject to mechanical loading. The package drawing and thermal evidence, not the image center, determine which region deserves a separate evaluation. The Reliability Study of Bottom Terminated Components examines voiding and heat transfer on specific test assemblies. Its results are not a release limit for the devices in your build.

3D X Ray PCB Inspection: Know When to Escalate

Shielded electronics X-ray inspection equipment next to a sample board — Select the inspection method to resolve the uncertainty. Illustrative equipment scene, not a measured radiograph.

Use an additional angled image if overlap obscures the pad outline or a nearby feature. If the depth of an indication changes the disposition, ask whether computed tomography can resolve it on this stackup; dense metal may limit usable contrast. A targeted destructive cross-section can verify the interface in the chosen plane, but cannot represent the entire joint on its own.

2D X-ray vs CT vs cross-section
Method	Best use	Limit
2D X-ray	Compare projected area and distribution across units.	Overlapping features can mask depth or boundaries.
CT	Separate features through depth when resolution permits.	Metal and acquisition conditions affect visibility.
Cross-section	Inspect wetting, interfaces and thickness in a chosen slice.	Destructive and local, not a full-pad map.

Solder Paste Stencil Design: Test One Change at a Time

Segmented apertures can change how paste deposits coalesce and how gases escape as solder melts. Do not infer the correct paste coverage from the final void percentage: printed paste and reflowed solder are different measurements. Start with the exact package guidance and verify the actual deposits with solder paste inspection before reflow.

When Unit A repeatedly shows a central void, compare the baseline against one proposed aperture layout with the same paste, package lot, profile and fixture. If the void does not respond, investigate wetting or the measured reflow profile rather than reducing paste until the X-ray looks better. Confirm that the change does not create opens or insufficient attachment at other joints. TI SLUA271C explains exposed-pad stencil considerations for QFN and SON.

Thermal Testing: Verify the Margin Before Release

Test representative assemblies at the specified worst-case operating point. Hold power, ambient temperature, heatsink contact, airflow and measurement method constant between samples. Use the package’s characterized temperature proxy or another approved junction-temperature method; the temperature of the aluminum base alone is not a junction measurement. If Unit A shows worse margin, verify the finding across more units before assigning causality. If both pass, still apply all agreed workmanship and electrical requirements.

A release record should include the PCB and stencil revisions, lot, pad evaluation boundary, total and largest void, location rule, image and thermal test record. IPC-7093A covers design and assembly considerations for bottom-termination components. Use the applicable purchase requirements and verified package guidance to define the inspection method and limits; do not adopt a blanket percentage from an unrelated package.

FAQ

Does 15% voiding always pass?

No. It is an example, not a threshold. Apply the written limits and check the measurement method.

Does more paste always reduce voiding?

No. Changing deposit coverage can change gas escape, component seating and other joints. Test a controlled change.

Is a hot QFN proof of poor solder coverage?

No. Check electrical dissipation and board-to-housing contact as well as the hidden joint.

Can a 2D image show where a void sits through the joint thickness?

Not by itself. A suitable additional view, CT or a cross-section can address the specific uncertainty.

Can I skip paste on a difficult center pad?

Only if the package documentation and approved design permit a different attachment. A ground or cooling function may depend on it.

Can I compare images from different inspection programs?

Only after verifying that the boundary, calibration and segmentation are equivalent for that joint.

Is a central void always worse than an edge void?

No. Risk depends on how heat, current and stress pass through the actual joint.

Does passing the thermal test clear an X-ray reject?

No. Treat thermal performance and agreed inspection criteria as separate release gates.

Discuss Your MCPCB Assembly Review

For a Best Technology review, send the package drawing, MCPCB stackup, pad and stencil files, sample X-rays and test conditions to sales@bestpcbs.com. Identify the heat path and the decision the inspection needs to support.

Tags: MCPCB, Solder Voids, X-ray inspection
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Parallel MOSFET Current Sharing: Why One FET Runs Hot

November 14th, 2026

When one of two parallel MOSFETs runs hotter, do not start by adding more copper or changing the gate resistor. First measure the two branch currents during the flat part of the on-time, then compare the switching edges. A mismatch on the plateau points first to the fully enhanced resistance and power paths. A mismatch confined to the edges points first to gate drive, commutation inductance, or device timing. If current and switching losses are similar, look at the two thermal paths instead.

Two power MOSFET packages on a motor-control circuit board — Two power devices can share one electrical switch position without sharing current equally. Illustrative bench photograph.

MOSFETs in Parallel: When It Pays Off

Parallel MOSFETs share the drain and source nodes of one switch. Splitting current across two devices can lower conduction loss and spread heat. It also adds gate charge, layout area, and more opportunities for one branch to take a bigger share. It does not raise the voltage rating. Do not add two datasheet current ratings to obtain a board rating. If you are new to the device, start with this FET fundamentals guide.

Consider a 24 V motor driver that needs 40 A through the energized low-side switch position. One device might meet the requirement with a stronger package or better thermal path. Two devices are justified if the single device cannot meet the loss or temperature budget, and if the layout and driver can support two independently verifiable branches. This example uses assumed values throughout, not test data.

Parallel MOSFET Current Sharing

In the 40 A example, effective branch resistances of 3 and 4 mΩ give 22.9 and 17.1 A, not 20 A each. This is the fully on, fixed-temperature limit. Both branches see the same terminal voltage, so the lower resistance draws more current: I_A = I_total × R_B ÷ (R_A + R_B). Effective resistance includes the device and the separate copper, vias, solder joints and other interconnects between the common split and join points. Shared copper before the split does not enter this simple division.

At a switching edge, that equation is not enough. The first MOSFET to turn on can momentarily carry most of the load, even when the later plateau is nearly balanced. A device that turns off later can take disproportionate turn-off energy. Check the plateau and edges separately rather than judging the current split from a single average value.

Measurements that distinguish the three likely causes of a hot branch
Where the mismatch appears	First thing to check	What would confirm it?
Fully on, after the edge	Hot branch resistance and actual gate-to-source voltage	Separate millivolt measurements show a resistance difference large enough to explain the current split.
Turn-on or turn-off only	Local gate waveform and commutation path	A branch current peak lines up with a repeatable gate or drain waveform difference.
Temperature only	Heat flow into the board or heatsink	Electrical losses are similar, but the hotter device has a less effective thermal path.

MOSFET On Resistance vs Temperature

Use the expected hot R_DS(on) at the actual gate drive, not the headline room-temperature typical value. For the example, suppose the two device contributions are 2.5 and 3.2 mΩ, with the remainder in the respective interconnects. Using the currents above, device-only conduction losses are approximately 1.31 and 0.94 W during the on-state. For steady PWM plateaus, multiply by on-duty fraction as a first estimate; it excludes switching and reverse-conduction losses. The branch that takes 5.8 A more is not necessarily the branch with the worst junction temperature; heat removal still matters.

A fully enhanced silicon MOSFET often has increasing on-resistance with temperature, which helps steady sharing. Verify the curve for the selected part. Do not assume the same stabilizing effect while the device is only partly enhanced, such as during slow startup or linear current limiting. Check the time-dependent safe operating area for those conditions; a low on-resistance does not qualify a device for linear operation.

Parallel MOSFET PCB Layout

Start by tracing the two drain paths from the common node to the packages and the two source paths back to the common return. Match path resistance and inductance, not just trace length. Layer changes, via arrays, plane neckdowns and unequal pad entry can make two equal-length paths electrically different. Where one device is fed through the other device’s connection point, move the split so each receives a comparable path. Keep the gate loop and the high-current commutation loop short and check both.

For heavy copper, note the finished thickness by layer instead of relying on a nominal ounce designation. Check actual copper at narrowed pads and via transitions, and account for the copper that connects the switch to the local bus capacitor. IPC-2152 addresses copper conductor sizing and temperature rise. It does not prescribe a current-sharing tolerance between devices or certify the full assembly. For the 40 A board, compare four-wire branch drops on the sample and verify temperatures with the actual cooling conditions.

Parallel MOSFET Gate Resistor

Place a separate local series gate resistor at each MOSFET. A single resistor ahead of the branch point limits the overall drive, but does not provide the same damping between the individual gate loops. Start with equal, manufacturer-informed values and comparable gate paths. If one branch switches faster, investigate source bounce and layout before trying to cancel it with different resistors.

A larger gate resistor can reduce ringing and overshoot, but slower edges can increase switching loss. On the example board, adjust one design variable at a time and compare overshoot, branch current peaks and switching loss under the same conditions. Fixing the visible ringing alone is not enough if the switch then exceeds its thermal budget at the actual switching frequency.

Kelvin Source MOSFET: When the Sense Pin Helps

A Kelvin source pin gives the driver a separate source reference. In a three-terminal layout, the same source path often carries gate-return current and power current. A rapid change in the latter produces a voltage across the shared inductance, so the effective gate-to-source voltage at the die can differ from what a driver-side trace suggests.

For a package with a dedicated sense source, route the drive return according to the manufacturer’s recommendation. Do not divert load current into that pin. With a three-terminal package, a separate board return to the source pad can remove some shared PCB impedance, but it cannot remove shared inductance inside the package. Compare gate voltage at the device references before and after the layout change.

Parallel MOSFET Gate Driver

The driver must charge and discharge both gates. For two assumed 45 nC devices at 100 kHz, the mean charge drawn for the pair is about 9 mA per switch position. This is a switching-charge estimate, not a peak-drive specification. Select using the actual datasheet gate-charge conditions and account for driver output resistance, the Miller plateau, thermal limits and the required transition time.

Single MOSFET vs parallel MOSFETs vs a power module
Option	When to use it	What it costs or leaves to verify
One larger MOSFET	One package meets the conduction, switching and cooling targets.	Simpler drive and measurement, but heat is concentrated in one package.
Two discrete MOSFETs	There is room for matched branches and cooling, and the driver can handle both gates.	More gate charge and routing. Verify each branch at hot load and during edges.
Power module	A documented module construction fits the current and mechanical envelope.	Higher integration does not remove external bus or cooling limits. Check its terminal and mounting conditions.

Double Pulse Test Setup

A double-pulse test places a controlled load current in the inductive test circuit, then uses the switching events to reveal overshoot, ringing and switching energy. For a parallel pair, total current alone can hide one overloaded branch. Use repeatable, suitable voltage and branch-current sensing, confirm probe bandwidth and timing alignment, and check that the sensor does not add enough impedance to change the split. Follow the instrument and fixture safety requirements; measurements on energized power stages belong in a qualified lab.

Oscilloscope probes on a low-voltage power-switch evaluation board — Probe each branch with the same measurement setup before comparing its switching events. Illustrative bench photograph, not a test record.

For the 40 A design, establish separate acceptance limits before testing: plateau current per device, peak branch current, V_DS and V_GS excursions, loss and junction-temperature margin. Document the bus voltage, temperature, load, device lot, gate settings and probe positions. Compare cold and hot results, then run continuous PWM in the real assembly: a double pulse does not establish sustained thermal performance. Keep the PCB revision, finished copper specification and the test report together. If the heavy-copper stackup changes, recheck the measured branch balance rather than assuming that equal trace widths preserve it.

FAQ

Can MOSFETs in parallel double the current rating?

No. The circuit is limited by the more heavily loaded branch, its switching and temperature, and the board and cooling constraints.

Can two parallel MOSFETs use one gate resistor?

They can switch with a common resistor, but it does not give each gate loop local damping. Start with a resistor per device and verify the waveforms.

Why does one MOSFET run hotter at the same measured DC current?

Compare switching losses, hot on-resistance and the path into the board or heatsink. Equal mean current does not imply equal dissipation or equal temperature.

Does increasing the gate resistance cure drain overshoot?

It may reduce the switching slew rate, but overshoot can also come from the commutation loop or the measurement setup. Verify those first and retest losses after the change.

Does a Kelvin source pin make both branches equal?

No. It reduces common-source feedback in the gate loop; it does not correct differences in power paths or device parameters.

Can a thermal camera prove current is sharing?

No. Use it to locate hot areas, but compare electrical waveforms and account for surface emissivity and thermal paths. Case temperature is not junction temperature.

Can a sample pass a double pulse test and still overheat?

Yes. The test isolates switching events and does not establish continuous operating temperature. Run the assembled board at sustained duty, temperature and cooling conditions.

Can a second-source MOSFET be mixed into a parallel pair?

Only after comparing the exact part’s on-resistance versus temperature, gate charge, threshold spread, switching behavior, package and thermal conditions, then verifying the populated board. Similar headline resistance does not establish compatibility.

References

Discuss a High-Current PCB Layout

For a heavy copper PCB fabrication review with Best Technology, send the board revision, stackup, finished copper requirements, via arrays and the test points used to compare the two branches to sales@bestpcbs.com. Start with the path that must preserve the validated voltage drop or temperature margin.

Tags: Current Sharing, heavy copper pcb, MOSFET Gate Drive, Parallel MOSFETs
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VNA Time Domain Gating Guide for PCB Reflections

November 14th, 2026

Use VNA time domain gating to investigate a PCB reflection only when the response you want to keep is separable from the response you want to suppress. Start with the ungated measurement and a known reference. If the peaks overlap or the answer changes sharply with small gate adjustments, do not use the cleaner trace to release the board.

RF circuit board connected to a vector network analyzer on a laboratory bench — Illustrative RF bench. The reference plane determines which launches are inside the measured path.

VNA time domain gating

A vector network analyzer records complex values across frequency. The time-domain transform reorganizes that data by delay, so an engineer can look for reflections that arrive at different times. A gate then weights a chosen interval of the transformed response. Returning to the frequency domain shows how the adjusted response differs from the original measurement.

Imagine a 50 Ω RF test board with an SMA launch followed by a layer transition. The measured return loss has ripple. The question is whether a separately identifiable launch reflection contributes to it. The gate can help test that hypothesis, but it cannot make the physical launch disappear from an assembly that actually includes it.

S11 measurement using network analyzer

S11 is the reflection measured looking into port 1, with the other port terminated in the specified reference impedance. Measure magnitude and phase, and keep the port direction and termination fixed. A magnitude-only export loses the phase information needed for a conventional time transform.

For the example board, use the same termination and sweep for a known reference coupon and the board under test. If the launch end and far end look interchangeable, mark the connectors physically and keep the port map with the file. The first response is not necessarily the first board feature; it depends on where calibration stops.

VNA calibration

Calibrate at the plane you intend to use. A calibration at a cable end does not automatically remove an adapter or PCB launch added after that plane. Establish whether each item belongs to the test fixture or the product and keep that decision consistent through comparison and reporting.

After calibration, check a known termination or coupon appropriate to the setup. Reconnect it and check that its response stays within the variability your decision allows. If peaks shift when the cable is moved or an adapter is reseated, first resolve that repeatability issue. Smoothing an unstable connection does not improve its underlying measurement.

VNA frequency range

For the illustrative sweep from 2 to 12 GHz, the span is 10 GHz and the reciprocal-span scale is 100 ps. This is a planning scale, not the guaranteed time resolution. The Keysight time-domain guide distinguishes response resolution from distance range and shows the effects of span, window and transform mode.

Setting or parameter	Example	Check before using the gate
Usable frequency span	2–12 GHz; span 10 GHz	Only use bandwidth supported by the fixture and calibration.
Frequency step	10 MHz; 1,001 uniformly spaced points	Check time range and aliasing using the instrument’s transform settings.
Estimated local propagation speed	160 mm/ns, assumed	Obtain a value from the actual line structure or a reference length if localization matters.
Reflection separation	20 mm gives about 250 ps round trip	Verify that the two responses are resolved, not just farther apart than 100 ps.

For two discontinuities along the same line, the extra round trip gives Δt ≈ 2Δx/v. With the same assumed speed, two features 10 mm apart are only about 125 ps apart. If the window broadens each peak or the reflections overlap, neither the displayed cursor precision nor a narrower gate makes those features reliably separable. These are planning calculations, not instrument or BestPCBs specifications.

Time domain windowing

A frequency-domain window changes how each reflection appears in time. Reducing sidelobes generally broadens the main response. This can expose a weak isolated echo that was masked by sidelobes, yet make two nearby features harder to distinguish. Window type therefore belongs in the report alongside the gate settings.

Use the initial transformed plot to place the gate outside the visible response you want to retain, allowing for the response tails. Vary the setting modestly and inspect the resulting frequency response over the actual requirement band. If it moves enough to change the decision, the result is sensitive to processing. Keysight’s gating reference describes how different gate choices retain or reject selected time intervals.

Time domain reflectometry

Use a reflection-versus-time view to locate candidate discontinuities, then use the appropriate calibrated impedance or physical inspection method to confirm them. A VNA bandpass impulse plot is not a direct step-response impedance profile. In this example the sweep begins at 2 GHz, so a low-pass or DC-equivalent interpretation should not be assumed without a separately validated setup.

Coaxial connector attached at the edge of a bare RF circuit board — Illustrative coaxial launch. Correlate its expected delay with the ungated response before attributing any peak to it.

A second echo can be the result of energy bouncing between discontinuities, not a second component at the distance indicated by a simple ruler conversion. Compare a reference coupon and a known geometry change before assigning an unfamiliar peak.

VNA de embedding

Choose a method based on what the test is meant to prove. Time gating can investigate isolated responses at the existing reference plane; validated de-embedding characterizes fixtures and removes their modeled effect so results can be expressed at another plane. One does not automatically substitute for the other.

Approach	When to choose it	Evidence required
Ungated calibrated result	Product includes the launch or connector under test.	Show the full response at the specified plane and termination.
Time-domain gating	Estimate the contribution of a separately resolvable event.	Preserve raw data, gate and window; verify the result is stable when settings vary modestly.
Fixture de-embedding	Report the DUT at an internal plane with a characterized fixture.	Document the fixture and validate the method across the reporting band.

IEEE 370 addresses electrical characterization of PCB interconnects and related structures. The BestPCBs fixture de-embedding guide covers the separate question of removing fixture effects. Do not treat a gated curve alone as evidence of conformity to a de-embedding procedure.

VNA time domain analysis

For the example board, retain both results and annotate the calibrated reference plane, sweep, transform, window, gate limits and DUT orientation. Repeat the experiment after reconnection. If the ungated response fails and only the gated response passes, report both. Unless the acceptance document explicitly permits that gate and excludes the affected structure, use the specified acceptance result and keep the gated curve as diagnostic evidence.

When the launch and transition cannot be separated, do not keep narrowing the gate until the plot looks better. Consider a suitable wider sweep if the calibration and fixture support it, a reference coupon that isolates the launch, or a validated fixture-removal procedure chosen for the actual test boundary.

Frequently asked questions

Does moving a gate move the reference plane?

No. A gate weights time-domain responses. Reference-plane changes need a separate, appropriate calibration or correction.

Does adding points always separate peaks?

No. At a fixed span more points reduce the spacing between acquired frequencies, which can extend the useful time range. They do not add the bandwidth needed for finer response separation.

Can I use a gate after repositioning an SMA cable?

First check a known reference and repeatability. Cable movement may change the raw measurement before any gate is applied.

Is the largest peak always the faulty connector?

No. Check its arrival time and response to an independently verified fixture or geometry change. A strong reflection can also obscure a smaller nearby event.

Can I determine a distance without knowing the propagation speed?

Report the measured delay. To convert it to physical distance, use a justified speed and the correct reflection or transmission path convention.

Can I infer an impedance in ohms from any VNA time plot?

No. An impedance profile requires the correct calibrated response and processing. A bandpass impulse shows events, not a direct impedance value.

Why does the gated frequency response look worse near an edge of the sweep?

Finite bandwidth, transform and gate processing can affect the resulting response, including at band edges. Compare against the ungated data and the instrument’s guidance before reporting those points.

What belongs in a supplier handoff?

Send the coupon drawing, port map, reference plane, sweep file and acceptance rule. Keep the raw and processed traces separately labeled.

Discuss your RF test coupon

For a Best Technology fabrication review, share the coupon geometry, stackup, connector footprint and test boundary with sales@bestpcbs.com. Identify whether the product specification includes the launch.

Tags: PCB Reflections, RF PCB, Time Domain Gating, VNA Measurement
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Group Delay Guide for PCB Filters: When Ripple Is Real

November 14th, 2026

To decide whether group delay ripple comes from a PCB filter, first specify the passband, test boundaries and VNA aperture. Measure a known reference path and repeat the filter sweep under the same conditions. A flat insertion-loss trace alone does not prove that a modulated waveform passes through without distortion.

RF filter evaluation board beside a vector network analyzer — Illustrative RF test bench, not an actual measurement. Define whether the connectors belong to the device under test.

Group delay definition

Group delay describes how fast the transmission phase changes with frequency. In a band where transmission is strong enough and the phase slope is smooth over the signal bandwidth, it describes the delay of a narrowband signal envelope. The qualifier matters: a filter can delay different portions of a wide signal spectrum by different amounts, so a single number cannot describe what happens to the whole waveform.

Consider an illustrative receive-filter board for a radio near 1 GHz. The engineering question is whether the filter and its intended launches add more delay variation than the receiver allows across the occupied band. It is not whether a second PCB route matches the phase of the first route.

Group delay formula

Group delay is minus the derivative of unwrapped transmission phase with respect to angular frequency. In degrees and hertz, estimate it as −Δφ/(360 × Δf) seconds when Δφ is in degrees. This is a finite-interval estimate, not a guarantee that the slope remains constant between the two points.

For an instructional example, suppose unwrapped S21 phase changes from −82° at 995 MHz to −91° at 1,005 MHz. The difference is −9° over 10 MHz, giving +2.50 ns. If the instrument shows a phase jump at its display wrap boundary, do not use that displayed jump as the physical phase difference. See Keysight’s VNA group delay procedure.

Group delay vs phase delay

Use group delay to judge slope and waveform timing across frequency. Use phase delay only when the absolute phase and its reference convention are defined; a wrapped angle at one tone does not establish an unambiguous delay.

Metric	Evidence and conditions	Use it when
Phase delay	Negative phase divided by angular frequency, with a defined phase branch and reference plane.	You need the equivalent delay of an individual sinusoid under that convention.
Group delay	Negative phase slope, with stated frequency interval, reference plane and usable transmission.	You need envelope transit time or in-band delay variation.
Insertion loss	Transmission magnitude at the same reference planes and terminations.	You need amplitude loss or want to flag low-signal regions where phase becomes unreliable.

Group delay in filters

A filter can meet its amplitude mask and still delay parts of a waveform unequally. Inside the occupied band, variation in phase slope can smear a fast pulse or change the shape of a modulated symbol. Compare the delay curve with the system signal bandwidth instead of averaging over the entire instrument sweep.

For the receive board, check the occupied band with its allowed frequency offsets. A steep delay change outside that window may matter to a different operating mode, but it does not automatically fail the present mode. Conversely, do not arbitrarily trim an in-band peak simply to make the report pass.

Group delay ripple

Peak-to-peak group delay ripple is the maximum minus the minimum delay over the declared band, using the declared measurement setup. On the illustrative board, 2.80 ns maximum and 2.35 ns minimum give 0.45 ns peak to peak. If the project allows 0.40 ns maximum, that sweep exceeds the limit by 0.05 ns. It is not a confirmed defect until the measurement is suitable for separating that margin from setup variation.

Test entry	Example only	Reason to retain it
Acceptance window	990–1,010 MHz	Prevents a different sweep or stopband feature from changing the result.
Peak-to-peak limit	0.40 ns	States the actual release metric; an average is not a substitute.
Aperture and point spacing	2 MHz aperture; 0.25 MHz uniform points	Allows repeat sweeps with the same effective differentiation interval.
Decision conditions	Named reference planes, stable connections, reference sweep and repeat data	Helps judge whether a small apparent failure can be resolved.

VNA group delay measurement

Use a calibrated two-port transmission measurement and define whether connectors and launches belong to the DUT. Start with a known thru or reference coupon rated for the test band. It need not show zero delay; the concern is whether it exhibits unexpected ripple or changes on reconnection.

Keep the cables stable, use the same port power and terminations, and retain complex S21 plus the setup file. If the specification excludes the fixture, use a validated correction for its actual geometry; a simple electrical-delay adjustment is not a substitute for removing mismatch and fixture effects. The PCB fixture de-embedding guide covers how to define that boundary.

Group delay aperture

Aperture is the frequency separation over which the analyzer estimates the phase slope. A larger aperture smooths the curve but can hide a narrow feature; a smaller one resolves finer detail but can make phase noise more obvious. Do not confuse aperture with the spacing between acquired points. The instrument may express aperture as points, hertz or a percentage of span.

Coaxial cables connected to an RF test board on a bench — Illustrative test connection and screen display, not measured data. Keep the cable arrangement and reference planes fixed when comparing aperture settings.

As a diagnostic check, repeat the sweep with two supported aperture settings while keeping the acquisition band and calibration fixed. A sharp spike that moves with settings or follows a noise floor calls for better measurement evidence. A repeatable feature may still shrink under heavier smoothing, so use the prescribed aperture for the acceptance result. Save both traces. Keysight’s aperture note also explains why edge points can disappear for wider intervals.

Group delay dispersion

Before attributing delay variation to the board, check whether the shape persists inside the usable passband, after reconnecting the DUT, and on another representative board if the decision warrants it. Compare the trace with insertion loss and return loss: a feature near a deep transmission null can have unstable phase and should not be used as evidence of passband behavior.

For the example, record the raw S-parameters, selected band, aperture, calibration or fixture file, curve extrema and location of the highest variation. If the reference is stable and the DUT exceeds the fixed limit in repeat tests with sufficient measurement margin, hold disposition for design review. If the reference shows similar variation, resolve the measurement problem before changing the PCB.

Frequently asked questions

Why does the trace drop out at the sweep ends?

The slope calculation may need points on both sides of the reported frequency. Sweep beyond the acceptance band so there are adequate points on either side, while retaining the actual window in the report.

Does flat group delay have to be zero?

No. A uniform delay can shift the arrival time without spreading the envelope. Check any separate latency requirement before deciding that a large constant offset is acceptable.

Can an S21 magnitude-only export be used?

No. It lacks the phase needed for the slope. Export complex S21, with frequency and port information, when the analysis will be repeated off the instrument.

Does more point density always cure phase wrapping?

It can help if large phase steps caused the ambiguity, but extra points do not improve a noisy transmission null. Verify both the spacing and the usable signal level.

Why does reconnecting an adapter change the result?

It can change the effective reference path or introduce a mismatch that was not accounted for by calibration. Record the adapter and verify a reference sweep after the connection change.

Can a negative value alone prove a faulty RF filter?

No. First check the reference convention, transmission level and phase processing. In a strongly dispersive region the phase slope can also yield an apparent negative delay without representing a signal traveling backward in time.

Does a TDR impedance check replace the group delay sweep?

No. TDR can locate impedance discontinuities, while a group delay sweep verifies transmission phase slope over the specified band. Use the two checks for different questions.

What goes in the production handoff?

Send the test boundaries, passband, limit, aperture, point spacing, fixture revision and report format. Link each result to its board revision and test state.

Discuss your RF PCB requirements

For a Best Technology fabrication review, send the stackup, RF launch or coupon geometry, and the intended measurement reference planes to sales@bestpcbs.com. Identify which connector and fixture structures the design includes.

Tags: Group Delay, RF Filters, RF PCB, VNA Measurement
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Ceramic PCB Copper Peel Strength: Can You Compare Two Reports?

November 14th, 2026

Do not approve a ceramic PCB lot from a peel-strength number alone. First match the specimen construction, peel angle, speed, conditioning and reporting interval. Then check where the specimen failed. A copper strip that tears and a strip that separates cleanly at the ceramic interface do not establish the same result.

Suppose two suppliers submit reports for a power-module substrate. One lists 18 N for a 4 mm strip; the other lists 20 N for a 5 mm strip. The second asks you to approve its lot because its force is higher. Before deciding, normalize the force and check whether the tests were equivalent. All example numbers below are hypothetical.

Copper strip above a flat ceramic coupon in a laboratory fixture — Illustrative test setup. Verify which angle the fixture maintains during the evaluated travel.

Copper Peel Strength: What the Number Means

Peel strength is force per unit width under a defined peeling procedure, commonly reported in N/mm. The instrument pulls a prepared strip while the fixture controls its orientation. The recorded force can include bending or deformation of the copper as well as separation from the underlying structure. It is not a material constant or an allowable design load.

Define what the purchase drawing requires. A minimum sustained peel result at a named condition is not interchangeable with the maximum force reached while starting the strip. Ask for the trace or calculation interval when the report gives only one rounded result.

Peel Strength Test Method: Match These Inputs

Before comparing reports, make sure they describe equivalent specimens and the same test. The manufacturing route, ceramic grade and copper thickness all matter when the result is used for incoming acceptance.

Report field	What you need to check
Substrate and copper construction	Exact grade, bonding route, copper thickness and tested face
Peel geometry and speed	Actual angle, fixture arrangement and specified test speed
Specimen geometry	Measured strip width, preparation and position on the coupon
Condition and reported result	Temperature or conditioning, measured interval, statistic and failure location

90 vs. 180 Degree Peel Test: Compare the Geometry

At 90 degrees the peeled strip is drawn approximately perpendicular to the substrate face. At 180 degrees it is folded back along the plane in the opposite direction. The geometries load and bend the strip differently. Use the configuration named by the purchase specification or approved test plan; do not convert one result into the other with a fixed multiplier.

Method	When to select it	What to verify
90-degree peel	The production acceptance plan calls for perpendicular peeling.	The fixture maintains angle through the evaluated travel.
180-degree peel	The approved procedure calls for back-fold peeling and the strip can be prepared accordingly.	The strip does not fail prematurely during preparation or bending.

If neither method can produce a representative strip, ask for an approved alternative assessment and define a separate acceptance criterion. Do not reuse a peel limit for a different loading mode.

Peel Strength Calculation: Normalize Before Comparing

Divide the specified force statistic by the actual strip width. If the two hypothetical reports use the mean over the agreed interval, 18 N divided by 4 mm gives 4.5 N/mm, while 20 N divided by 5 mm gives 4.0 N/mm. The apparent ranking reverses after normalization.

That arithmetic still does not resolve the purchasing decision. If one report used a peak and the other used an average, or their peel angles differ, ask for a matched test. A normalized unit makes the comparison possible only after the method and specimen have been matched.

Peel Test Failure Modes: Inspect the Separated Surfaces

Record whether separation followed the bond, whether ceramic fractured or whether the copper strip tore. Retain photos of both sides with the specimen identifier and correlate the event with the force trace. A change in the trace is a reason to inspect; it does not identify the failure plane by itself.

If the strip tears before the specified interval is complete, do not enter its tear load as a normal bond-strength result. Apply the method’s invalid-test or alternative-reporting rule. If the procedure leaves the treatment unclear, retain the data and agree on a retest before release.

Separated ceramic coupon pieces and copper on an inspection bench — Illustrative specimens. In an actual report, retain images of both fracture faces and the specimen identifier.

DBC vs. AMB: Read the Datasheet Conditions

Rogers curamik technical data sheet 135-004, version 1.19 JP, page 2, lists at least 4.0 N/mm at 50 mm/min for its DBC construction with 0.3 mm copper and at least 10.0 N/mm at the same speed for its AMB construction with 0.5 mm copper. These are supplier-stated results for different constructions, not a controlled experiment isolating the bonding process or universal acceptance limits. See the curamik data sheet, “Copper peeling strength”.

For the power module, compare offers against the same assembly requirements rather than ranking bonding routes by their datasheet numbers. Request evidence for the exact build you would buy.

Thermal Cycling Test: Keep Conditioned Results Separate

An as-received peel result can support an incoming check. It does not establish adhesion after repeated temperature changes or prove the reliability of the assembled module. If conditioning is required, document the profile, number of cycles, specimen state, and acceptance method before the test.

Use matched specimens for the baseline and conditioned checks. Peel testing damages the specimen, so do not describe a before-and-after comparison as repeated measurements on the same already-peeled strip. If the failure location changes after conditioning, report that as well as the force.

Peel Strength Test Report: Decide Whether to Release

First verify that the report applies to the received lot and agreed construction. Then verify the method and calculate the specified result. Release only when the required measurements and failure reporting meet the approved criteria. If the suppliers used different methods, request a matched retest rather than applying an unverified conversion.

The Best Technology DBC yellowing test report is an example of reporting individual peel-force statistics and normalized strength. Its conclusion applies to the specimens in that report, not every discolored ceramic substrate.

Frequently Asked Questions

Is 4 N/mm a universal DBC minimum?

No. Use the limit and test procedure agreed for the actual construction.

Does a higher peak mean a stronger interface?

Not necessarily. The peak may reflect initiation or deformation. Compare the same defined interval and statistic.

Can 90-degree and 180-degree results be averaged?

No. They are different configurations. Report them separately unless a qualified procedure establishes equivalence for the specific application.

Why record copper thickness if the result is already in N/mm?

Dividing by width does not remove thickness-dependent bending or deformation.

What if I cannot peel the thin copper without breaking it?

Document that outcome and agree on a more suitable test and its acceptance criterion. Do not treat the tear load as a direct adhesion result.

Does a good peel result prove a ceramic card will pass insulation testing?

No. Use the agreed electrical test for the insulation requirement.

Can I apply an as-received report after thermal cycling?

No. Request the relevant conditioned evidence if it is required by the qualification plan.

What evidence helps resolve a supplier disagreement?

Send the approved drawing, lot identity, raw force traces, specimen dimensions, fixture details and photos of the failure surfaces.

References

EP4310065A1: ceramic composite substrate, example of perpendicular peel geometry. This is a documented test example, not a universally applicable acceptance standard.

Discuss Your Ceramic Substrate Acceptance Plan

Send the ceramic grade, copper construction, drawing and proposed test method to sales@bestpcbs.com for a Best Technology review. Identify whether the decision concerns a new material qualification or the release of a received lot.

Tags: AMB Substrate, ceramic PCB, Copper Peel Strength, dbc substrate
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