PCB manufacturing PCB manufacturing
Home > Blog

What Is Sequential Lamination in PCB and How Does It Work?

September 17th, 2026

Sequential lamination builds a PCB in two or more controlled lamination stages so internal vias can be formed before later layers make them inaccessible. The practical question is not how many layers the board has. It is which blind, buried, or microvia connections must be completed at each stage and what those choices mean for reliability, cost, and lead time.

sequential lamination, multilayer PCB cross-section beneath a lamination press

What Is Sequential Lamination in PCB?

A conventional multilayer PCB is usually bonded as one prepared stack. Sequential lamination pauses the build, forms connections in an accessible partial structure, adds another layer set, and continues outward.

A buried via can therefore be drilled and plated before later layers enclose it. Multi-level microvias follow the same logic: each lower tier is completed before the next dielectric covers its landing layer.

The deciding test is layer access. Trace every via from its drilling side to its target layer. If that connection can still be formed after the main bond, another build stage may be unnecessary. If the target becomes enclosed first, the stack must be divided into accessible substructures. Sequential lamination is therefore a construction sequence, not a performance grade.

How Is Sequential Lamination Different From Standard PCB Lamination?

The difference is when the internal connections are made. Standard construction completes most internal preparation before one main multilayer bonding stage. Sequential construction inserts drilling, plating, filling, or inspection between bonding stages.

Factor Standard Multilayer Lamination Sequential Lamination
Lamination process Mainly one multilayer bonding stage Two or more controlled build stages
Via structures Mainly through vias and structures accessible after bonding Buried vias, blind vias, and multi-level microvias
Layer access Internal layers become inaccessible after bonding Selected layers remain accessible between stages
Process complexity Lower when it meets the design Higher because controlled operations repeat
Cost and lead time Generally lower Generally higher
Typical use Conventional multilayer PCB HDI and complex internal via structures

A high layer count does not by itself require sequential lamination. A board with many layers and only plated through holes may use a conventional build, while a board with fewer layers but a buried via or several microvia tiers may need staged construction.

When Does a PCB Design Require Sequential Lamination?

Sequential lamination becomes necessary when a required connection cannot be drilled, plated, filled, or verified after the full stack has been bonded. Four design situations commonly create that condition:

  • Buried vias that would be sealed inside the finished stack: the via must be completed in a core or sub-composite while both target layers are still exposed.
  • Multiple HDI build-up layers: each added dielectric can create a new microvia level that must be formed before another layer is added.
  • Stacked or multi-level microvias: the lower microvia usually needs controlled plating, filling, and a planar landing surface before the upper level is built.
  • Fine-pitch BGA escape that cannot reasonably use through vias: adjacent-layer microvias can release routing area, but their start and stop layers determine the build sequence.

High layer count and the HDI label are not sufficient reasons by themselves. Hide the outer layers in the stackup view, add them back in build order, and note where a connection loses access before it is complete. That via map reveals whether staged construction is necessary and whether a routing change could remove a build-up tier.

How Does the Sequential Lamination Process Work?

The process follows the changing access to each via target. It starts with the innermost structure, adds a layer set, completes the connections that are accessible at that point, and repeats only when the stackup requires another tier.

sequential lamination, six-stage PCB build sequence on a white background
  1. Document the stackup and via spans. Identify every copper layer, dielectric, via start and stop layer, fill requirement, and controlled-impedance reference. The output is a build diagram that can be checked before routing is frozen.
  2. Build the initial core or sub-composite. Image and etch the inner copper, then align the partial structure. The layers that will support internal vias remain reachable.
  3. Drill and plate the internal vias. Form the buried holes or first accessible connections, then clean, metallize, fill, and inspect them as required. Their conductive path is complete before enclosure.
  4. Laminate the next layer pair or build-up layer. Add dielectric and copper to the verified partial structure. The result is a larger stack with a new outer surface available for processing.
  5. Form the next blind or microvia level. Drill and plate the newly accessible tier, using filling or planarization where another via must land above it. This completes the next connection level.
  6. Repeat as required and finish the PCB. Continue the add-layer-and-connect sequence for the remaining tiers, then complete final through holes, outer-layer processing, solder mask, finish, profiling, and the agreed testing.

This sequence explains the design consequence: adding or extending one via span can change the required build stages. It may add a fill dependency, alter which layer must remain exposed, or require another controlled cycle.

For the designer, the useful output is a confirmed build diagram: layer order, via levels completed at each stage, landing surfaces required by the next tier, and any geometry or material limit that changes the stackup.

How Do Different Via Structures Affect the Lamination Sequence?

Each via must be formed while its drilling side and target layer are accessible. The name of the via helps describe the connection, but the exact start-stop layers and stacking arrangement determine the sequence.

sequential lamination, cross-sections of through blind buried stacked and staggered vias
  • Through vias: these normally pass through the completed stack and can be drilled after final lamination, so they do not create a sequential stage by themselves.
  • Buried vias: these connect internal layers and must be processed before later layers hide both ends.
  • Blind vias: these connect an outer surface to an internal target. Their route depends on the depth, dielectric thickness, drill method, and stage at which the target is exposed.
  • Single-level microvias: these usually connect adjacent layers through a thin dielectric and may fit within one build-up stage.
  • Stacked microvias: the upper microvia lands directly above the lower one, creating a fill and planarity dependency between tiers.
  • Staggered microvias: the levels are offset, which avoids a direct via-on-via interface but does not necessarily remove the need to build each dielectric tier in sequence.

Do not assign a cycle count from terms such as blind via or HDI alone. Two boards can use the same via label yet require different sequences because the vias stop on different layers or use different fill and stacking arrangements.

How Does the PCB Stackup Determine the Number of Lamination Cycles?

The cycle count follows the number of connection groups that must be completed before another layer blocks access. Total layer count matters less than the order in which via targets disappear inside the stack.

Notation such as 1+N+1 or 2+N+2 shows the build-up layers around a core region, but it does not prove a universal press count. The core may contain buried vias, and outer tiers may be stacked, staggered, symmetric, or one-sided. The notation shows the layer arrangement; the via start-stop map shows the build dependencies.

Three simplified cases show how that logic changes the build:

  • Eight-layer board with through vias only: the prepared layers can normally be bonded in the main multilayer lamination, followed by through-hole drilling. The layer count does not create another stage by itself.
  • Core containing buried vias: the internal via is drilled and plated while its core or sub-composite is accessible. Outer layers are laminated only after that connection is complete, so the via architecture creates a staged build.
  • 2+N+2 HDI with stacked microvias: the first microvia tier must be formed before the second build-up dielectric covers it. Direct stacking can also require a filled, planar lower via before the upper tier is added.

Estimate the sequence from the inside out:

  1. Map every start and stop layer. Separate through, blind, buried, and microvia spans.
  2. Group connections that are accessible together. Vias that can be formed in the same exposed sub-composite may share a stage.
  3. Mark each covering event. When a new dielectric hides a completed target, record the lamination needed before that happens.
  4. Add stacking dependencies. A microvia tier that needs a filled, planar lower via must be completed before the next tier can begin.

If two proposed builds show different cycle counts, compare their layer-by-layer diagrams, via formation stages, and fill sequence before treating either number as correct.

What Should You Check Before Finalizing a Sequential Lamination Stackup?

Review the stackup before dense routing makes the construction difficult to change. The goal is to prove that every added tier solves a real routing or electrical constraint and that its build dependency is understood.

  • Via start and stop layers: make the CAD data, drill table, and cross-sectional stackup agree.
  • Stacked or staggered arrangement: confirm whether direct stacking is necessary or an offset path can meet routing and reliability needs.
  • Number of build-up tiers: test whether a routing change, another conventional layer, or a different escape pattern can remove a tier.
  • Material system: check whether cores, prepregs, build-up dielectrics, and copper constructions suit the planned press and assembly thermal history.
  • Impedance and reference layers: protect return paths, reference-plane continuity, dielectric targets, and any backdrill requirement when the build changes.
  • Reliability requirements: state the product environment, assembly exposure, acceptance class, coupon needs, and qualification expectations.

Generic online limits should not be copied directly into CAD rules. Usable geometry depends on the material, dielectric thickness, copper, drill and fill process, registration capability, and product requirement. For a useful DFM or quotation review, send the stackup, via map, fabrication data, quantity, and reliability requirements together.

How Can Multiple Lamination Cycles Affect PCB Reliability?

Extra cycles add thermal, pressure, and registration exposure. That does not make a sequentially laminated PCB unreliable by definition, but it reduces the value of judging the design by layer count or a room-temperature electrical test alone.

Risk area Why multiple cycles matter What to verify
Microvia interface Repeated thermal exposure can reveal weak plating, fill, or target-pad interfaces Via structure, fill route, representative coupons, and qualification method
Layer registration Alignment error can accumulate as more structures are bonded Capture pads, registration allowance, and evidence from intermediate stages
Material thermal history The laminate experiences repeated heat and pressure before assembly reflow Material suitability for the full fabrication and assembly history

Risk is often concentrated at interfaces: a microvia base meeting its target pad, a filled via supporting an upper tier, or resin bonding around uneven copper. Residue, voids, weak plating, poor planarity, expansion mismatch, and registration error can reduce margin during reflow or thermal cycling.

Qualification should represent the connections with the greatest structural dependency. Match the coupon or test vehicle to the microvia tiers, target-pad interfaces, fill arrangement, materials, and expected assembly exposure. A room-temperature continuity check confirms a path at that moment; it does not reproduce repeated reflow or service thermal cycling.

How Does Sequential Lamination Affect PCB Cost and Lead Time?

Cost and lead time usually rise because pressing, drilling, plating, filling, planarization, and inspection may repeat for each build stage. There is no reliable universal percentage; the impact depends on the stackup, material, panel use, via density, registration demand, testing, and quantity.

  • Repeated controlled operations: each added tier consumes equipment time and requires another alignment and processing sequence.
  • Fill and planarization: stacked structures may need a prepared landing surface before the next level can be formed.
  • Intermediate verification: hidden circuitry and via quality need to be checked before the next layer removes access.
  • Longer dependency chain: later work cannot begin until the preceding structure is complete and suitable for the next tier.
  • Greater late-stage loss: a defect found after several completed stages affects more accumulated processing than an early defect.

The best cost reduction is often one unnecessary build-up tier removed before layout release. Compare alternatives that preserve the same electrical and mechanical requirements, such as fewer unique via spans, staggered rather than stacked microvias, a different BGA escape, or an added conventional layer.

FAQs About Sequential Lamination Technology

Q1: What files help a supplier quote the actual build instead of making assumptions?

A1: Send one consistent data package. Include Gerber or ODB++ data, NC drill data, a controlled stackup, via start-stop layers, finished copper weights and board thickness, material and impedance requirements, via-fill or cap requirements, acceptance and test expectations, quantity, and target delivery date.

Q2: How should blind and buried via spans appear in the drill data?

A2: Every start-stop layer pair must be unambiguous. Separate drill files or a clearly mapped drill table can be used, but each span should identify its layer pair, plated status, finished size, tolerance, and any fill or cap requirement. The naming convention matters less than agreement between the drill data, stackup, and fabrication drawing.

Q3: Can stacked microvias be changed to staggered microvias without design approval?

A3: No. The alternative may improve the build margin, but it changes pad locations, routing space, and possibly reference-plane or impedance conditions. It should be proposed as a documented DFM change and approved in the controlled design data before production.

Q4: Why can two PCB quotations use different build sequences?

A4: The suppliers may be working from different assumptions or grouping operations differently. Compare the annotated build diagrams, via spans, fill and planarization route, materials, impedance construction, and test scope. A lower cycle number is not automatically the better or equivalent proposal.

Q5: Can an enclosed buried-via defect be repaired after final lamination?

A5: It is generally not a practical local rework. The connection is trapped inside the bonded stack, so opening it can damage surrounding layers and dielectric. Intermediate inspection, representative coupons, and final electrical testing are used to find problems; an affected bare board is usually rejected or rebuilt rather than patched.

Ready to build a sequential-lamination PCB? Send your stackup, Gerber or ODB++ files, via map, material and impedance requirements, quantity, and target delivery date to sales@bestpcbs.com. EBest Circuit can review the proposed construction and prepare a PCB quotation based on the actual build sequence.

Tags: , , , ,
Posted in PCB Technology | No Comments »

High Frequency PCB in Switzerland: 10 Suppliers for Your RFQ Shortlist

September 17th, 2026

If you need a high frequency PCB in Switzerland, first determine where the board will be manufactured and whether that factory can process the specified laminate, stackup, impedance, and RF test requirements. The suppliers below cover Swiss production, European production, a Swiss sourcing office, and overseas manufacturing, so compare quotations by the proposed factory and scope rather than the company address alone.

This article gives you 10 suppliers to approach, explains how to use the list, and compares Swiss, European, and overseas sourcing. It also shows which RF capabilities, materials, stackup data, impedance limits, tests, files, and DFM answers to request before you compare quotations and approve production.

High Frequency PCB in Switzerland, microscope inspection of an RF PCB fixture

10 High Frequency PCB Suppliers to Consider for Projects in Switzerland

Start with these 10 suppliers, then narrow the list by manufacturing site, laminate experience, stackup fit, and available RF verification. Their supply models differ, so each quotation should identify where the board will be made and which site owns the RF process.

1. Optiprint AG, Switzerland

Optiprint provides a Swiss-manufacturing option from its Berneck operation. The company publishes high-frequency and PTFE PCB capability for Rogers, Taconic, and Neltec materials, mixed-dielectric multilayers, and metal-core or metal-backed constructions. Include it in the RFQ when Swiss manufacture, direct local engineering contact, or a specialized PTFE construction is part of the sourcing requirement.

2. Fineline Switzerland AG

Fineline has a Swiss office in Lucerne and publishes RF PCB capability through a global network of audited manufacturing partners, including materials and constructions for frequencies up to 100 GHz. This is a sourcing and engineering route rather than proof of a Swiss factory. Ask the Swiss team to name the proposed plant, material source, test scope, and subcontracted operations before adding the offer to a factory-level comparison.

3. ACB, France

ACB publishes a dedicated RF and microwave PCB service supported by its French manufacturing operation. Its public information covers PTFE-based materials, hybrid constructions, multilayer RF boards, and work for microwave applications. Ask ACB to quote when the design needs a European RF specialist, then confirm the exact plant, laminate availability, and board-specific schedule during RFQ review.

4. Aspocomp, Finland

Aspocomp manufactures in Oulu and publishes high-frequency multilayer, PTFE, mixed-build, and HDI capability. That combination is useful when an RF section must coexist with microvias, dense interconnects, or a mixed RF/FR-4 construction. Public delivery information does not replace a stackup-specific schedule; the quotation still needs to tie material availability and timing to the proposed build.

5. AT&S, Austria

AT&S lists high-frequency PCBs up to 10 layers at its Fehring plant in Austria, alongside standard multilayer, HDI, flexible, semi-flexible, and rigid-flex technologies. This makes the site relevant when RF requirements sit inside a broader interconnect problem. The RFQ should name Fehring or another approved build site explicitly, because group capability should not be assumed to apply at every AT&S location.

6. Eurocircuits, Europe

Eurocircuits offers an RF Pool route for eligible 2- and 4-layer boards using I-Tera and Rogers materials, plus non-pooled options for other constructions. Its model is suited to prototypes and small quantities that fit a defined online manufacturing envelope, with manufacturability checking and electrical test included in that service. Designs outside the published envelope should be treated as a separate engineering quotation rather than forced into the pooled route.

7. KSG, Germany and Austria

KSG publishes high-frequency PCB production for 24 to 77 GHz applications, with 2 to 20 layers, PTFE and hydrocarbon materials, and homogeneous or hybrid multilayers. The capability is relevant to radar, sensing, and other designs in which etching control and material choice directly affect RF geometry. Buyers should still confirm which KSG factory will build the board and which combinations of material, layer count, thickness, and tolerance are available together.

8. Schweizer Electronic, Germany

Schweizer Electronic publishes RF technology paths for 6-24 GHz and 77 GHz and operates PCB production in Schramberg, Germany. Its profile is particularly relevant to radar and sensor programs that need high-frequency structures within an established European production route. Because the group also has manufacturing outside Germany, the quote should state the actual production and qualification site.

9. Teledyne Labtech, United Kingdom

Teledyne Labtech manufactures complex RF and microwave PCBs in the UK and publishes PTFE, LCP, mixed-dielectric, multilayer, metal-backed, and thermally managed constructions. It also offers assembly and RF test services, with an accelerated option for qualifying prototypes. Ask it to quote when the project needs specialist microwave fabrication or a closer link between bare-board manufacture, assembly, and RF verification.

10. EBest Circuit, China

EBest Circuit is a China-based PCB manufacturer supplying international projects, including deliveries to Switzerland. Published capabilities include Rogers and PTFE materials, Rogers/FR-4 hybrid constructions, controlled-impedance fabrication, prototypes, and production support. EBest Circuit does not claim a factory, warehouse, or branch in Switzerland, so buyers should evaluate it as an overseas manufacturing route and define the import and delivery boundary in the RFQ.

Before moving a supplier to the next round, obtain written confirmation of the manufacturing site, material, construction, test scope, quantity, and schedule. A capability page is enough to start the conversation, but the quotation must answer these project-specific points.

How Should You Use This Supplier List for Your RFQ?

Use the ten names as a first-round candidate pool, then send the same technical package to every supplier. A company should advance only if its reply connects your files to an identified factory, a buildable stackup, available material, and a defined verification plan.

  • Confirm the build site: ask for the legal entity, factory address, subcontracted processes, inspection location, and ship-from country.
  • Confirm material availability: request the exact laminate, bondply or prepreg, thickness, copper type, and any minimum buy or procurement delay.
  • Request a proposed stackup: compare dielectric thicknesses, reference planes, finished copper, RF layers, and all deviations from the supplied construction.
  • Define verification: state the impedance coupon, sampling, RF measurements, dimensional checks, raw data, and report format required for acceptance.
  • Match the production stage: separate prototype quantity, qualification lot, repeat order, and forecast volume instead of assuming one route fits all four.
  • Lock changes: require customer approval before a material, dielectric thickness, copper type, RF geometry, test method, or production site is changed.

A useful first-round response should expose open assumptions rather than hide them behind a unit price. Remove any candidate that cannot identify the factory or return a construction that can be checked against the RF requirements.

Should You Source High Frequency PCBs Locally or Overseas?

Choose the production region from the project requirement, not from a general belief that one country is always better. The correct route depends on contractual origin, engineering access, process fit, material supply, quantity, logistics, and the cost of qualifying a second site.

Switzerland-based manufacturing makes sense when the contract requires Swiss manufacture, the project needs close access to the production team, or the RF construction is available from a qualified Swiss plant. The RFQ should identify which operations must occur in Switzerland instead of accepting a Swiss invoice or sales address as proof of origin.

European manufacturing can provide a regional factory and shorter transport path while expanding the available RF process base. It suits projects that do not require Swiss-made boards but still want production within Europe. Check the actual plant, because a European sales or engineering office can still route work to a different country.

Overseas manufacturing is practical when the contract permits it and the supplier can return a complete digital engineering package. It may expand material, capacity, and commercial options, but the Swiss buyer must define importing, customs clearance, Incoterms, document ownership, nonconformance returns, and the approval required for any site transfer.

Location is one qualification field, not a substitute for technical review. Select the route that can meet the approved RF baseline and make its responsibilities clear from factory release through arrival in Switzerland.

Which High Frequency PCB Capabilities Should You Confirm First?

Confirm whether the proposed factory can manufacture the exact RF structure before discussing general company credentials. The answer should refer to a named site and to combinations that have been reviewed against your layer count, materials, geometry, and panel design.

  • Low-loss laminate processing: verify the named PTFE, hydrocarbon-ceramic, LCP, or other RF material family and the related drilling, plasma, plating, bonding, and surface-preparation route.
  • Mixed-dielectric multilayers: ask whether the factory can press the proposed RF material with FR-4 or another dielectric while holding the required finished thickness and registration.
  • Controlled-impedance fabrication: confirm field-solver review, coupon design, etching compensation, dielectric control, finished copper assumptions, and access to TDR data.
  • RF via structures: identify plated-through vias, blind or buried vias, via filling, via fences, backdrilling, and the residual-stub limit that the design requires.
  • Special mechanical construction: confirm cavities, metal-backed boards, coins, edge plating, depth routing, thin dielectrics, or oversized panels only when the drawing calls for them.
  • Registration and conductor control: ask for the achievable result for the proposed material and copper, not an isolated minimum trace value copied from a general capability table.

“We make RF PCBs” is not enough. The factory should either confirm the requested combination or return the limits and changes needed to make it manufacturable.

What RF Materials and Stackup Details Should Be Included in the RFQ?

Name the exact material system and define the finished construction that the electrical design assumes. “Rogers PCB” or “low-loss material” leaves too many variables open for suppliers to quote the same board.

High Frequency PCB in Switzerland, engineer reviewing RF laminate samples and a multilayer stackup
  • Laminate and bonding materials: manufacturer, product family, grade, core, bondply or prepreg, and approved source where the project controls it.
  • Electrical values: the Dk and Df used in design, including the data source, test method, frequency, direction, and whether the value is a design or process value.
  • Finished stackup: layer order, RF signal layers, reference planes, finished dielectric thicknesses, total thickness, and tolerance.
  • Copper definition: foil type or profile where relevant, starting copper, plating contribution, and required finished copper on each controlled layer.
  • Hybrid construction: the location of each RF and conventional material, bonding system, resin constraints, and any special sequential lamination.
  • Substitution rule: the parameters that must remain equivalent and the written approval required before any alternate material is used.

Ask every bidder to return its proposed stackup with the quotation. This exposes material or thickness substitutions before they become hidden differences in impedance, loss, phase, or lead time.

How Should Controlled Impedance and RF Performance Be Specified?

Specify the electrical result separately from the method used to test it. The fabrication drawing and RF requirement should say what the board must achieve; the inspection plan can then define how that result will be verified.

  • Impedance: list each single-ended or differential target, tolerance, layer, reference plane, trace structure, and controlled geometry.
  • Frequency: state the operating band and any harmonics, bandwidth, or sweep range that affects material selection or acceptance.
  • Loss: define insertion-loss limits, line length, frequency points or curve, fixture, connector, and de-embedding assumptions where loss is a purchase requirement.
  • Matching: state return-loss, phase, delay, amplitude-balance, or length-matching limits only for the nets and conditions that require them.
  • Critical transitions: identify launches, connectors, vias, layer changes, antenna feeds, filters, and reference-plane discontinuities that may control system performance.
  • Change boundary: mark trace width, gap, dielectric, copper, mask, via, and finish changes that require engineering approval before production release.

Performance requirements become comparable when they identify the controlled structure, operating condition, limit, and acceptance basis. A target such as “50 ohms” without a layer, tolerance, and geometry does not provide enough information for release.

What Testing and Inspection Should You Ask the Supplier to Provide?

Choose tests that can verify the risks in the released design instead of ordering every available inspection. The scope should follow operating frequency, sensitivity to geometry and material variation, product risk, and the customer’s acceptance criteria.

High Frequency PCB in Switzerland, RF test coupon connected to a laboratory measurement fixture
  • TDR and impedance coupons: define coupon ownership, representative layers and structures, calibration, sampling, reported values, and failure disposition.
  • Insertion loss, return loss, or S-parameters: request these only when the RF response is a purchase requirement, and define the test vehicle, ports, sweep, fixture, de-embedding, data format, and limits.
  • Microsection: use it to check plating, dielectric, copper, lamination, and via or backdrill features selected in the inspection plan.
  • Dimensional and X-ray inspection: apply these to registered layers, cavities, drilled features, hidden structures, or other RF-critical dimensions that cannot be confirmed visually.
  • Bare-board electrical test: require continuity and isolation testing, while recognizing that it does not prove impedance, insertion loss, return loss, or complete RF performance.
  • Material traceability: request laminate identity, lot or batch records, approved substitutes, and any storage or handling evidence required by the quality plan.

Standard bare-board electrical testing does not verify the complete RF performance of a high frequency PCB. The final plan should link each required test to a stated risk or acceptance criterion and identify whether it applies to first article, each lot, a sample, or periodic requalification.

What Files Should You Send for an Accurate High Frequency PCB Quote?

Send one revision-controlled package so every supplier prices the same board. Missing stackup, material, impedance, or test information forces each bidder to make different assumptions, which makes the returned prices impossible to compare fairly.

  • Fabrication data: Gerber or ODB++, NC drill and route files, netlist if available, and a fabrication drawing with revision identity.
  • Stackup: layer order, dielectric and copper targets, total thickness, controlled layers, reference planes, and allowed construction changes.
  • Material callouts: exact laminate and bonding materials, thicknesses, copper type, electrical-data source, and approved alternates.
  • Impedance and RF requirements: target table, tolerances, RF-sensitive geometry, operating band, loss or phase limits, and critical transitions.
  • Mechanical and finish requirements: outline, tolerances, cavities, backdrill, metal backing, connector interfaces, solder mask, legend, and surface finish.
  • Verification package: coupon, inspection, sampling, raw-data, report, certificate, traceability, and first-article requirements.
  • Commercial inputs: prototype and production quantities, panel constraints, delivery destination, requested ship or arrival date, Incoterm, and packaging needs.

Identify unresolved items in the package rather than leaving them blank. Suppliers can then return the same open questions and quote assumptions, giving procurement a usable basis for comparison.

What Should a Useful DFM Review Tell You Before Production?

A useful RF DFM review should return the proposed build, every requested deviation, and the questions that still block release. A generic “files are manufacturable” reply does not show whether the supplier reviewed the RF-sensitive parts of the design.

  • Proposed stackup: material set, dielectric targets, copper assumptions, pressed thickness, reference planes, and the geometry used for impedance calculation.
  • Material status: availability, procurement time, minimum buy, shelf-life or storage concern, and any requested substitute.
  • RF geometry changes: proposed trace, gap, ground clearance, mask, via, pad, launch, or coupon changes and their reason.
  • Process limits: combinations of etching, registration, drilling, backdrill, filling, plating, cavity, metal backing, or panelization that need adjustment.
  • Test approach: coupon design, correlation to production layers, sampling, method, fixtures, data format, acceptance limits, and unavailable measurements.
  • Release questions: a short list of unresolved material, stackup, geometry, testing, documentation, or delivery decisions assigned to the responsible party.

Any proposed change that may alter RF performance should return to the customer for approval before production release. The approved DFM response then becomes part of the baseline used to review first article and repeat orders.

How Should You Compare RFQ Responses from Different Suppliers?

Compare the complete technical and delivery scope, not the unit price in isolation. For high frequency PCB in Switzerland, two offers are not equivalent if they use different laminates, stackups, test plans, manufacturing sites, or responsibility boundaries.

RFQ Item What Buyers Should Compare
Material Exact laminate, bondply or prepreg, thickness, copper type, availability, and approved substitutes
Stackup Returned construction, finished dielectric and copper targets, RF layers, reference planes, and deviations
Impedance Targets, tolerances, calculation assumptions, coupon design, sampling, and reported data
RF testing Included measurements, test structures, fixtures, frequency range, de-embedding, limits, and report format
Manufacturing site Legal entity, actual plant, subcontracted operations, inspection location, and ship-from country
NRE Tooling, CAM or engineering, coupons, test setup, reports, and repeat-order charges
Lead time Material procurement, approval start point, fabrication, testing, shipment, customs, and partial-delivery terms
Change control Material, construction, process, site, and test changes that require written customer approval

Normalize the offers by listing every exclusion and assumption beside the quoted price. If one price omits the specified material, representative coupon, RF measurement, or approved build site, correct the scope before selecting a supplier.

If your project allows manufacture outside Switzerland, EBest Circuit can review the current design and return a proposed stackup, material options, DFM questions, and quotation. Ready to request a quote? Send your Gerber or ODB++ files, stackup, material callouts, impedance and RF requirements, quantities, test scope, and delivery destination to sales@bestpcbs.com.

FAQs About High Frequency PCB in Switzerland

Q1: Does a high frequency PCB for a Swiss project need to be manufactured in Switzerland?

A1: No, unless the contract, customer approval, data restriction, or qualification plan requires Swiss manufacture. If overseas or European production is allowed, name the approved plant and assign importing, customs, delivery, and return responsibilities before the order.

Q2: Is Rogers material always required for a high frequency PCB?

A2: No; Rogers is one group of RF laminate products, not a universal requirement. Select the material from the operating frequency, loss budget, impedance stability, thermal and mechanical needs, assembly process, supply status, and qualified electrical data.

Q3: Can PTFE and FR-4 be used in the same multilayer PCB?

A3: Yes, a qualified fabricator can build mixed PTFE/FR-4 constructions. The returned stackup must address bonding, thermal expansion, registration, resin flow, drilling, plating, finished thickness, and the RF geometry affected by the hybrid build.

Q4: Does TDR testing prove complete RF performance?

A4: No; TDR is primarily used to evaluate characteristic impedance and discontinuities. Loss, return loss, phase, launch behavior, resonance, and antenna performance may need separate test structures or system-level verification.

Q5: Can an RF PCB supplier substitute the specified laminate?

A5: Only when the RFQ permits substitution and the customer approves the proposed alternative. Compare Dk and Df under relevant methods and frequencies as well as thickness, copper, thermal, mechanical, processing, availability, and qualification effects.

Q6: Why can RF laminate availability affect lead time?

A6: Specialized cores, bondplies, thicknesses, or copper types may not be held in the required quantity. Procurement, minimum buys, lot allocation, incoming inspection, and shelf-life controls can add time before fabrication begins.

Q7: Should prototype and production boards use the same stackup?

A7: Use the production-intent stackup when prototype results will support qualification. If an early prototype uses a different material or construction, document the difference and repeat the affected electrical and reliability checks after transfer.

Q8: Can high frequency PCBs be manufactured in China and shipped to Switzerland?

A8: Yes, if the project permits Chinese manufacture and the supplier can meet the technical and documentation requirements. The buyer should define the approved factory, Incoterm, importer, customs data, VAT and clearance responsibility, packaging, delivery point, and nonconformance return route.

Q9: Does every high frequency PCB require S-parameter testing?

A9: No; the need depends on the controlled RF response and the product risk. Specify S-parameter testing when insertion loss, return loss, coupling, or another network response must be verified beyond impedance and ordinary electrical test.

Q10: What changes should trigger customer approval on repeat orders?

A10: Require approval for changes that can move the validated RF baseline. Typical triggers include laminate or bondply, dielectric or copper, impedance geometry, finish, drilling or backdrill, test method, coupon, subcontracted process, and manufacturing site.

Tags: , , ,
Posted in RF & Telecom PCB | No Comments »

What Is Brazing? Process, Types, Uses & Welding vs Soldering

September 17th, 2026

What is brazing? It joins metal parts without melting the base materials themselves. Instead, heat melts a separate filler alloy, which wets the mating surfaces and flows through the joint gap by capillary action. After cooling, the filler solidifies and forms a metallurgical bond between the parts.

This process is useful when welding would create too much distortion, when dissimilar metals need to be joined, or when a clean and leak-tight joint is required. Brazing is common in HVAC, refrigeration, automotive, aerospace, electrical equipment, heat exchangers, tooling, and many other metal assemblies.

What is brazing illustration showing torch brazing of copper tubing and filler metal flowing into the joint

Key Takeaways

  • Brazing is a metal-joining process that melts a filler metal above 450°C (840°F) while keeping the base metals solid.
  • The molten filler enters a close-fitting joint through wetting and capillary action, rather than by melting the parts being joined.
  • Successful brazing depends heavily on clean surfaces, correct joint clearance, suitable filler metal, controlled heating, and oxide management.
  • Brazing differs from welding because the base metal normally does not melt. It differs from soldering mainly because brazing filler metals melt above 450°C.
  • Common methods include torch, furnace, induction, resistance, dip, and vacuum brazing.
  • Brazing is widely used for HVAC tubing, heat exchangers, automotive assemblies, aerospace parts, electrical contacts, cutting tools, and leak-tight metal joints.
  • Copper-to-copper joints can sometimes use phosphorus-bearing filler without separate flux, while dissimilar joints require more careful filler and flux selection.

What Is Brazing?

Brazing is a metal-joining process in which a filler metal melts above 450°C (840°F) and flows between closely fitted parts while the base metals remain solid.

The process uses heat to bring the joint area above the filler alloy’s melting range, but below the melting temperature of the components being joined. The filler then wets the surfaces and fills the gap between them.

This makes brazing different from welding, where the base material is normally melted to create the joint. It also separates brazing from soldering, which uses filler metals with a liquidus temperature below 450°C.

A brazed joint can connect similar or dissimilar metals, depending on the filler alloy, joint design, surface condition, and service requirements.

How Does the Brazing Process Work?

The answer to what is brazing process is straightforward: heat a prepared joint until the filler metal melts and flows through the clearance between the parts.

  1. Clean the surfaces. Remove oil, grease, dirt, and oxides that could prevent wetting.
  2. Fit the parts together. Maintain an appropriate and reasonably uniform joint clearance.
  3. Apply flux if required. Flux limits oxide formation and helps the molten filler wet the surfaces.
  4. Heat the joint. Bring the assembly to the correct brazing temperature without melting the base metals.
  5. Introduce the filler metal. The filler melts when it contacts the heated joint area.
  6. Allow capillary action to distribute the filler. Molten alloy is drawn into the joint.
  7. Cool the assembly. The filler solidifies and forms the final bond.
  8. Clean the joint if necessary. Residual flux may need to be removed.

The filler should generally melt because of heat in the workpieces rather than being melted directly by the flame. This helps produce more uniform flow and reduces the risk of overheating the filler before the joint reaches brazing temperature.

Brazing process steps showing cleaning fit-up flux heating filler application and cooling

Why Are Joint Clearance, Wetting and Capillary Action Important?

A brazed joint depends on molten filler being able to wet both surfaces and flow through the joint gap. Joint clearance therefore has a direct effect on filler distribution.

If the gap is too large, capillary attraction becomes weaker and the filler may not fill the joint evenly. If the gap is too tight, filler penetration can also be restricted, especially when thermal expansion changes the clearance during heating.

Good wetting also requires clean metal surfaces. Oil, heavy oxidation, or unsuitable surface films can prevent the filler from spreading across the base metal.

Clean surface + suitable clearance + correct temperature → good wetting → capillary flow → complete joint

This is one reason brazing quality cannot be judged only by how much filler is visible around the outside of the connection. A large external fillet does not automatically mean the filler has properly penetrated the internal joint.

Brazing wetting and capillary action diagram showing correct clearance too wide and too tight joints

What Are Brazing Rods, Filler Metals and Flux?

Brazing filler metal is the alloy that melts and forms the joint between the base materials. A brazing rod is simply one physical form in which that filler can be supplied.

Common filler forms include:

  • Rod
  • Wire
  • Ring
  • Strip
  • Foil
  • Preform
  • Paste
  • Powder

Different filler alloys are selected according to the base metals, brazing temperature, corrosion requirements, service temperature, joint strength, and manufacturing process.

Flux serves a different purpose. It helps control oxides that would otherwise prevent proper wetting and filler flow. Depending on the formulation, flux can dissolve existing oxides and reduce further oxidation during heating.

Not every brazing operation requires external flux. Vacuum brazing and controlled-atmosphere processes can manage oxidation without conventional flux, while some copper-phosphorus fillers can be self-fluxing on copper-to-copper joints.

Brazing filler metal forms including rod wire ring paste powder and brazing flux

What Types of Brazing Are There?

Brazing methods are usually classified by how heat is applied to the joint.

Brazing Method Heat Source / Environment Typical Use
Torch brazing Gas flame HVAC, repair, low-volume production
Furnace brazing Controlled furnace Batch or volume assemblies
Induction brazing Electromagnetic induction Fast, localized heating
Resistance brazing Electrical resistance Small, repeatable joints
Dip brazing Molten bath Specialized assemblies
Vacuum brazing Vacuum furnace Clean, high-reliability components

Torch brazing is common for manual work because the heat can be directed at a specific joint. HVAC copper tubing is a typical example.

Furnace brazing is useful when many joints must be heated at once. It provides better repeatability and lends itself to higher-volume manufacturing.

Induction brazing heats conductive parts rapidly using an alternating electromagnetic field. It is useful where short cycle times and local heat control matter.

Vacuum brazing is used when oxidation, contamination, flux residue, or high joint cleanliness are critical, such as in aerospace, vacuum hardware, and precision assemblies.

Types of brazing including torch furnace induction resistance and vacuum brazing

Brazing vs Welding: What Is the Difference?

The most important difference is that brazing normally does not melt the base metals, while welding usually joins parts by locally melting and fusing the base material.

Factor Brazing Welding
Base metal melts No Usually yes
Filler metal Commonly required Depends on process
Joint mechanism Wetting and capillary flow Fusion
Heat input to base material Usually lower Usually higher
Distortion Often lower Often higher
Dissimilar metals Often easier Can be more difficult
Joint design Often relies on overlap Butt, fillet, lap and other joints

Brazing is useful when dimensional stability matters because the base parts remain below their melting temperature. This can reduce distortion and preserve more of the original component geometry.

Welding is often preferred when a fused structural joint is required or when the joint must become part of the base-metal section itself.

It is not accurate to say that welding is always stronger than brazing. Joint strength depends on material combination, filler alloy, joint overlap, clearance, section thickness, loading direction, and operating temperature.

Brazing vs Soldering: What Is the Difference?

Brazing and soldering are closely related because both join materials using a molten filler while keeping the base metals solid.

The standard temperature distinction is the filler metal’s liquidus temperature:

  • Brazing: above 450°C / 840°F
  • Soldering: below 450°C / 840°F
Factor Brazing Soldering
Base metal melts No No
Filler temperature Above 450°C Below 450°C
Capillary action Common Common
Flux may be used Yes Yes
Typical mechanical capability Higher Lower
Typical service temperature Higher Lower
Common examples HVAC, heat exchangers, tooling Electronics, wires, connectors

Soldering is especially common in electronics because the lower temperature limits thermal stress on components and PCB materials used in PCBA.

Brazing is more appropriate when higher mechanical strength, higher service temperature, leak-tight tubing, or more demanding metal assemblies are required.

Brazing welding and soldering comparison showing base metal condition filler behavior and temperature ranges

What Metals Can Be Brazed?

Many common engineering metals can be brazed when a compatible filler alloy and process are selected.

Examples include:

  • Copper
  • Brass
  • Carbon steel
  • Stainless steel
  • Nickel and nickel alloys
  • Aluminum
  • Silver-containing alloys
  • Carbide-to-steel tool assemblies
  • Selected dissimilar-metal combinations

Copper is particularly brazing-friendly because many filler alloys wet it effectively, and copper tubing can be joined reliably with proper preparation.

Aluminum also can be brazed, but its stable oxide layer requires suitable flux, atmosphere, filler alloy, and temperature control.

The key point is that brazability depends on the specific base-metal combination, not just on whether each material can be brazed individually.

What Is Brazing Used For?

Brazing is used when metal components need a strong, clean, dimensionally stable, or leak-tight joint without melting the base materials.

Common applications include:

  • HVAC refrigeration lines
  • Copper tubing
  • Heat exchangers
  • Radiators
  • Automotive components
  • Aerospace assemblies
  • Cutting tools
  • Carbide tips
  • Electrical contacts
  • Hermetic housings
  • Plumbing assemblies
  • Industrial tubing
  • Refrigeration equipment
  • Vacuum hardware

Heat exchangers are a good example because many thin metal sections and internal flow passages may need to be joined while maintaining geometry and leak tightness.

Cutting tools also use brazing to attach carbide inserts or tips to steel bodies. The process allows materials with very different properties to be joined without melting either base component.

Industrial brazing applications including HVAC heat exchanger cutting tool and electrical contact

What Is Brazing in HVAC and Copper Pipe Work?

In HVAC and refrigeration systems, brazing is widely used to join copper tubing that carries refrigerant under pressure.

The process is preferred because properly brazed joints can provide:

  • Strong mechanical connection
  • Leak resistance
  • High-pressure capability
  • Good temperature resistance
  • Compact joint geometry

For copper-to-copper tubing, phosphorus-bearing copper filler alloys are commonly used. Some of these fillers can provide self-fluxing action on clean copper, so separate flux may not always be required.

For copper-to-brass, the filler and flux requirements depend on the alloy system and joint design.

For copper-to-steel, more care is required. Phosphorus-bearing filler metals should not simply be transferred from copper-to-copper practice because brittle compounds can form with ferrous materials. A suitable phosphorus-free filler and compatible flux are normally selected instead.

HVAC brazing quality also depends on tube preparation, fit-up, heating technique, filler distribution, and oxidation control inside and outside the tubing.

HVAC brazing copper refrigerant line with copper-to-copper and copper-to-steel joint examples

What Are the Advantages and Limitations of Brazing?

Brazing offers several manufacturing advantages, but it also places tight requirements on surface condition and joint design.

Advantages Limitations
Lower distortion than many welding processes Joint clearance is important
Joins dissimilar metals Surface cleanliness is critical
Good for thin sections Filler compatibility must be verified
Can create leak-tight joints Service temperature is limited by filler alloy
Suitable for complex assemblies Flux residues may require cleaning
Can be automated Poor joint design can reduce strength
Base metals remain solid Heating must still be controlled

Because the base metals do not melt, brazing can preserve thin sections and precision geometries better than some fusion processes.

The trade-off is that brazing is less forgiving of contaminated surfaces, unsuitable clearances, or incorrect alloy selection. A visually neat joint can still perform poorly if filler has not penetrated the intended joint area.

FAQ About Brazing

1. What temperature is considered brazing?
Brazing uses filler metals with a liquidus temperature above 450°C (840°F) while remaining below the melting temperature of the base metals.

2. Does brazing melt the base metal?
No. The base metals remain solid during brazing. Only the filler metal is melted and distributed through the joint.

3. Is brazing stronger than soldering?
Brazed joints generally support higher mechanical loads and service temperatures than soldered joints, but actual strength depends on the filler alloy, base materials, clearance, joint geometry, and loading.

4. Can copper be brazed?
Yes. Copper is commonly brazed in HVAC, refrigeration, plumbing, heat exchangers, and electrical assemblies.

5. Does copper brazing need flux?
Not always. Certain phosphorus-bearing filler metals are self-fluxing on copper-to-copper joints, although other material combinations may require flux.

6. Is brazing the same as welding?
No. Welding normally melts and fuses the base material, while brazing joins solid base metals using a separate molten filler.

Brazing is most successful when the filler alloy, flux or atmosphere, joint clearance, and heating method are selected as one system rather than as separate choices. For engineering projects, the base-metal combination and service conditions should always be defined before choosing the brazing process.

Tags: , , , ,
Posted in best pcb, Electrical Components, PCB Technology, SMT Technology | No Comments »

Embedded Resistors in PCB: Benefits and Manufacturing

September 17th, 2026

Embedded resistors in PCB manufacturing are resistive elements formed inside the board rather than installed as separate surface-mounted components. They free up component space, reduce resistor placements, and can shorten electrical connections. For compact products, this moves selected circuit functions into the bare board while leaving more surface area available for other components.

The manufacturing challenge is to deliver the required resistance consistently, not simply to produce a conductive pattern. Material variation, etching accuracy, temperature, and electrical loading all affect the result. Understanding how those factors translate into measurable resistance changes helps engineers and purchasing teams evaluate the finished product.

embedded resistors in PCB

What Are Embedded Resistors in a PCB?

Embedded resistors are passive elements integrated into a PCB’s internal circuit layers. They perform functions such as termination, biasing, and voltage division, with the resistive structure forming part of the laminated board.

In a common thin-film construction, a resistive alloy is deposited on copper foil and bonded to a dielectric. Selective etching exposes the resistor body while retaining copper terminals at its ends. Current flows through the film between those terminals, and subsequent lamination encloses the structure inside the PCB.

This process differs from placing a packaged chip resistor inside a cavity. The thin-film element receives its final resistance through material properties and patterned dimensions, making its value a characteristic of the manufactured board. This article focuses on that foil-based construction.

How Do Embedded Resistors Compare with Surface-Mount Resistors?

Embedded resistors reduce surface occupancy and individual component connections. Surface-mount resistors provide easier access for value changes, replacement, and calibration. The practical choice depends on which functions benefit from integration and which need to remain adjustable.

ComparisonEmbedded Thin-Film ResistorsSurface-Mount Resistors
LocationInternal circuit layersBoard surface
ConnectionResistive film connected directly to copper terminalsComponent terminations connected through solder joints
Production stageFormed during PCB fabricationPlaced and soldered during assembly
Resistance controlMaterial and processing establish the finished valuePurchased component specification, with assembly effects considered
Value changesUsually require revised fabrication dataOften possible through component substitution
ReplacementLimited access after laminationAccessible for component-level replacement

The electrical benefit comes from the resulting interconnect, rather than burial alone. Shortening a connection can reduce parasitic inductance and capacitance. In RF circuits, the relevant result is the performance of the complete connection across the operating band.

Removing a chip resistor also removes its component-to-board solder joints, but adds resistor formation and verification to PCB fabrication. A mixed construction can embed stable termination functions while keeping tuning and calibration resistors on the surface.

embedded resistors in PCB

What Materials Are Used for Embedded PCB Resistors?

Foil-based embedded resistors commonly use nickel-phosphorus or nickel-chromium resistive alloys combined with copper and a compatible dielectric. The alloy provides the resistance; the copper supplies the terminals and conductors, while the dielectric supports and insulates the structure.

Resistive MaterialTypical ConstructionManufacturing Consideration
Nickel-phosphorus, or NiPElectrodeposited resistive alloy on copperSelective processing must preserve the resistor film and copper terminals
Nickel-chromium, or NiCrVacuum-deposited resistive alloy on copperEtching chemistry and sequence must match the alloy and foil construction

Material grades are described by sheet resistance, expressed in ohms per square, or Ω/□. This is different from the finished resistor value. For example, a uniform 50 Ω/□ film patterned into a simple rectangle with an effective length-to-width ratio of 2:1 gives a nominal 100 Ω before manufacturing variation.

The dielectric is a separate part of the specification. Suitable constructions can use FR4, high-frequency laminates, or polyimide, provided the complete material combination is compatible with processing and service conditions. A flexible circuit also requires verification under its intended bending conditions.

Copper thickness, surface treatment, adhesion, and lamination behavior influence manufacturing consistency. A replacement material therefore needs more than a matching sheet-resistance value: its complete construction must remain compatible with the approved production process.

How Are Embedded Resistors Manufactured in a PCB?

Embedded thin-film resistors are produced through imaging, selective etching, inspection, and lamination. In a typical nickel-phosphorus process, two imaging operations define the combined circuit and then the exposed resistor bodies.

  1. Prepare the resistor laminate. Check material identification, surface condition, and handling. The copper, resistive film, and dielectric must be suitable for the intended chemical and thermal processing.
  2. Form the combined circuit pattern. Photoresist protects the required conductor and resistor areas. Unwanted copper is removed, followed by unwanted resistive material outside the circuit pattern.
  3. Expose the resistor bodies. A second image protects the copper conductors and terminals. Selective copper removal exposes the film that will carry current through each resistor.
  4. Inspect and measure the inner layer. Optical inspection checks geometry and visible defects. Electrical measurements establish resistance while the patterned elements remain accessible.
  5. Laminate and complete the board. The resistor layer is incorporated into the multilayer structure. Subsequent fabrication and final electrical testing complete the production sequence.

The etching route depends on the alloy. Some nickel-chromium processes remove unwanted copper and resistive material together during the initial circuit etch, reducing the need for a separate resistor-film removal stage.

Registration and etching at the copper-to-resistor boundary determine the effective element dimensions. Measurements before and after later processing help distinguish variation introduced during resistor formation from changes associated with lamination or subsequent operations.

Production records should connect material lot, artwork revision, and resistance measurements. This makes a resistance shift traceable to the relevant stage rather than leaving the investigation dependent on the final test result alone.

embedded resistors in PCB

What Resistance Values and Tolerances Can Embedded Resistors Achieve?

Foil-based constructions can produce values from a few ohms through tens of kilohms, depending on material and geometry. Finished tolerance must be established for the actual process. A 100 Ω ±10% requirement, for example, means acceptance between 90 and 110 Ω at the specified measurement stage and conditions.

Three requirements need to remain separate:

RequirementWhat It Specifies
Material toleranceVariation in the supplied film’s sheet resistance
Finished resistance toleranceDeviation from the target value after a defined manufacturing stage
Stability limitPermitted change after specified thermal, environmental, or electrical loading

Consider a 100 Ω target with an assumed ±5% sheet-resistance variation and ±3% variation in the effective length-to-width ratio. Combining the worst-case limits gives 100 × 0.95 × 0.97 = 92.15 Ω at the lower end and 100 × 1.05 × 1.03 = 108.15 Ω at the upper end.

The calculated upper value is only 1.85 Ω below a 110 Ω acceptance limit, before any additional processing shift. A ±5% material specification does not automatically produce a ±5% finished resistor. This example shows how material and dimensional variation consume the available tolerance allowance.

Actual production results also depend on film uniformity, imaging accuracy, etching consistency, and later processing. Smaller features are more sensitive to a given absolute dimensional error, so the same material can produce different tolerance outcomes in different geometries.

Tighter requirements may involve trimming while the resistor remains accessible. The adjusted element must still meet the final acceptance limits after the remaining manufacturing steps; an accurate pre-lamination reading alone does not establish finished-board accuracy.

How Do Power and Temperature Affect Embedded Resistor Performance?

Power generates heat, while temperature changes the operating resistance and can affect long-term stability. The useful operating limit is therefore the load at which the resistor remains within its electrical requirements, not simply the point before it fails open.

Temperature-related resistance change

The temperature coefficient of resistance, or TCR, estimates how much resistance changes with temperature. Assuming a constant coefficient over the interval:

Resistance change (%) = TCR (ppm/°C) × temperature change (°C) ÷ 10,000.

Consider two resistors that each measure 100 Ω at 25°C, with assumed positive temperature coefficients of 50 and 100 ppm/°C. If both resistor bodies reach 85°C, the estimated changes are:

Assumed Temperature CoefficientTemperature RiseEstimated Resistance ChangeEstimated Operating Resistance
+50 ppm/°C60°C+0.30%100.30 Ω
+100 ppm/°C60°C+0.60%100.60 Ω

If the circuit allows temperature effects to contribute no more than 0.5%, the second example exceeds that allowance. The first remains within this particular budget, but initial manufacturing error and permanent drift still need separate consideration.

The relevant temperature is the resistor body’s temperature, including self-heating. An enclosure at 85°C does not establish an 85°C resistor temperature. Nearby copper, dielectric thickness, and heat paths determine how far the element rises above its surroundings.

Power loading and stability

At a nominal 100 Ω, increasing current from 10 mA to 20 mA raises heat generation from 10 mW to 40 mW. Doubling current quadruples power when resistance is held constant. The calculation establishes the electrical load; the actual temperature rise depends on the PCB’s thermal behavior.

Power qualification should assess both behavior under load and resistance after cooling to the reference temperature. A resistor can remain conductive while drifting outside its stability limit. Continuous-use capability therefore requires more than a brief overload-survival result.

Pulse loading

An illustrative 1 W rectangular pulse lasting 1 ms every 10 ms produces 0.1 W average power and 1 mJ per pulse. Average power alone does not establish safe operation: peak temperature also depends on pulse duration and the element’s thermal response. Pulse assessment includes amplitude, duration, and repetition rate.

How Are Embedded Resistors Tested During PCB Manufacturing?

Embedded resistors are verified by resistance measurements, supported by pattern inspection and normal PCB continuity and isolation checks. The test program must identify whether a reading represents one resistor or an interconnected network.

Before lamination

Optical inspection checks for copper remnants, damaged film, dimensional errors, and irregular terminal geometry. Measurements through the copper terminals verify the electrical result. Process-control coupons track manufacturing variation, while product measurements provide the coverage specified for the actual circuit.

Finished-board measurement

A resistor-capable flying-probe or fixture-based system accesses the completed board’s test nodes. Two ideal 100 Ω resistors in parallel measure 50 Ω, but 90 Ω and 112.5 Ω also produce 50 Ω. A correct network reading therefore cannot, by itself, prove that both elements meet a 100 Ω ±10% requirement.

Measurement connections matter as well. An assumed 0.2 Ω of combined lead and contact resistance adds 2% to a 10 Ω two-wire reading. Four-wire sensing separates current delivery from voltage measurement, reducing that contribution. Controlled test current limits self-heating, and a defined temperature keeps measurements comparable.

Stability and acceptance

Consider an illustrative 100 Ω resistor measuring 100.4 Ω before a specified stress exposure and 101.0 Ω afterward, both at the same reference temperature. Its final nominal error and its change from the measured baseline give different acceptance results:

CheckCalculated ResultExample RequirementDecision
Final error from 100 Ω nominal+1.0%Within ±10%Pass
Change from the 100.4 Ω baselineApproximately +0.60%No more than 0.5%Fail

A broad nominal tolerance can therefore hide an unacceptable stability change unless both quantities are reported. Test records should identify the element or network, measured values, reference conditions, acceptance limits, and board or lot, with qualification sampling distinguished from routine production coverage.

embedded resistors in PCB

Where Are Embedded Resistors Used?

Embedded resistors suit stable circuit functions that benefit from close integration with the PCB. The most relevant applications combine a clear electrical purpose with a practical need for compact interconnections or reduced surface occupancy.

  • High-speed communication and computing boards: Series or parallel termination can be integrated near the relevant circuit layer, freeing surface space around dense component areas.
  • RF and microwave assemblies: Power dividers, combiners, attenuators, and equalizers can incorporate thin-film elements. In a Wilkinson divider, the isolation resistor becomes part of the printed RF network.
  • High-density modules and package substrates: Pull-up, pull-down, bias, and voltage-divider functions can be embedded where their accuracy and stability requirements match the manufacturing process.
  • Localized heating: Patterned resistive foil can form a heater inside the board. Here, qualification focuses on temperature distribution, operating load, and thermal cycling.

The application determines the evidence needed. DC resistance supports resistor acceptance, while an RF network also needs performance verification across its operating band. A heater is evaluated against its thermal requirements rather than a signal-termination specification.

When Are Embedded Resistors Cost-Effective?

Embedded resistors are cost-effective when savings in components, assembly, or packaging justify the added PCB material, processing, and testing. The useful comparison is cost per accepted assembled board, including yield and rework, rather than bare-board price alone.

Replacing 200 two-terminal chip resistors removes 200 component placements and 400 component-to-board solder joints. The remaining assembly may still need the same reflow pass, so reduced placement work should not be counted as eliminating an entire soldering operation.

Cost GroupItems to Include
Added fabrication costResistive material, imaging and etching, resistance testing, qualification, and yield effects
Removed assembly costPurchased resistors, their placement, and related solder-joint inspection
Product-level valueUsable board area, enclosure fit, and required electrical performance

A hypothetical break-even calculation makes the comparison clearer. Assume one-time qualification costs of $1,200 and a recurring saving of $1.20 per accepted assembly after all affected production costs. Break-even occurs at 1,000 boards; producing 2,000 boards gives a net saving of $1,200.

These inputs illustrate the calculation rather than market pricing. Higher resistor density can distribute material and imaging costs across more functions, while frequently changed resistor values may favor surface-mounted parts during development. Both cases should be evaluated against the expected production volume.

What Should You Confirm Before Ordering an Embedded Resistor PCB?

An embedded-resistor PCB order needs identifiable resistor elements, a complete material construction, and measurable acceptance criteria. Fabrication and assembly documents must distinguish formed resistors from discrete parts that still require purchasing and placement.

Order InformationDetails to Include
Resistor scheduleReference identifiers, target values, finished tolerances, and electrical connections
Material constructionResistive grade, sheet resistance, copper thickness, dielectric, and layer location
Fabrication filesGerber or ODB++ data, resistor artwork, netlist, stackup, and controlled drawing revision
Operating conditionsContinuous load, pulse profile, temperature range, and stability requirements
TestingAccessible nodes, individual or network measurements, coverage, reference conditions, and acceptance limits
Production scopePrototype and repeat quantities, assembly scope, material availability, and delivery requirements

The resistor schedule should map directly to the artwork and test program. A requirement such as 100 Ω ±10% also needs an acceptance stage and measurement conditions. Any post-exposure drift limit belongs in a separate field rather than being folded into the nominal tolerance.

Material substitutions require review of processing and thermal behavior as well as sheet resistance. Once the sample build is approved, the released construction, fabrication data, and test limits become the reference for repeat production.

For mixed assemblies, the schematic can show both embedded and discrete resistors. The assembly BOM and placement data should identify which positions require physical components, preventing embedded functions from being purchased or placed a second time.

FAQs About Embedded Resistors in PCB

1. Do embedded resistors require an extra PCB layer?

Not necessarily. Thin-film resistors can share an existing circuit layer with copper conductors. Whether another layer is needed depends on the available area, electrical connections, and complete board construction.

2. Can embedded resistors be used in flexible PCBs?

Yes. Suitable polyimide-based resistive laminates support flexible and rigid-flex constructions. The finished circuit still needs verification for its intended bend radius and number of flex cycles; material compatibility alone does not establish dynamic-flex life.

3. Can one resistive layer contain different resistor values?

Yes. Different patterned dimensions produce different nominal values from the same sheet-resistance material. Each resistor retains its own target value, finished tolerance, and acceptance requirement in the production data.

4. Can embedded resistors be replaced after lamination?

A buried thin-film resistor is generally not replaceable like a surface-mounted component. Any repair or alternative connection requires board-level assessment and an approved method that preserves the intended circuit function.

5. Can embedded resistors and capacitors be used in the same PCB?

Yes. Compatible embedded-passive constructions can incorporate both functions. Their resistance, capacitance, dielectric, and manufacturing requirements need to be evaluated together within the proposed board structure.

EBest Circuit provides PCB fabrication, component sourcing, and PCB assembly services. For embedded resistors in PCB manufacturing, send your fabrication files, resistor schedule, material requirements, and quantities to sales@bestpcbs.com for an engineering review.

Include the finished resistance limits, operating load, and required test coverage. These requirements give our team a clear basis for evaluating manufacturability, verification, and quotation scope before production.

Tags: , ,
Posted in best pcb, bestpcb, Electronic Components | No Comments »

How Do You Control PCB Surface Flatness?

September 17th, 2026

PCB surface flatness describes how closely a bare board or a defined local area conforms to its intended plane. For fabrication acceptance, bow and twist are the usual whole-board measures; for assembly, local coplanarity near a BGA, connector, thermal interface or test fixture may be just as important. At EBest Circuit (Best Technology), we control flatness through stack-up review, copper balance, lamination, panel design, routing and dimensional inspection, then align the acceptance method with your drawing and assembly process.

Conceptual PCB surface flatness inspection with a height gauge and optical metrology system

What Does PCB Surface Flatness Mean?

PCB flatness is not a single universal reading. A finished board can meet a bow-and-twist limit and still have a local high point that interferes with a heatsink, connector or fine-pitch package. Conversely, a small local feature may be acceptable even when a poorly supported panel appears distorted during handling. The specification must identify the object, area, condition and measurement method.

A flat surface PCB requirement should therefore answer four questions: Is the sample a production panel, a routed bare board or an assembled board? Is the concern global bow and twist or local surface profile? Is the measurement made at room temperature or through a thermal cycle? Which datum, fixture and acceptance limit apply?

Do not confuse PCB surface flatness with PCB surface roughness. Roughness describes small-scale texture, while flatness concerns form over a much larger area. PCB surface finish also affects pad planarity and solderability, but an ENIG or OSP coating cannot correct a warped laminate.

PCB Bow, Twist and Local Coplanarity: What Is the Difference?

Bow is a roughly cylindrical or spherical curvature in which the corners of a rectangular board remain in one plane. Twist is diagonal deformation: three corners can touch a reference plane while the fourth is raised. Local coplanarity describes height variation within a defined region, such as a BGA land field or the mounting area for a power module.

Conceptual comparison of PCB bow and PCB twist against a flat reference plane
Condition What changes Useful measurement basis
Bow The board curves along its length or width while the corners remain approximately coplanar Maximum gap divided by the relevant board dimension
Twist One corner rises relative to the plane formed by the other three corners Corner displacement and diagonal length using the specified method
Local coplanarity A defined pad, component or mounting region departs from its local datum plane Profile map, CMM or optical measurement over the stated area
Dynamic warpage Board shape changes as temperature changes Thermal-profile measurement with the agreed support condition

The phrase PCB warpage is often used broadly for bow, twist and temperature-dependent shape change. A PCB bow and twist specification is appropriate for room-temperature bare-board acceptance, but it should not be treated as proof of local BGA coplanarity or behavior during reflow.

Why Does Flatness Matter During PCB Assembly?

Assembly equipment assumes a predictable relationship between the board, stencil, placement head and support system. Excessive deformation can reduce contact between the stencil and pads, change solder-paste release, shift the focal plane for inspection, or leave a large package with uneven stand-off. Press-fit connectors, edge-card contacts and enclosure features can also become difficult to align.

Conceptual illustration of PCB flatness effects on stencil contact, BGA coplanarity and fixture support

For fine-pitch assemblies, our HDI PCB manufacturing and PCB assembly services can be reviewed together. The board construction, solder-paste process, package coplanarity and underside support all affect the result. A flat bare board does not eliminate every assembly variable, and a fixture that forces a board flat can hide its free-state deformation.

Mechanical interfaces create another constraint. If a PCB must contact a thermal pad or metal baseplate, the drawing should define the mounting region and allowable gap rather than relying on a general statement such as “board must be flat.”

How Is PCB Flatness Measured?

A basic PCB flatness measurement places the bare board on a precision surface plate and uses feeler gauges, a height indicator or equivalent metrology to measure the gap. IPC-TM-650 Method 2.4.22 describes production and referee procedures for bow and twist percentage on rigid boards, rigid portions of rigid-flex boards and panels. Its scope does not establish the special support conditions needed for populated assemblies.

Measurement task Typical equipment Report should record
Go/no-go bow check Surface plate and calculated feeler or pin gauge Board length/width, permitted percentage and tested direction
Actual bow percentage Surface plate, gauge set and dimensional measurement Maximum gap, corresponding span and calculated result
Twist measurement Surface plate, corner support and height gauge Diagonal, raised-corner displacement and calculation method
Local surface profile CMM, laser scanner or optical metrology Datum, area of interest, point spacing and maximum deviation
Thermal warpage Temperature-controlled optical measurement system Temperature profile, support, side viewed and shape versus time

For bow, the percentage is the maximum gap divided by the measured length or width, multiplied by 100. Under the production twist method in IPC-TM-650 2.4.22, twist percentage is the measured raised-corner gap divided by twice the diagonal, multiplied by 100. A PCB bow and twist formula must therefore match the selected procedure. A PCB bow and twist calculator is only as reliable as its inputs; using the wrong span or fixture creates a precise-looking but invalid result.

Record the board dimensions, diagonal, measured gap, test side and restraint used for every PCB bow and twist measurement. This is more useful than reporting only a pass/fail label because it makes the result reproducible.

A documented PCB surface flatness check should also identify whether protective films, tooling tabs or breakaway rails remain on the sample. If measurements from the fabricator and assembler disagree, first compare sample state, reference plane, restraint and temperature before comparing numbers.

Which Flatness Limits Should You Put on the Fabrication Drawing?

A PCB flatness specification should state the controlling document and revision, product class where applicable, maximum bow and twist, test condition, sample state and any local coplanarity zone. A PCB flatness tolerance is meaningful only when those conditions are defined. “Meet IPC” alone is incomplete because several IPC documents address different products, methods and acceptance contexts.

For our FR4 boards, we list a bow-and-twist capability of ≤0.75%, subject to the stack-up, board size, thickness, material system, copper distribution and engineering review. This is a manufacturing capability statement, not an automatic limit for every design. A thin, long board, a mixed-material stack-up or a local interface may need a different requirement and a dedicated measurement plan.

Drawing item Example of a clear instruction Why it matters
Sample state Routed bare board after final finish, rails removed Prevents panel rails from masking individual-board shape
Global requirement Maximum bow and twist per the named method and agreed percentage Defines the overall acceptance calculation
Local requirement Maximum plane deviation within a marked component or mounting area Protects the interface that drives assembly performance
Thermal condition Room temperature or specified temperature profile Separates incoming inspection from reflow behavior
Reporting Lot sample size, datum, instrument and measured result Makes supplier and customer data comparable

IPC-6012 bow and twist requirements should be interpreted with the purchase documentation and applicable revision. If your product has a tighter enclosure, optics or thermal-interface requirement, put that requirement on the drawing instead of expecting the general board class to imply it.

What Causes PCB Warpage?

PCB warpage develops when stresses are not balanced through the board thickness or across the panel. Laminate resin, glass reinforcement, copper and surface coatings expand and contract differently. Lamination, oxide treatment, solder-mask curing, surface finishing and assembly reflow expose the construction to repeated heat and moisture changes.

  • Asymmetric stack-up: different dielectric thicknesses or copper weights above and below the centerline create unequal shrinkage.
  • Uneven copper distribution: a solid plane on one side and sparse routing on the opposite side can leave residual stress after cooling.
  • Material mismatch: hybrid high-frequency, metal-core or stiffener constructions can respond differently to temperature.
  • Thin or elongated geometry: low bending stiffness makes the same residual stress produce more visible deflection.
  • Panel and routing design: weak rails, uneven coupon placement, large cutouts and an unbalanced routing sequence can release stress unevenly.
  • Moisture and thermal history: storage, baking, solder-mask cure and reflow can change the free-state shape.

A PCB warpage calculation based only on laminate CTE cannot predict the final board. Copper pattern, resin flow, press cycle, panel position, routing and later assembly loads also matter. Use calculation to compare design options, then validate critical builds with representative coupons or samples.

How Do Stack-Up Symmetry and Copper Balance Reduce Warpage?

A mechanically balanced stack places similar copper weights and dielectric structures at comparable distances from the centerline. It does not require identical routing on every layer, but it avoids unnecessary imbalance in copper area and layer construction. This gives the laminate a more uniform response during pressing and cooling.

Conceptual PCB stack-up comparison showing balanced and unbalanced copper distribution

Our FR4 PCB manufacturing supports single-sided, double-sided and multilayer constructions up to 32 layers, subject to engineering review. More layers do not automatically improve or reduce flatness. What matters is the actual build: core and prepreg selection, copper weight, layer pairing, resin fill, overall thickness and panel utilization.

Copper thieving can improve local plating distribution and may help balance unused panel areas, but it is not a universal repair for an asymmetric product stack-up. We review copper distribution together with impedance, spacing and manufacturability so a flatness correction does not create an electrical or fabrication problem elsewhere.

How Do Board Thickness, Panelization and Routing Affect Flatness?

Thickness raises bending stiffness, so very thin boards are more sensitive to handling and residual stress. Our extra-thin PCB options include constructions from 0.15 mm, subject to material, size and engineering review. A thin-board requirement should therefore include panel support, assembly fixture and handling expectations rather than only the nominal thickness.

Panelization affects flatness before and after separation. Rails, crossbars, breakaway tabs, V-scores, routed slots and coupon placement change panel stiffness and the way stress is released. A large panel can pass while restrained by its frame, yet individual boards may change shape after routing. For flatness-critical parts, inspect both the production panel and the final routed board when those states serve different purposes.

Board outline matters too. Long narrow shapes, large internal windows and one-sided edge copper can create compliant regions. The best corrective action may be a stack-up change, panel rotation, added temporary support or revised routing sequence; simply increasing the final thickness can conflict with connectors, impedance or enclosure space.

Can PCB Surface Finish Improve Flatness?

A PCB surface finish can improve pad planarity relative to another finish, but it does not make the entire laminate flat. ENIG and immersion finishes deposit a comparatively uniform coating on exposed copper, while HASL can leave more variation across individual pads. This distinction matters for fine-pitch solder printing and probing.

However, the phrase PCB surface finish flat surface should not be interpreted as an overall warpage control method. Finish thickness is small compared with the board stack, and the chemical or thermal process cannot reverse a mechanically unbalanced construction. Select the finish for solderability, contact function, wire bonding, shelf life and pad-planarity needs; control global shape through the board design and fabrication process.

How Do We Control Flatness During PCB Manufacturing?

We begin with the released stack-up and panel, because most flatness risks are easier to prevent than to sort after fabrication. Our DFM review looks for asymmetry, concentrated copper, thin long geometry, mixed materials, large openings, unusual routing and local interfaces that deserve their own tolerance.

  1. Confirm the applicable flatness definition, acceptance method and sample state.
  2. Review layer symmetry, dielectric distribution and copper balance.
  3. Plan panel rails, coupons, scoring or routing so the panel remains stable during processing.
  4. Control lamination, curing and cooling according to the approved material and stack-up.
  5. Inspect at the state that matters: panel, routed bare board and, when separately agreed, the assembly condition.
  6. Use dimensional data to distinguish a design-driven pattern from a process or handling issue.

Our listed quality capabilities include 3D dimensional measurement, AOI, microsection analysis and electrical testing. These tools answer different questions. Flatness metrology measures shape; electrical testing checks continuity and insulation; microsectioning examines internal structure. One result should not be presented as proof of another.

What Should You Check After Reflow or Depaneling?

A room-temperature bare-board check is not the same as an assembled-board assessment. During reflow, the board becomes less stiff and materials expand at different rates. Components, solder, edge supports and fixtures add loads that are outside the basic bare-board bow-and-twist method. After cooling, some deformation recovers and some may remain.

When failure appears only after assembly, compare incoming flatness, panel location, paste printing, reflow profile, support-pin layout, component distribution and depaneling method. Measure the board both free and in its intended fixture if the product relies on mounting force. Record which condition produces the functional problem.

For a connector or thermal interface, inspect the actual local zone rather than averaging the entire board. For BGA-related opens, separate PCB shape from package warpage, paste volume and pad design before changing the fabrication limit.

What Information Should You Send for a Flatness-Critical PCB Order?

Send the fabrication files and a controlled drawing that identifies the critical flatness requirement. A complete manufacturing package includes:

  • Finished board dimensions, outline and panel preference
  • Layer count, proposed stack-up, copper weights and finished thickness
  • Material system and any mixed-material or stiffener construction
  • Maximum bow and twist, controlling method and sample state
  • Local coplanarity area, datum, maximum deviation and inspection method
  • Assembly process, peak thermal exposure and fixture constraints
  • Critical components, connectors, heat spreaders and enclosure interfaces
  • Required report format, sample size and lot traceability

At EBest Circuit (Best Technology), we will review the requirement against the actual board construction instead of treating one percentage as universal. Send your files and target PCB surface flatness criteria to sales@bestpcbs.com. We can align the drawing, manufacturing plan and assembly risk before production planning.

Tags: , , ,
Posted in pcb manufacturing, PCB Technology, Quality | No Comments »

How Does a Telematics Control Unit Work?

September 17th, 2026

A telematics control unit connects a vehicle’s internal networks with cellular, satellite-navigation, and cloud services. It receives vehicle data, adds location or communication information, processes selected messages, and exchanges data with external platforms. That combination enables functions such as remote diagnostics, emergency calling, fleet monitoring, stolen-vehicle tracking, and over-the-air service support.

For a product team, the TCU is also a demanding electronic assembly. Wireless modules, processors, memory, vehicle-network interfaces, power protection, RF connections, and large automotive connectors must work together inside a limited enclosure. EBest Circuit can support PCB fabrication, component sourcing, PCBA assembly, manufacturing review, inspection, traceability, and customer-defined testing. To discuss a TCU board build, contact sales@bestpcbs.com with the released manufacturing data and required test scope.

telematics control unit

What Is a Telematics Control Unit?

A telematics control unit, usually shortened to TCU, is the electronic module that provides a vehicle with a controlled connection to external communication networks. It acts as a bridge between information available inside the vehicle and services outside it. It is also called a T-Box in some automotive markets.

The complete unit is more than a circuit board. Depending on the product, it may include:

  • an assembled PCB;
  • a cellular modem and SIM or eSIM function;
  • a GNSS receiver;
  • a processor or microcontroller;
  • memory and secure storage;
  • CAN, CAN FD, LIN, or automotive Ethernet interfaces;
  • Wi-Fi, Bluetooth, or V2X hardware;
  • RF connectors or internal antennas;
  • protected power supplies and a backup-energy function;
  • firmware, security functions, an enclosure, and vehicle connectors.

The exact boundary varies by vehicle architecture. One TCU may focus on emergency calling and remote diagnostics, while another may also support Wi-Fi access, OTA communication, fleet data, infotainment services, or V2X. The released system specification—not the label “TCU” alone—determines what the hardware must contain.

This distinction also affects sourcing. A PCB supplier may fabricate the bare board, while a PCBA supplier may source components, assemble the board, program devices, and perform agreed tests. The complete telematics product still requires firmware, antennas, enclosure integration, network provisioning, security validation, and vehicle-level approval.

What Is a TCU in a Car, and What Does It Do?

A TCU collects selected vehicle information and transfers it to an external service, while also receiving authorized data or commands from outside the vehicle. It does not normally replace every other electronic control unit. Instead, it communicates with those controllers through the vehicle network.

A typical data path works like this:

  1. Vehicle ECUs publish status, sensor, diagnostic, or event data on an internal network.
  2. The TCU receives the permitted messages through CAN, CAN FD, LIN, or Ethernet interfaces.
  3. Its processor filters, packages, encrypts, stores, or prioritizes the information.
  4. A GNSS receiver can add position and time data.
  5. The cellular modem sends the required information to a cloud or service platform.
  6. Authorized responses, updates, or remote-service requests return through the controlled communication path.

This data flow can support several functions:

  • automatic crash notification and emergency calling;
  • remote diagnostics and fault reporting;
  • location, geofencing, and stolen-vehicle tracking;
  • fleet usage and maintenance information;
  • remote status checks and selected vehicle commands;
  • data transport for OTA software updates;
  • connectivity for infotainment or onboard Wi-Fi;
  • communication with external road or vehicle infrastructure.

Not every TCU supports every function. A commercial-vehicle fleet unit and an OEM passenger-car module may have different networks, environmental limits, security requirements, data rates, and service lives. Those differences change the component set, PCB complexity, assembly process, and validation plan.

What Components Are Inside a Telematics Module?

A telematics module normally combines a computing section, wireless communication section, vehicle interfaces, power conditioning, and protection. The components are selected as a system because a failure in one section can interrupt the complete data path.

Hardware block Typical purpose Manufacturing concern
Processor or MCU Runs communication, diagnostics, security, and control tasks Fine-pitch package, programming, thermal load
Cellular modem Connects the vehicle to mobile networks BGA/LGA joints, controlled supply rails, RF path
GNSS receiver Provides position and timing RF sensitivity, shielding, antenna connection
Memory and secure device Stores software, logs, keys, or credentials Package orientation, programming, traceability
CAN/LIN/Ethernet transceivers Connect the TCU to in-vehicle networks ESD protection, termination, connector routing
Power-management devices Convert and supervise vehicle power Thermal dissipation, transient-rated parts, solder quality
RF filters and matching parts Condition cellular, GNSS, Wi-Fi, or V2X signals Small components, placement accuracy, approved substitutions
Connector system Links power, vehicle networks, antennas, and service ports Coplanarity, pin soldering, mechanical support

The BOM must identify the complete manufacturer part number, package, grade, approved alternatives, and any programming or traceability requirements. A generic description such as “LTE module” or “GNSS filter” is not enough for controlled sourcing. Devices with similar commercial descriptions may differ in frequency bands, qualification status, firmware, temperature range, package revision, moisture sensitivity, or lifecycle status.

Long-lead wireless modules, processors, secure devices, automotive connectors, and memory parts deserve early supply-chain review. If an alternative part changes the footprint, RF behavior, power demand, firmware interface, or qualification status, it is an engineering change—not a routine purchasing substitution.

How Do Cellular, GNSS, and Vehicle Networks Work Together?

Cellular, GNSS, and vehicle-network circuits perform different jobs but meet at the TCU processor. Vehicle networks provide information from inside the vehicle, GNSS supplies position and timing, and cellular communication carries selected data between the vehicle and remote services.

The processor controls that exchange. It decides which vehicle messages are relevant, manages communication sessions, stores data when coverage is unavailable, and sends queued information after the connection returns. It may also coordinate Wi-Fi, Bluetooth, or V2X hardware when those functions are part of the product.

These interfaces create several hardware interactions:

  • a cellular transmitter can generate noise that reduces GNSS receiver sensitivity;
  • digital clocks and high-speed memory can couple noise into RF circuits;
  • vehicle-network transients can enter through harness connections;
  • modem transmit bursts can create rapid changes in power demand;
  • enclosure, cable, shielding, and antenna placement can alter RF performance;
  • sleep and wake behavior can affect both current consumption and network availability.

The PCBA must therefore preserve the separation and reference structures defined by the released design. During manufacturing review, the supplier can check whether the stackup, impedance requirements, fabrication notes, component footprints, assembly clearances, shield features, and test points are producible. The product owner remains responsible for proving antenna performance, protocol behavior, wireless certification, security, and operation in the intended vehicle.

telematics control unit

What Makes an Automotive Telematics Control Unit Difficult to Assemble?

An automotive telematics control unit is difficult to assemble because its PCBA combines dense digital electronics, RF circuits, vehicle power, large connectors, and hidden solder joints. A process that works for a simple controller may not provide enough control for this mixture.

Depending on the released design, a TCU may combine RF sections, high-speed digital interfaces, controlled-impedance routing, and multilayer PCB stackup requirements on the same assembly.

Important production challenges include:

  • Mixed component geometry: The same board may contain small RF passives, BGAs, QFNs, modules, shields, and large through-hole connectors. Stencil design and reflow settings must support different solder-volume and thermal demands.
  • Hidden solder joints: Modems, processors, memory, and power packages may use BGA, LGA, QFN, or bottom-terminated packages. AOI cannot see every critical joint, so the inspection plan may require X-ray.
  • Module coplanarity: A wireless module with many edge or underside pads can produce opens or uneven soldering if paste deposition, placement pressure, warpage, or reflow is poorly controlled.
  • RF component sensitivity: Matching components are often small and value-specific. A wrong value, rotated device, tombstone, or unauthorized alternative can change performance even when the board powers on.
  • Shield and connector assembly: Shield frames, coaxial connectors, and vehicle connectors can introduce thermal imbalance, mechanical stress, or secondary soldering operations.
  • Vehicle power conditions: Protection and power components may carry higher current or dissipate more heat than the digital section. Their joints, copper connections, and thermal interfaces need suitable process control.
  • Programming and identity: The assembly may require boot code, secure provisioning, serial numbers, MAC addresses, or customer-specific labels. The exact responsibility and data-handling method must be agreed before production.

Manufacturing review should happen before material release. Conflicts among the Gerber or ODB++ data, BOM, pick-and-place file, assembly drawing, programming instruction, and test specification can otherwise reach the line as different interpretations of the same product revision.

Which Assembly Defects Should TCU Manufacturing Testing Detect?

TCU manufacturing testing must detect more than a board that is completely dead. An assembly defect can produce intermittent communication, weak RF performance, unexpected resets, high standby current, unreliable vehicle-network data, or failures that appear only after temperature or vibration changes.

Common defect paths include:

  • insufficient solder or opens beneath BGA, LGA, QFN, and module pads;
  • solder voiding beneath power or thermal pads;
  • bridges around fine-pitch processors, transceivers, and connectors;
  • missing, wrong-value, shifted, or tombstoned RF passives;
  • poor wetting on shield frames or large ground connections;
  • damaged coaxial or board-to-board connectors;
  • excessive residue or contamination near high-impedance and RF sections;
  • cracked joints caused by connector insertion or board handling;
  • incorrect component revision or an unapproved BOM substitute;
  • incomplete programming, duplicated identifiers, or mismatched firmware files.

No single inspection method finds all of these problems. SPI can verify solder-paste deposition before placement. AOI can identify visible polarity, placement, and solder defects. X-ray can examine concealed joints and voiding. Electrical tests can detect opens, shorts, supply problems, and selected component values. A functional fixture can exercise defined power, communication, and I/O behavior.

The acceptance plan should connect each important risk with an appropriate check. For example, an AOI record cannot prove cellular sensitivity, and a successful network connection cannot prove that every hidden solder joint has acceptable process quality. Inspection evidence and system-performance evidence answer different questions.

telematics control unit

How Do You Choose a PCBA Manufacturer for a Telematics Unit?

Choose a PCBA manufacturer whose experience covers the difficult parts of the TCU assembly, not only general SMT production. EBest Circuit has experience with the component, process, inspection, and traceability controls that these mixed RF and automotive electronics projects require.

Our relevant experience includes:

  • assembling BGA, LGA, QFN, RF modules, shield structures, and mixed SMT/THT boards;
  • checking BOM data and complete manufacturer part numbers before purchasing;
  • controlling component alternatives and obtaining customer engineering approval before release;
  • managing moisture-sensitive devices and baking requirements where applicable;
  • using SPI, AOI, X-ray, electrical testing, and agreed functional testing for different acceptance needs;
  • supporting programming, serialization, labeling, and production-data traceability;
  • completing first-article inspection before volume release;
  • maintaining board, production-lot, revision, and critical-component traceability;
  • working with customer fixtures, test limits, software, and golden samples;
  • separating PCBA manufacturing acceptance from antenna, wireless-network, firmware, cybersecurity, and vehicle-level validation.

These controls help prevent a TCU project from being released only because the assembly looks complete. Depending on the agreed scope, production evidence can include first-article results, AOI or X-ray records for defined features, programming logs, serial-number records, electrical-test results, functional-test reports, and approved nonconformance records.

EBest Circuit can review the released PCB and assembly package, identify manufacturing conflicts, source specified components, assemble the mixed-technology PCBA, and coordinate the inspection and customer-defined testing included in the quotation. Broader automotive PCB assembly controls may also apply, while each TCU project should still define its critical components, inspection points, test limits, and required records.

FAQs About the Telematics Control Unit

Is a telematics control unit the same as an ECU?

A TCU is a type of automotive electronic control unit focused on external connectivity and telematics functions. “ECU” is the broader term for vehicle controllers. An electronic control unit board may support engine, body, chassis, battery, gateway, or other functions, while a TCU specifically manages vehicle-to-network communication and related services.

Is a TCU the same as a transmission control unit?

No. Both may use the abbreviation TCU. In this article, TCU means telematics control unit. A transmission control unit manages transmission operation and is a different automotive controller.

Does every telematics control unit include 5G?

No. The wireless technology depends on product generation, target region, service requirements, network availability, cost, and lifecycle plan. A TCU may use LTE, 4G, 5G, satellite communication, or another approved connection. The exact modem and supported bands must be defined in the product specification and BOM.

Can AOI prove that a TCU PCBA will communicate correctly?

No. AOI checks visible assembly characteristics such as component presence, position, polarity, and selected solder features. Communication performance requires suitable electrical, programming, RF, network, and system-level tests. X-ray may also be required for concealed solder joints.

What testing can a PCBA manufacturer perform for a TCU?

The available scope may include SPI, AOI, X-ray, electrical testing, programming, interface checks, and customer-defined functional testing. Antenna performance, cellular certification, GNSS performance, cybersecurity, cloud communication, vehicle integration, and regulatory approval normally require additional product- or system-level validation defined by the customer.

If you need PCB fabrication or PCBA support for a telematics control unit, send the released board data, BOM, component-placement file, drawings, programming instructions, test requirements, quantity, and required production records to sales@bestpcbs.com for review.

Tags: , ,
Posted in Automotives, best pcb, bestpcb, Solutions | No Comments »

TQFP Package: Dimensions, Pin Counts, LQFP/QFN Comparison & PCB Guide

September 17th, 2026

The TQFP package remains widely used for microcontrollers, mixed-signal ICs, communication devices, motor-control ICs, and other components that need moderate to high I/O counts without moving to BGA packaging. Their exposed gull-wing leads also make them attractive when visual solder inspection, prototyping, and rework matter.

The main challenge is that “TQFP64” or “TQFP100” does not uniquely define a package. Two ICs can have the same TQFP pin count but different body sizes, lead pitches, or overall dimensions. For PCB designers, the correct workflow is therefore part number → package drawing → land pattern, not pin count → generic footprint.

TQFP package overview showing thin body gull-wing leads visible solder joints and common pin counts

Key Takeaways

  • TQFP stands for Thin Quad Flat Package, a surface-mount IC package with gull-wing leads extending from all four sides.
  • TQFP is a package family, not one fixed footprint. Pin count alone does not determine body size, lead pitch, or PCB land pattern.
  • Common examples include TQFP32, TQFP44, TQFP48, TQFP64, TQFP100, and TQFP144, but dimensions can vary between semiconductor manufacturers.
  • For example, NXP lists both 10 × 10 mm and 7 × 7 mm TQFP64 packages, showing why “TQFP64” is not enough information for footprint selection.
  • TQFP and LQFP are closely related QFP variants, but package names alone do not guarantee footprint compatibility.
  • Compared with QFN, TQFP uses visible gull-wing leads, which makes solder-joint inspection and rework easier but requires more PCB area.
  • PCB footprints should always be built from the exact manufacturer package drawing, including pitch, body size, overall lead span, lead width, lead length, and package orientation.

What Is a TQFP Package?

TQFP stands for Thin Quad Flat Package, it is a surface-mount package with leads extending from all four sides of a thin molded body. It belongs to the broader QFP, or Quad Flat Package, family. The leads are formed into a gull-wing shape so they can sit on PCB pads and be soldered by standard SMT reflow processes.

Typical TQFP characteristics include:

  • Leads on four sides
  • Gull-wing lead shape
  • Surface-mount assembly
  • Relatively low package profile
  • Fine lead pitch
  • Visible solder joints
  • Pin counts from a few dozen to well above 100

A TQFP package is commonly used when the IC needs more I/O than SOIC or similar two-sided packages can provide but the design does not require BGA-level interconnect density.

How Is a TQFP Package Constructed?

A TQFP package normally contains a silicon die mounted inside a molded plastic body and electrically connected to an external lead frame.

Its basic construction includes:

  • Silicon die
  • Die attach material
  • Bond wires or equivalent internal interconnection
  • Copper-alloy lead frame
  • Mold compound
  • Gull-wing leads
  • Pin 1 orientation mark

The lead frame carries signals from the silicon die to the external terminals. After molding, the leads extend outward from all four sides and bend downward toward the PCB.

The package body itself is smaller than the total installed footprint because the leads extend beyond the molded body. This distinction matters during placement and land-pattern design.

Exploded TQFP package construction showing mold compound silicon die bond wires lead frame gull-wing leads and pin 1

What Dimensions Define a TQFP Package?

TQFP package dimensions include several mechanical values, not just the molded body width.

Parameter What It Describes
D × E Molded body length and width
HD × HE or overall D × E Total span including leads
A Overall package height
A1 Standoff above the PCB seating plane
e Lead pitch
b Lead width
L Gull-wing lead length
N Total lead count

Body size and overall lead span are not the same dimension. A PCB footprint designed only from the stated body size can miss the additional space occupied by the gull-wing leads.

TQFP package dimension drawing showing body size overall lead span pitch height lead width and lead length

TQFP32, 44, 48, 64, 100 and 144: What Are the Common Dimensions?

TQFP packages appear in many pin counts, but the following values should be treated as representative package examples rather than universal dimensions.

Package Example Representative Body Size Representative Pitch
TQFP32 7 × 7 mm 0.80 mm
TQFP44 10 × 10 mm 0.80 mm
TQFP48 7 × 7 mm 0.50 mm
TQFP64 7 × 7 or 10 × 10 mm examples 0.40 or 0.50 mm examples
TQFP100 14 × 14 mm 0.50 mm
TQFP144 16 × 16 mm example 0.40 mm

The package name should therefore never replace the exact IC mechanical drawing.

Representative TQFP32 TQFP44 TQFP48 TQFP64 TQFP100 and TQFP144 package examples

Does the Same TQFP Pin Count Always Mean the Same Footprint?

No. The same TQFP pin count does not guarantee the same body size, lead pitch, lead span, or PCB footprint.

TQFP64 is a clear example. Different vendors offer 64-pin packages in multiple body sizes and pitches, so a CAD library entry named only “TQFP64” is not sufficiently specific for production.

Before reusing a footprint, compare:

  • Body dimensions
  • Overall lead span
  • Lead pitch
  • Lead width
  • Lead length
  • Package height
  • Pin 1 orientation

A footprint can look plausible on screen and still be completely incompatible with the physical component.

TQFP64 comparison showing same 64 pin count with 7 by 7 mm and 10 by 10 mm packages and different pitch

TQFP vs QFP: What Is the Difference?

QFP is the broader Quad Flat Package family, while TQFP is a thinner-profile member of that family.

Both use:

  • Leads on four sides
  • Gull-wing terminals
  • Surface-mount assembly
  • Similar general soldering methods

The difference is mainly in the mechanical outline and package profile. TQFP should therefore not be treated as a package technology completely separate from QFP; it is better understood as a thinner mechanical implementation within the same four-sided leaded package concept.

TQFP vs LQFP: What Is the Difference?

In a TQFP vs LQFP package comparison, both are closely related low-profile QFP variants. Their naming conventions can overlap enough that engineers should compare actual mechanical drawings instead of relying on the acronym.

Feature TQFP LQFP
Full name Thin Quad Flat Package Low-Profile Quad Flat Package
Leads Gull-wing Gull-wing
Mounting SMT SMT
Typical profile Thin Low profile
Common pitch range 0.4–0.8 mm 0.4–0.8 mm
Footprint compatibility Only if full outline matches Same rule

Never assume that TQFP and LQFP are footprint-compatible just because the pin count is the same.

TQFP vs QFN: Which Is Easier for PCB Assembly?

In a TQFP vs QFN package comparison, TQFP is generally easier to inspect and rework because its gull-wing leads and solder joints are visible around the package perimeter.

Assembly Factor TQFP QFN
External leads Gull-wing Leadless bottom pads
Solder-joint visibility High Limited
AOI access Good Bottom joints less visible
X-ray requirement Usually not essential Often useful
Manual rework Easier More difficult
PCB area Larger Smaller
Fine-pitch defect risk Bridging / opens Insufficient wetting / voids
Thermal pad Package dependent Common on many QFNs

QFN can save significant PCB area and often offers a shorter electrical and thermal path, while TQFP remains attractive when inspection access and rework matter.

TQFP versus LQFP versus QFN package comparison

How Should a TQFP PCB Footprint Be Designed?

A TQFP PCB footprint should be created from the exact semiconductor manufacturer’s land-pattern or package drawing, not from a generic pin-count template.

Check these dimensions first:

  • Lead pitch
  • Lead width
  • Lead length
  • Molded body size
  • Overall lead span
  • Pin 1 orientation
  • Seating-plane information
  • Package tolerances

The PCB land pattern must also provide suitable solder fillets around the gull-wing leads. Toe, heel, and side fillets depend on the package geometry and the chosen land-pattern standard.

Also include clear pin 1 marking, solder-mask clearance, silkscreen that does not overlap pads, component courtyard, pick-and-place origin, and adequate neighboring-component clearance.

TQFP PCB footprint design showing pad length pitch solder mask clearance courtyard and pin 1

What SMT Assembly Problems Are Common with TQFP Packages?

The most common TQFP assembly defects involve fine-pitch leads, solder-paste volume, placement accuracy, and lead coplanarity.

Typical issues include:

  • Solder bridging
  • Insufficient solder
  • Open joints
  • Bent leads
  • Lifted leads
  • Lead coplanarity problems
  • Component misalignment
  • Wrong orientation
  • Contamination around fine-pitch pads

Solder bridging is especially common when pad geometry, stencil aperture, paste volume, or placement is poorly controlled. Fine-pitch packages leave little margin between adjacent solder deposits.

A robust SMT process may use solder paste inspection, accurate placement, controlled reflow, AOI, microscope inspection, and X-ray when hidden structures also require it.

Common TQFP SMT assembly defects including solder bridge open joint bent lead and misalignment

When Is TQFP a Good Package Choice?

TQFP is a practical choice when the design needs a moderate or high pin count while keeping solder joints visible and accessible.

It works particularly well for:

  • Microcontrollers
  • Industrial control ICs
  • Motor-control devices
  • Mixed-signal ICs
  • Communication controllers
  • Prototype and low-to-medium-volume assemblies
  • Products where rework access matters

TQFP may be less attractive when the design requires extremely high I/O density, minimum PCB area, very short high-speed interconnects, exceptional thermal dissipation, or package sizes smaller than exposed-lead QFP can provide.

For many industrial, automotive-control, instrumentation, and embedded applications, the additional board area is acceptable because the visible leads simplify inspection and troubleshooting.

FAQ About TQFP Packages

1. What does TQFP stand for?
TQFP stands for Thin Quad Flat Package. It is a surface-mount IC package with gull-wing leads on all four sides.

2. Is TQFP a surface-mount package?
Yes. TQFP is designed for surface-mount PCB assembly and is commonly soldered using SMT reflow.

3. What is the typical TQFP64 package size?
A common TQFP64 example is 10 × 10 mm with 0.5 mm pitch, but 7 × 7 mm TQFP64 packages also exist. Always check the exact IC datasheet.

4. What is the typical TQFP100 package size?
A common TQFP100 example is 14 × 14 mm with 0.5 mm lead pitch. Always verify the actual manufacturer drawing.

5. Is TQFP the same as LQFP?
No. They are closely related QFP variants, but the package profile and mechanical outline can differ. Some specific TQFP and LQFP parts may share a footprint only when all relevant dimensions match.

6. Can every TQFP with the same number of pins use the same PCB footprint?
No. Pin count alone does not define body size, pitch, lead span, or land pattern. A TQFP64, for example, can exist in multiple mechanical outlines.

If you are moving a TQFP-based design into fabrication or assembly, EBest Circuit can review the component package drawing, footprint, pad geometry, stencil requirements, orientation, BOM, and PCBA manufacturability before production. Send your Gerber files, BOM, placement files, and component datasheets to sales@bestpcbs.com for DFM review.

Tags: , , , ,
Posted in best pcb, Electrical Components, PCB Design, SMT Technology | No Comments »

PCB Thermocouple Placement for Reflow Profiling and Temperature Measurement

September 17th, 2026

A PCB thermocouple records how hot a specific point on an assembly gets during reflow and how long it stays there. Place sensors where a joint may heat too slowly or a component may get too hot, then secure them so the readings reflect the assembly rather than the attachment. The profile must show that critical joints receive enough heat without exceeding the monitored component limits.

PCB Thermocouple, instrumented circuit board connected to a reflow profiling data logger

What Is a PCB Thermocouple and What Does It Measure During Reflow?

A PCB thermocouple is a welded junction of two dissimilar conductors fixed to a defined point on a populated circuit board. It records local temperature versus time at the junction; it does not measure the oven setpoint or provide one temperature for the whole assembly.

The contact point determines what the curve represents. A junction attached to a lead heel or pad can track solder-joint heating. A package-top junction checks component-body temperature. A sensor suspended above the board measures local air and cannot prove that a hidden termination reached the required soldering window.

Keep the conductors insulated up to the welded bead. If the bare wires touch before that bead, the contact can become a second measuring junction and shift the apparent location. Record the component reference, exact contact point, attachment method, channel number, and measurement purpose before the run.

Why Does PCB Thermocouple Placement Affect Temperature Measurement Accuracy?

A temperature trace is useful only when its sensing point represents the joint or component being checked. Joints connected to large copper areas may heat slowly, while exposed edge components may reach a higher peak. A well-attached sensor at a convenient but unrelated spot can still give the wrong basis for setting the oven recipe.

  • Thermal mass: Large connectors, shields, transformers, and dense component groups usually heat more slowly than small exposed devices. Place the junction on the joint or body that could limit the process.
  • Copper connection: A pad tied to a plane or heavy copper can lag behind a nearby isolated pad. Check the actual copper path instead of assuming adjacent joints behave alike.
  • Airflow exposure: Board edges, leading corners, and unshielded parts may heat faster than central or shadowed areas. Add separate points when orientation or panel position changes airflow.
  • Attachment mass: Excess solder or thick adhesive slows sensor response. The bead should touch the target directly with only enough material to hold it.
  • Measurement target: Package temperature and joint temperature are different acceptance checks. Label every channel by both location and purpose.

Where Should Thermocouples Be Placed on a PCB for Reflow Profiling?

Place thermocouples at the points most likely to narrow the reflow process window. The minimum plan covers a suspected cold joint, a suspected hot point, and any component or termination with a critical temperature requirement. Add panel positions only when copper distribution, component loading, or airflow can make them thermally different.

Multiple fine-wire thermocouples attached to different thermal-risk locations on a populated PCB panel

Choose candidate points from the assembly drawing, BOM, copper layout, panel orientation, and component limits. A cold-joint point matters when insufficient heat there could prevent an otherwise acceptable recipe; it need not be the lowest reading anywhere on the board.

Profile Point Recommended Location Verification Target
Cold joint Critical pad tied to a large plane, heavy copper, or high-mass component Peak and time above liquidus at the slowest relevant joint
Hot point Small exposed component or joint near a board edge Maximum temperature and available upper margin
Critical joint Exact lead heel, pad, or accessible hidden termination tied to reliability risk Solder-joint thermal exposure at the required connection
Sensitive part Specified package-body or lead location Component temperature limit
Panel variation Representative edge, center, leading, and trailing assemblies Temperature spread caused by panel position

Mark each location on an assembly drawing or photograph, including the exact contact point and why it is monitored. “TC4—U12 corner ball—cold-joint check” is more useful than “TC4” alone.

How Many Thermocouples Should Be Used for PCB Reflow Profiling?

Use enough channels to cover the thermal risks that could change the oven recipe. Roughly three to five points may cover a small, uniform assembly; a large panel or mixed-mass board may need six to twelve or more. The number depends on the actual risks, not a fixed profiling rule.

  • Cover both extremes: Include at least one predicted cold location and one predicted hot or temperature-sensitive location.
  • Add critical interfaces: Give separate channels to hidden terminations, high-reliability joints, or body limits that cannot be represented by the existing points.
  • Sample real panel differences: Add edge, center, leading, or trailing positions only where layout and airflow make a different result plausible.
  • Avoid measurement disturbance: Do not fill spare channels without a purpose. Dense wire bundles can alter airflow, pull on junctions, or interfere with the conveyor.

If the profiler lacks enough inputs, divide the plan into controlled repeat runs. Keep the oven recipe, conveyor direction, assembly state, and at least one reference channel unchanged so the groups can be compared.

Which Thermocouple Type and Wire Size Are Suitable for PCB Temperature Measurement?

Fine-wire Type K thermocouples are commonly suitable for electronics reflow profiling when they match the profiler input, connector polarity, temperature range, and insulation rating. A smaller conductor responds faster and disturbs a small joint less; a larger conductor is more durable but conducts more heat and needs more routing space.

About 0.2 mm wire is a practical choice for accessible joints; about 0.1 mm may help reach a BGA or fine-pitch target. These are examples, not required sizes. Choose a wire fine enough for the contact point but robust enough to stay attached through the planned runs.

  • Profiler match: Confirm thermocouple type, connector type, polarity, and channel configuration before installation.
  • Target access: Use finer wire when the junction must reach a hidden or closely spaced termination without bridging nearby conductors.
  • Thermal response: Keep the welded bead and exposed conductor length small enough to follow the target rather than surrounding air.
  • Mechanical life: Use insulation and strain relief that can survive the full oven cycle without softening, shorting, or contaminating the assembly.

How Should Thermocouples Be Attached and Routed on a PCB?

Fix the welded junction in direct, low-mass contact with the target and strain-relieve the wire before routing it toward the rear of conveyor travel. High-temperature solder is effective on accessible metal points; qualified high-temperature adhesive may suit package surfaces. Tape is better used for lead restraint than as the only precision contact at a solder joint.

Fine-wire thermocouple junction attached to a component lead with flat routing and tape strain relief
  1. Prepare the point: Clean and identify the exact pad, lead, joint, or package location. Confirm that the selected point matches the channel plan.
  2. Attach the bead: Use the smallest secure amount of high-temperature solder or approved adhesive. Under magnification, the junction should touch the target directly.
  3. Add strain relief: Restrain the lead a short distance from the bead. A gentle pull on the cable should not move the sensing point.
  4. Route the wire: Keep it close to the board, away from moving hardware and hot oven surfaces, and clear of the local airflow being measured.
  5. Check the channel: Verify continuity, polarity, channel label, and room-temperature response before the board enters the oven.

When high-temperature solder is used, the attachment alloy must remain solid during the measured cycle. Remove incompatible low-melting solder from a sacrificial profile point where necessary, and avoid a large solder fillet that would add thermal mass.

What Thermocouple Placement Challenges Occur with BGAs, QFNs, Large Components, PCB Panels?

Hidden joints, component bodies, and panel positions cannot all be judged from the same sensing point. When a joint cannot be instrumented directly, a nearby reading can help investigate heating, but it must not be reported as that joint’s temperature.

  • BGA: A package-top sensor measures body temperature. It does not prove solder-ball temperature. Direct joint measurement may require a sacrificial assembly and controlled underside access to a selected ball.
  • QFN or LGA: An exposed perimeter pad may not represent the center thermal pad. Use underside access or a purpose-built profile sample when center-joint behavior controls the decision.
  • Large component: Connectors, transformers, and shields can create a slow joint while the component body has a separate maximum-temperature limit. Monitor both when either can restrict the recipe.
  • PCB panel: Measure representative edge, center, leading, and trailing positions when panel layout or airflow can create a meaningful thermal gradient. Compare those positions before assuming that one assembly’s profile represents every board in the panel.
  • Dense assembly: If simultaneous wiring would disturb airflow or prevent safe conveyor travel, use controlled repeat runs with a stable reference channel.

How Do You Evaluate Temperature Data from PCB Thermocouples During Reflow?

Compare each curve with the requirement for the point it actually measures. Joint traces use the selected solder-paste and alloy limits; component-body traces use the applicable component limit. Oven zone settings and conveyor speed are inputs, while the thermocouple curves show the temperature experienced by the assembly.

  • Ramp rate: Calculate the heating slope where required and check whether fast and slow locations remain within the applicable process limits.
  • Soak: Check the time and temperature range specified for the selected paste process, rather than applying a generic soak target.
  • Time above liquidus: For each critical joint, measure the interval between the trace rising above and falling below the alloy’s liquidus temperature. Compare that interval with the selected paste’s process window.
  • Peak temperature: Compare joint and package peaks with their own limits; one peak limit should not be applied to every channel.
  • Cooling rate: Review the cooling slope when it is part of the product or paste requirement.
  • Temperature spread: Compare decision-relevant channels in the same run. A cold joint and a hot package must both meet their respective limits; a small spread by itself does not prove either result.

Accept a recipe only when every critical joint and monitored package meets its own limit in the same run. If improving a cold joint pushes a component past its limit, change one controlled input—such as zone temperature, conveyor speed, or orientation—and profile again. Compare the new traces against the same channel locations and requirements.

What Causes Inaccurate PCB Thermocouple Temperature Measurements?

The most common causes are a moved junction, excessive attachment mass, damaged wiring, incorrect profiler setup, or a sensor placed on the wrong thermal object. Diagnose the trace together with the physical installation and channel record.

Trace Pattern Likely Cause Corrective Check
Abrupt step or drift Junction moved or lifted Inspect the bead and strain relief; repair and repeat
Intermittent spikes Loose connector, broken wire, or unintended conductor contact Check continuity, insulation, polarity, and connector seating
Unusually slow response Excess solder, thick adhesive, or heavy wire Compare with a lower-mass attachment at the same target
Smooth curve but poor soldering result Wrong target or surface proxy used as joint data Match the channel record and photographs to the physical contact point
Poor run-to-run agreement Attachment damage or changed loading, orientation, or board condition Repeat under controlled conditions with one stable reference channel
All channels shifted Wrong thermocouple type, logger setup, or cold-junction compensation Verify the profiler configuration and perform a known-temperature check

A smooth trace does not establish where the bead was attached. Reject a channel if its contact point cannot be confirmed after reflow, and repeat the measurement with a documented attachment.

How Can You Verify That PCB Thermocouple Measurements Are Reliable?

Check the sensor before and after reflow, confirm the profiler settings, and repeat the critical measurements. Compare runs only when the board revision, channel map, and oven recipe match.

  1. Inspect the installation: Verify bead contact, attachment size, insulation, strain relief, polarity, and connector seating. Save close-up photographs of every point.
  2. Test channel identity: At a stable room temperature, apply a controlled touch or heat stimulus to each junction. Only the expected channel should respond.
  3. Confirm the profiler: Check thermocouple type, sample interval, trigger, channel labels, and calibration status. Save the configuration with the run.
  4. Profile the real thermal load: Use the intended panel, component population, carrier, conveyor direction, and loading condition. Record any deviation.
  5. Inspect after reflow: Reject data from a junction that moved, lifted, shorted, or was damaged. Match accepted traces to the saved photographs.
  6. Repeat the run: Hold the recipe and assembly conditions constant, then compare peak, time above liquidus, ramp, and spread on the critical channels.

Reprofile when a change can alter heat transfer or the allowable window. Typical triggers include a new paste, a package or component-mass change, revised copper or stackup, a new panel layout, a different carrier, major oven maintenance, or transfer to another production line.

FAQs About PCB Thermocouple Placement and Reflow Profiling

Q1: Can a bare PCB be used for reflow profiling?

A1: A bare board cannot establish the final assembly profile. Components, solder deposits, shields, and connectors change thermal mass and airflow. Use a populated production-representative assembly or a documented equivalent profile vehicle for recipe approval.

Q2: Does changing solder paste require a new reflow profile?

A2: Reprofile if the required thermal window changes. Compare liquidus temperature, time above liquidus, soak guidance, peak range, and cooling requirements before using the existing recipe.

Q3: When does a design or BOM change require reprofiling?

A3: Reprofile when the change can affect heat transfer or a temperature limit. Large copper changes, board-thickness changes, added shields, heavier connectors, alternate packages, and revised sensitive components are common triggers.

Q4: Can a thermal camera replace attached thermocouples?

A4: A thermal camera can locate surface hot and cold regions, but it cannot automatically replace contact profiling. Emissivity, viewing angle, and line of sight limit the result, especially at hidden BGA and QFN joints.

Q5: Can the same profiling board be reused indefinitely?

A5: No. Set an inspection and retirement rule. Repeated heat cycles and handling can age the assembly, loosen attachments, and damage fine wires. Retire or rebuild the board when it no longer represents production.

Q6: What should be saved with a PCB reflow profile?

A6: Save enough data to reproduce the installation and oven run. Keep the raw traces, calculated metrics, channel map, attachment photographs, product and BOM revisions, paste identity, panel orientation, oven recipe, profiler settings, and calibration status.

For a PCBA quotation with reflow-profile or reporting requirements, send Gerber or ODB++, a BOM with exact part numbers, assembly and panel drawings, solder-paste requirements, quantity, target delivery date, and required profile or inspection records to sales@bestpcbs.com. Include any joints or component limits that need separate temperature measurements so the quotation can account for them.

Tags: , , ,
Posted in PCB Assembly / PCBA | No Comments »

Relay Diagram: 4-Pin, 5-Pin, 8-Pin Wiring & Symbols Explained

September 17th, 2026

A relay diagram is easier to understand once you stop viewing the relay as one component and instead divide it into two sections. A low-power control circuit energizes the coil, while electrically separate contacts switch another circuit that may operate at a different voltage or carry much higher current.

This distinction explains most 4-pin, 5-pin, 8-pin, 14-pin, and 12V relay diagrams. The contact arrangement changes from one relay type to another, but the reading method stays similar: identify the coil, determine the contact form, confirm the pin numbering, and then check the actual device datasheet before wiring or PCB layout.

Relay diagram showing 4-pin 5-pin and 8-pin relay wiring and symbols

Key Takeaways

  • A relay diagram shows how the relay coil controls one or more electrical contacts and how those contacts connect or disconnect the load circuit.
  • The easiest way to read any relay is to separate it into a control side and a load side. The coil belongs to the control side; COM, NO, and NC belong to the switched side.
  • On common automotive relays, terminals 85 and 86 are typically the coil, 30 is common, 87 is normally open, and 87a is normally closed.
  • A common 4-pin automotive relay is usually SPST and normally open, while a common 5-pin version adds a normally closed contact and behaves as an SPDT relay.
  • An 8-pin relay is often DPDT, while many 14-pin relays provide four changeover contact sets. Physical pin numbering is not universal, so the datasheet must still be checked.
  • Relay schematic symbols, wiring diagrams, pin diagrams, and PCB footprints describe different things. A correct schematic can still produce a wrong PCB if the footprint orientation or pin mapping is mirrored.
  • Coil polarity may matter when a relay contains an internal diode, LED, or other polarity-sensitive suppression component.

What Is a Relay Diagram?

A relay diagram shows the relay coil, switching contacts, terminal functions, and the electrical relationship between the control circuit and the load circuit.

Several diagram types are commonly called a “relay diagram,” although they provide different information:

  • Schematic diagram: Shows electrical function.
  • Wiring diagram: Shows how wires connect between devices.
  • Pin diagram: Shows terminal or pin assignments.
  • Internal relay diagram: Shows the coil and contact arrangement inside the relay.
  • PCB footprint: Shows the actual pad or hole positions used for board layout.

A schematic may tell you that a relay is SPDT, but it does not necessarily tell you which physical pin is at the top-left corner of the package. That information comes from the relay pinout or package drawing.

This is why a relay diagram should always be matched to the exact relay model before wiring or creating a PCB footprint.

How Does a Relay Diagram Separate the Control Side from the Load Side?

A relay diagram normally separates the device into a control side containing the coil and a load side containing the contacts.

The relationship can be simplified as:

Control voltage → Coil → Magnetic force → Moving contact → Load circuit changes state

The coil is electrically isolated from the switched contacts in a conventional electromechanical relay. Applying the rated coil voltage creates a magnetic field that moves an armature and changes the contact position.

For example, a 12V control signal may energize a relay coil while the contacts switch a higher-current lamp, motor, pump, heater, or another circuit.

Relay control side and load side showing coil magnetic actuation and isolated contacts

What Do Coil, COM, NO and NC Mean on a Relay Diagram?

Coil, COM, NO, and NC describe the main functional parts found in common electromechanical relay diagrams.

Marking Meaning Coil De-Energized
Coil Electromagnetic control input No magnetic actuation
COM Common moving contact Connected according to normal state
NO Normally Open Open
NC Normally Closed Connected to COM

The word “normally” means the relay coil is not energized. It does not describe the state during normal machine operation.

In an SPDT relay, COM connects to NC when the coil is off. When the coil is energized, the contact moves away from NC and connects COM to NO.

Relay contact terms showing COM NO and NC when coil is de-energized and energized

Relay Diagram Symbols: How Do You Read the Coil and Contacts?

Relay symbols show the electrical relationship between the coil and the contacts rather than the physical appearance of the relay.

A schematic typically includes:

  • A coil symbol
  • One or more contact symbols
  • NO or NC contact positions
  • A dashed mechanical relationship between the coil and contacts
  • A device designator such as K1, K2, RY1, or REL1

A dashed line between the coil and contacts represents mechanical linkage, not an electrical wire. When multiple contact sets share the same relay designation, one coil operates all of those contacts together.

4-Pin vs 5-Pin Relay Diagram: What Do 30, 85, 86, 87 and 87a Mean?

A common automotive 4-pin relay uses terminals 30, 85, 86, and 87, while the common 5-pin changeover version adds terminal 87a.

A 4 pin relay diagram shows the coil and normally-open switching path. A 5 pin relay diagram adds the 87a normally-closed path.

Terminal Common Automotive Function
85 Coil
86 Coil
30 Common power contact
87 Normally open contact
87a Normally closed contact

A typical 4-pin automotive relay is an SPST normally-open relay. With the coil off, 30 and 87 are open; when voltage is applied across 85 and 86, terminal 30 connects to 87.

A common 5-pin relay adds terminal 87a and usually operates as an SPDT changeover relay. With the coil off, 30 connects to 87a; when energized, 30 transfers to 87.

4-pin and 5-pin automotive relay diagram showing terminals 30 85 86 87 and 87a

How Do You Read an 8-Pin Relay Diagram?

An 8-pin relay is commonly a DPDT relay containing one coil and two independent changeover contact sets. An 8 pin relay diagram therefore shows both contact sets operated by the same coil.

Its internal functions normally include:

  • 2 coil terminals
  • 2 COM terminals
  • 2 NO terminals
  • 2 NC terminals

That gives a total of eight pins. Conceptually, the relay contains two SPDT switches operated by the same coil.

There is no universal physical numbering arrangement for every 8-pin relay. The relay case diagram and datasheet should therefore be checked before connecting an 8-pin socket or creating a PCB footprint.

8-pin DPDT relay diagram with two changeover contact sets

What Does a 14-Pin Relay Diagram Usually Show?

A 14-pin relay often provides four changeover contact sets operated by one coil, commonly described as 4PDT or 4CO.

A typical functional breakdown is:

  • 2 coil terminals
  • 4 COM terminals
  • 4 NO terminals
  • 4 NC terminals

That totals 14 electrical connections. These relays are common in industrial control panels, PLC interface circuits, interlocking systems, alarm circuits, machine control, and signal distribution.

As with 8-pin relays, the 14-pin count does not guarantee one universal physical pin sequence. Socket numbering and terminal arrangement must be verified against the exact part number.

How Do You Read a 12V Relay Wiring Diagram?

A 12V relay wiring diagram should be read by checking the coil circuit first and then tracing the switched load circuit.

  1. Confirm the coil voltage. Make sure the relay is actually rated for a 12V coil.
  2. Identify the coil pins. These may be 85/86 on automotive relays or A1/A2 on industrial designs.
  3. Identify COM, NO, and NC. Determine which contact state the application needs.
  4. Check coil polarity. A plain coil may not be polarity-sensitive, but an internal diode or LED can make polarity mandatory.
  5. Protect the control device. Use appropriate coil suppression when required.
  6. Fuse the load circuit. The relay does not replace proper overcurrent protection.
  7. Check contact current and voltage ratings. Motor and lamp loads may have high startup current.
  8. Confirm wire size and grounding. The wiring must suit the actual load current.
12V 4-pin relay wiring diagram showing supply fuse switch coil terminals 85 86 and contacts 30 87

Where Are 4-Pin and 5-Pin Relay Diagrams Commonly Used?

Four-pin and five-pin automotive relay diagrams appear in many systems where a low-current control signal operates a higher-current electrical load.

Application Typical Relay Role
Horn Switch controls higher-current horn circuit
Starter Ignition/control path operates starter solenoid circuit
Fuel pump ECU or control circuit switches pump supply
Auxiliary light Dashboard switch controls lighting load
Cooling fan Sensor or ECU controls fan motor
Compressor Control circuit switches compressor clutch
Heater Low-current controller switches heating load

A horn relay, starter relay, fuel-pump relay, or driving-light relay still follows the same basic coil-and-contact logic. The application name does not define the internal relay pinout, so the actual relay markings must still be checked.

Relay Diagram vs Wiring Diagram vs Pin Diagram: What Is the Difference?

A relay schematic, wiring diagram, pin diagram, and PCB footprint answer different engineering questions.

Diagram Type Main Question It Answers
Relay schematic What does the relay do electrically?
Wiring diagram Where should each wire connect?
Pin diagram Which physical terminal performs each function?
Internal diagram How are the coil and contacts arranged?
PCB footprint Where are the actual pads or holes?

A schematic may show an SPDT relay as a coil plus COM, NO, and NC contacts. The wiring diagram then shows how those terminals connect to the power supply, switch, and load.

A relay pin diagram maps those functions to physical relay pins. Finally, the PCB footprint converts the mechanical package into copper pads or plated through holes.

Relay schematic wiring diagram pin diagram and PCB footprint comparison

What Should You Check Before Using a Relay Diagram for PCB Design?

Before placing a relay on a PCB, verify the physical pinout against the exact manufacturer datasheet rather than relying on a generic relay diagram.

Important checks include:

  • Datasheet drawing orientation
  • Top view versus bottom view
  • Coil pin locations
  • COM / NO / NC pin mapping
  • Coil voltage
  • Coil current
  • Internal suppression components
  • Contact current and voltage rating
  • Load type
  • Contact resistance
  • PCB hole size
  • Pad diameter
  • Relay body clearance

The coil also affects the surrounding circuit. A microcontroller normally cannot drive many relay coils directly, so the PCB may need a BJT or MOSFET driver, base or gate resistor, flyback diode, LED indicator, optocoupler, or separate relay supply rail.

For higher-voltage loads, creepage and clearance between the control side and switched contacts must also be reviewed. A correct schematic symbol can still produce a wrong PCB if the footprint is mirrored or the physical pinout is interpreted from the wrong viewing direction.

EBest Circuit can review relay footprints, driver circuits, through-hole assembly, isolation spacing, trace current capacity, and PCBA requirements during DFM before fabrication.

FAQ About Relay Diagrams

1. What does a relay diagram show?
A relay diagram shows the relationship between the coil and switching contacts, including functions such as COM, NO, and NC.

2. What do 85 and 86 mean on a relay?
They are commonly the coil terminals on standard automotive relays. The actual relay marking or datasheet should still be checked.

3. What is the difference between a 4-pin and 5-pin relay?
A common 4-pin automotive relay provides a normally-open switching path, while a common 5-pin changeover relay adds terminal 87a for the normally-closed path.

4. What is an 8-pin relay diagram?
An 8-pin relay is commonly a DPDT relay with two changeover contact sets and one coil. Physical pin numbering varies by model.

5. Does relay coil polarity matter?
Not always. Polarity becomes important when the relay contains an internal diode, LED, or another polarity-sensitive suppression circuit.

6. Can I use the same relay diagram for every relay with the same number of pins?
No. The same pin count can be used by relays with different contact forms, internal features, and physical pin assignments. Always verify the exact datasheet.

Designing a PCB Around a Relay?

A relay diagram explains the electrical switching function, but reliable PCB implementation also depends on the actual footprint, coil driver, suppression method, load current, isolation spacing, and assembly process.

EBest Circuit supports relay control PCB fabrication, through-hole and SMT assembly, DFM review, component sourcing, and functional testing. If you have a similar control-board project, send your Gerber files, BOM, schematic, and relay specifications to sales@bestpcbs.com for engineering review.

Tags: , , , ,
Posted in best pcb, Electrical Components, Industrial Control, PCB Design | No Comments »

PCB Test Coupons: Types, Testing & IPC Guide

September 17th, 2026

PCB test coupons are representative test structures placed on the same fabrication panel as the production boards. They are built with the same materials, copper plating, lamination, drilling, and other key processes so manufacturers can verify characteristics such as controlled impedance, plated-hole quality, via reliability, registration, and solderability without cutting into the finished PCB.

Different PCB test coupons serve different purposes. Impedance coupons are commonly checked with TDR, while structural coupons can be microsectioned to inspect plating and internal alignment. The coupon design should reflect the actual production stackup and fabrication process.

PCB test coupons integrated into the panel rail of a production PCB panel

What Is a PCB Test Coupon?

A PCB test coupon is a dedicated test structure manufactured on the same panel as the production PCB to represent selected features of the finished board.

Unlike the functional PCB, the coupon is created specifically for inspection or measurement. Depending on the requirement, it may reproduce:

  • Controlled-impedance traces
  • Plated through holes
  • Microvias or blind vias
  • Internal layer registration features
  • Copper plating structures
  • Solderability features

The key point is representation. A useful coupon should experience the same relevant fabrication processes as the board it is intended to represent.

PCB test coupons are commonly placed in the panel rail or other non-product area, so testing does not consume a usable PCB.

At EBest Circuit, coupon requirements can be reviewed together with the production stackup during DFM. For controlled-impedance, HDI, RF, or high-reliability boards, this helps keep the test structure aligned with the actual PCB manufacturing conditions.

Why Are Test Coupons Used Instead of Testing the Production PCB?

PCB test coupons allow measurements and destructive inspections to be performed without damaging the production board.

Some verification methods cannot be carried out conveniently on a finished PCB. Microsection analysis, for example, requires the sample to be cut, mounted, polished, and inspected under magnification.

Coupons also provide a more consistent structure for tests such as TDR because production routing may contain:

  • Vias
  • Pads
  • Connectors
  • BGA breakouts
  • Plane changes
  • Short trace segments

These features can make measurement results harder to interpret.

A dedicated coupon can reproduce the required stackup and trace geometry while providing enough length and accessible test points for repeatable measurement.

The coupon therefore does not replace electrical or functional testing of the PCB. It provides process evidence for specific fabrication characteristics.

What Types of PCB Test Coupons Are Commonly Used?

PCB test coupon types are usually selected according to what needs to be verified rather than by using one universal coupon design.

Coupon / Test Structure What It Checks Typical Test Method
Impedance coupon Single-ended or differential impedance TDR
PTH structural coupon Hole wall plating and registration Microsection
Via reliability coupon Via or interconnect integrity Thermal stress / resistance monitoring
Microvia coupon HDI microvia quality and stacking Microsection / reliability test
Solderability coupon Solder wetting performance Solderability test
Peel-strength coupon Copper adhesion Peel test
SIR coupon Surface insulation resistance Electrical resistance testing

Some IPC qualification and conformance structures use letter-based coupon designations. However, for most PCB buyers and engineers, the more useful question is not the letter itself but what manufacturing characteristic the coupon is intended to verify.

Common PCB test coupon types including impedance plated through-hole microvia via reliability solderability and SIR coupons

What Can PCB Test Coupons Verify?

PCB test coupons can verify several manufacturing characteristics that are difficult to confirm from visual inspection alone.

Common checks include:

  • Controlled impedance
  • Copper plating thickness
  • Plated through-hole integrity
  • Microvia quality
  • Annular ring condition
  • Internal layer registration
  • Solderability
  • Copper adhesion
  • Interconnect reliability

For example, an impedance coupon can confirm whether a nominal 50 Ω or 100 Ω structure is within tolerance after lamination, plating, and etching.

A microsection coupon serves a different purpose. It allows the manufacturer to inspect the actual cross-section of a plated hole or via and evaluate conditions such as copper distribution, registration, and interface quality.

PCB test coupon illustrating impedance trace geometry plating via quality and layer registration verification

Where Are Test Coupons Located on a PCB Panel?

PCB test coupons are usually placed in the panel rail or another non-functional area of the production panel.

This position allows the coupon to travel through the same major fabrication processes as the PCBs while remaining separate from the customer’s usable board outline.

A useful coupon should be positioned so that it represents the production process as closely as practical, especially for:

  • Lamination
  • Drilling
  • Copper plating
  • Etching
  • Surface treatment

Coupon placement also needs to leave enough room for test access, sectioning, or removal from the panel.

For controlled-impedance production, the coupon is typically designed around the same layer pair, dielectric thickness, copper condition, and trace geometry used by the actual impedance-controlled routing.

PCB panel showing test coupons located in the top and bottom panel rails

How Are Impedance Test Coupons Tested with TDR?

An impedance test coupon reproduces the controlled-impedance structure of the production PCB so its characteristic impedance can be measured with time-domain reflectometry, or TDR.

The coupon normally represents the same:

  • Signal layer
  • Reference plane
  • Dielectric thickness
  • Copper thickness
  • Trace width
  • Differential spacing, where applicable
  • Material system

During TDR testing, a fast electrical edge is launched into the coupon. The instrument measures reflections along the transmission line and converts them into an impedance profile.

The result is then compared with the specified target, such as:

  • 50 Ω single-ended
  • 90 Ω differential
  • 100 Ω differential

A typical tolerance may be ±10%, although tighter limits can be specified.

The coupon should be based on the final production stackup rather than only the original CAD trace width. Plating, etching, dielectric thickness, and manufacturing compensation can all change the finished impedance.

PCB impedance test coupon connected to TDR equipment for controlled impedance verification

How Are Test Coupons Used for Microsection and Via Inspection?

Microsection coupons are cut and polished so the internal PCB structure can be inspected directly under magnification.

This method is commonly used to evaluate plated through holes, blind vias, microvias, and multilayer registration.

A typical microsection can reveal:

  • Hole-wall copper thickness
  • Copper distribution
  • Annular ring condition
  • Layer-to-hole registration
  • Resin condition
  • Via interfaces
  • Microvia geometry
  • Lamination quality

Because the coupon is intentionally sacrificed, the production PCB remains intact.

For HDI boards, microsection inspection is especially useful because microvias, stacked structures, and thin dielectric layers can create manufacturing risks that are not visible from the board surface.

Microsection results should be interpreted against the relevant drawing, customer specification, and applicable IPC acceptance requirements rather than treated as a generic pass/fail image.

PCB microsection showing plated through hole microvia copper layers annular ring and resin

Who Should Design PCB Test Coupons—the Designer or the Fabricator?

PCB test coupon design is typically a shared responsibility: the PCB designer defines the electrical and reliability requirements, while the fabricator finalizes the coupon structure for the actual production process.

The customer should provide requirements such as:

  • Target impedance
  • Impedance tolerance
  • Stackup constraints
  • Material requirement
  • Via structure
  • Reliability requirement
  • Required reports or inspection records

The fabricator then knows the actual production details, including dielectric availability, drill size, finished copper thickness, plating allowance, and etching compensation.

For that reason, it is often better for the PCB manufacturer to create or adjust the coupon after the production stackup is confirmed.

If a customer-supplied coupon is included in the fabrication data, it should still be reviewed during DFM to make sure it matches the manufacturing stackup and test method.

Engineer reviewing PCB stackup impedance and test coupon requirements during DFM

What Test Coupon Requirements Should You Include in Your PCB RFQ?

A PCB RFQ should clearly state what needs to be verified rather than simply asking for “test coupons.”

For controlled-impedance or high-reliability projects, provide:

  • Gerber or ODB++ files
  • PCB stackup or stackup constraints
  • Material grade
  • Finished board thickness
  • Copper weight
  • Target impedance
  • Single-ended or differential requirement
  • Impedance tolerance
  • Critical routing layers
  • Via or microvia structure
  • Required test reports
  • Whether physical coupons should be returned

For example, “50 Ω controlled impedance required” is less useful than specifying the routing layer, reference plane, stackup requirement, and tolerance.

FAQ About PCB Test Coupons

1. Is a PCB test coupon part of the finished PCB? No. It is normally placed in the panel rail or another non-product area and removed from the production panel.

2. Do I need to include a test coupon in my Gerber files? Not always. In many projects, the customer provides the test requirement and the PCB manufacturer creates the coupon based on the final production stackup.

3. What is an impedance test coupon? It is a representative transmission-line structure used to measure the finished PCB impedance, commonly with TDR.

4. Can a test coupon prove that every PCB on the panel is good? No. A coupon provides representative process evidence for specific characteristics. It does not replace board-level inspection or electrical testing.

5. Are PCB test coupons normally sent to the customer? They can be. Whether physical coupons, TDR reports, microsection images, or other records are supplied should be defined in the order or quality requirement.

6. What information should I provide for controlled-impedance coupon testing? Provide the target impedance, tolerance, routing layer, reference plane, stackup, material, copper weight, and any special coupon or reporting requirements.

Ready to Review Your PCB Test Coupon Requirements?

PCB test coupons are most useful when they are tied to a specific manufacturing risk, whether that is impedance, plating, microvia quality, registration, or another measurable characteristic. Defining the test requirement before production makes the coupon more representative and the resulting data more useful.

EBest Circuit supports controlled-impedance, HDI, RF, multilayer PCB manufacturing, PCBA, DFM review, TDR testing, and microsection inspection. For projects that require coupon-based verification, send your Gerber files and PCB specifications to sales@bestpcbs.com. Our engineering team can review the stackup, test requirements, and coupon approach before fabrication.

After coupon results are approved, our SMT assembly workflow can also coordinate circuit board stencil requirements with the released fabrication data.

Tags: , , , ,
Posted in best pcb, PCB Design, PCB Technology, Quality | No Comments »

« Older Entries
Newer Entries »