PCB Thermal Spreading Resistance: A Practical Guide

November 14th, 2026

Before adding copper to a hot PCB, measure where the temperature drops. A hot region beside the device and a much cooler region on the same plate suggest a spreading bottleneck. A large drop across the mounting interface points to contact or interface material. If the whole heat sink is hot relative to the incoming air, work on heat rejection first. These problems can coexist, so hold the dissipated power constant while you compare changes.

Power circuit board, copper spreader plate and finned heat sink on a bench — The board, spreader and heat sink can address different parts of one heat path. Illustrative hardware.

Thermal Spreading Resistance: Why the Source Footprint Matters

Thermal spreading resistance is the extra resistance associated with heat flowing from a small source into a larger body instead of travelling straight through a uniform cross-section. Heat near the source must turn sideways to reach more of the plate. The source footprint, its position, the plate thickness and the cooling boundary all affect that flow. A high-conductivity plate can still have a local hot spot.

When a board uses an insulated metal substrate, the component, solder, foil, dielectric and baseplate each influence the path. A large aluminum base does not help as much if heat cannot reach it through the small area where it enters the board. The University of Waterloo spreading-resistance research explains why the source and boundary conditions are part of the result.

Thermal Resistance Calculation Example: Separate the Drops

In a hypothetical steady-state 6 W power-board test, assume most of the heat exits through the base. Readings are 82 °C near the source on the plate, 70 °C on the plate at a specified transfer region, 65 °C on the sink side of that region, and 40 °C in the incoming air. The 12 °C plate gradient is about 2.0 K/W when divided by the total 6 W. It is a diagnostic indicator, not the analytical spreading resistance of the material.

Temperature drops in the same assumed 6 W test
Measured region	Drop	First area to investigate
Near-source plate to transfer region	12 °C	Footprint, plate continuity and spreading geometry.
Across corresponding mounting faces	5 °C	Interface compression, flatness and contact.
Sink base to incoming air	25 °C	Heat-sink size, orientation and airflow.

None of those points is the semiconductor junction. If a second route through the package or PCB carries significant power, dividing by total power does not isolate a segment resistance. Nor should you add lateral and through-interface temperature differences from arbitrary points as if they were all on one series path. Mark the sensor locations in the report.

Heat Spreader vs Heat Sink: Choose the Part That Changes the Right Drop

A spreader distributes heat over a wider area. A heat sink helps release heat to air or another cooling medium. A finned sink can perform both roles at its base, but the mechanisms respond to different changes.

Heat spreader vs heat sink vs mounting correction
Change	Choose it when	Check the trade-off
Improve the spreader	The hot region is concentrated while unused plate area stays cooler.	More metal adds mass and may not improve the component-to-plate entry path.
Improve the heat sink or airflow	The sink is broadly hot relative to incoming air.	Size, orientation, fouling and enclosure pressure loss affect cooling.
Improve contact	A temperature drop concentrates across the mounting joint.	Pad thickness, pressure, isolation and mechanical tolerances must all work together.

PCB Copper Thickness: Check the Continuous Path

Additional copper can improve lateral conduction only where it stays connected to the source and reaches a useful cooling area. A large plane fed through a narrow neck, split by a clearance or reached through poorly coupled layers may offer less benefit than its area suggests. Review the as-built conductor width, copper thickness and dielectric separation together. onsemi AND8432 discusses the influence of uninterrupted spreader area and thickness.

For a powered copper path, IPC-2152 informs conductor sizing for the allowable temperature rise. It does not quantify the device-to-spreader temperature drop. Do not connect extra copper to a switching node merely to gain thermal area; verify the electrical, isolation and EMI consequences.

Thermal Interface Material: Check the Installed Joint

The material’s conductivity is only one variable. Thickness after compression, actual contact area, flatness and local pressure change the mounted result. A thicker pad may bridge a real gap, yet add more through-thickness resistance than a thinner material in a flat joint. Use the specified bond line and do not remove an electrical insulating layer without an approved isolation design.

For the 6 W example, a mounting change is meaningful if the temperature on the source side falls while the heat sink, workload and cooling conditions stay comparable. A cold sink alone is ambiguous: it can indicate effective cooling or a poor path preventing heat from reaching it.

Heat Sink Thermal Resistance: Use the Real Air Boundary

Use the incoming air temperature near the installed sink instead of a distant room measurement. The enclosure may recirculate warm exhaust. Compare installation orientation and airflow with the datasheet condition, and account for nearby heat sources. The apparent sink-to-air value in the example is 25 °C ÷ 6 W, about 4.2 K/W, only under the assumption that essentially all 6 W reaches that sink.

PCB Thermal Simulation: Model the Bottlenecks Explicitly

Start with the real heat-entry footprint, layer geometry, material properties, contact thickness and cooling boundary. A one-dimensional estimate through a uniform layer can give a useful reference, but it does not capture spreading from a small device. Change one input at a time to see whether a thicker spreader, a better interface or stronger convection offers the greatest improvement. Correlate temperatures at multiple locations before using the model to approve a new design.

Keep package metrics separate from board results. The TI thermal metrics guide explains why the quoted junction-to-ambient value depends on the test setup. Use an applicable characterization method when estimating junction temperature.

PCB Thermal Testing: Verify the Change at the Same Power

Circuit board mounted to a plate with thermocouple leads and a thermal camera nearby — Repeat measurements at fixed locations and under the same load. Illustrative bench, not a test record.

Run the baseline and revision to the same steady-state criterion. Record actual component loss, air temperature, mounting torque where specified, and the point and method of each measurement. For infrared readings, account for emissivity and reflections, particularly on bare copper or aluminum. Confirm critical temperatures with suitable independent sensors or the device’s validated temperature proxy.

In the example, approve a spreader change only if it improves the required device or local margin without creating another hot spot or violating electrical constraints. Record the base construction and interface so the result can be reproduced on production hardware. The BestPCBs thermal pad MCPCB guide covers board construction choices for the next design review.

FAQ

Is a copper spreader always better than aluminum?

No. Conductivity helps, but footprint, geometry, mounting and downstream cooling control the overall result.

Is spreading resistance the same as junction-to-ambient resistance?

No. It refers to a local heat-flow mechanism; junction-to-ambient includes the larger assembly and test environment.

Can more thermal vias fix every hotspot?

No. Vias improve a vertical path only when they connect usable spreading layers and a downstream cooling route.

Does a cooler heat sink prove the board runs cooler?

No. It may receive less heat because of poor contact. Compare the source and both interface sides.

Does a larger plate always reduce thermal resistance?

No. Extra area helps only if heat can reach it and leave through a useful cooling boundary.

Can I measure bare copper directly with an infrared camera?

Validate the measurement first. Reflections and low emissivity can make an uncorrected reading misleading.

Can I compare two builds at different power levels?

Use matched power whenever possible. Changing operating point can also change losses, airflow and heat partition.

What should I send for a thermal layout review?

Send the stackup, source footprint and dissipation, contact construction, operating conditions and marked temperature locations.

Discuss Your Metal Core PCB Heat Path

For a Best Technology manufacturing review, send the approved PCB revision, metal base and dielectric requirements, mounting drawing and thermal observations to sales@bestpcbs.com. Identify the temperature drop the board change is intended to reduce.

Tags: MCPCB, PCB Thermal Testing, Thermal Spreading Resistance
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MCPCB Solder Voids: Why the Same 15% Can Differ

November 14th, 2026

Two power assemblies can both show 15% projected solder voiding and still need different decisions. A single void beneath the main heat-transfer area can interrupt a larger share of that local path than several small voids near its edges. First confirm that both images used the same pad boundary. Then compare void location and size, and verify temperature under the same operating conditions. The percentage alone does not prove a thermal pass.

Surface-mounted power package on an aluminum-backed circuit board — The solder joint under the exposed package pad is hidden after assembly. Illustrative bench scene.

Metal Core PCB Stackup: Trace the Heat Path First

On a typical insulated metal substrate, heat flows from the package through its exposed pad and solder, then through the upper conductor and insulating dielectric into the metal base. The base may then transfer heat into a housing through a separate interface. A direct-thermal-path design can bypass the dielectric locally, but it still depends on the solder joint where the component meets the board.

In the motor-controller example below, assume the device is electrically and thermally connected at its exposed pad. Verify that requirement with the device drawing: depending on the part, the pad may be connected to ground, a power node or another specified potential. The metal base must not be treated as that net unless the approved construction makes the connection intentional. The thermal pad MCPCB guide explains those stackup choices.

Exposed Pad Soldering: Separate the Three Interfaces

The exposed package pad is not a soft thermal gap pad, and the solder underneath it is not the board-to-housing interface. A hot device can result from poor solder contact, the board dielectric, or uneven enclosure contact. Changing stencil openings will not fix an uneven heatsink fit. When troubleshooting, record device power and mounting conditions before comparing X-rays from two assemblies.

Use the exact package drawing and the supplier’s attachment guidance to define the required soldered region and net connection. Board copper outside the intended joint does not belong in the void calculation. An edge fillet or a good visual inspection does not establish coverage beneath the package.

Solder Void X Ray: Read the Projection

A top-down 2D X-ray combines attenuation along the beam. The inspection software can outline regions with less solder within a specified joint area. The resulting image is useful for screening, but does not locate a void in depth or prove that the two solder interfaces are fully wetted. Copper, features on the opposite side, and the metal base can change contrast.

Use the same orientation, magnification and segmentation settings when comparing units. Save the unannotated image plus the measured overlay. If bright spots track vias or repeat in features outside the pad, review the board data and image settings before counting them as voids. Document what the image could not separate rather than forcing a percentage for an unreadable region.

Solder Void Percentage: Use the Same Denominator

If the agreed evaluation region covers 20 mm² and the combined projected void area covers 3 mm², the total is 15%. Count overlapping projections only once in that total. It is an area fraction, not a volume fraction, and it cannot simply be multiplied by junction-to-ambient thermal resistance.

For a hypothetical central region of 6 mm², one 3 mm² void entirely inside it would cover 50% of that region. Six voids of 0.5 mm² outside the same region also give 15% overall but 0% inside the defined region. These assumed values show why the denominator and location matter; they are not factory data or acceptance criteria. Define a critical region using the package’s actual heat path or other approved evidence, not an arbitrary center circle.

Projected void percentage vs location in two example units
Finding	Unit A	Unit B
Total projected void area	3 of 20 mm² (15%)	3 of 20 mm² (15%)
Largest single void	3 mm²	0.5 mm²
Overlap with defined heat-transfer region	3 of 6 mm² (50%)	0 of 6 mm² (0%)
Next investigation	Verify central coverage and temperature margin.	Check edge wetting and confirm thermal performance.

QFN Thermal Pad Voiding: Check the Actual Heat-Transfer Area

A large central void may be of greater concern if heat enters the pad mainly there. But an edge void can matter if it overlaps a critical portion of the electrical termination, disrupts solder wetting, or is subject to mechanical loading. The package drawing and thermal evidence, not the image center, determine which region deserves a separate evaluation. The Reliability Study of Bottom Terminated Components examines voiding and heat transfer on specific test assemblies. Its results are not a release limit for the devices in your build.

3D X Ray PCB Inspection: Know When to Escalate

Shielded electronics X-ray inspection equipment next to a sample board — Select the inspection method to resolve the uncertainty. Illustrative equipment scene, not a measured radiograph.

Use an additional angled image if overlap obscures the pad outline or a nearby feature. If the depth of an indication changes the disposition, ask whether computed tomography can resolve it on this stackup; dense metal may limit usable contrast. A targeted destructive cross-section can verify the interface in the chosen plane, but cannot represent the entire joint on its own.

2D X-ray vs CT vs cross-section
Method	Best use	Limit
2D X-ray	Compare projected area and distribution across units.	Overlapping features can mask depth or boundaries.
CT	Separate features through depth when resolution permits.	Metal and acquisition conditions affect visibility.
Cross-section	Inspect wetting, interfaces and thickness in a chosen slice.	Destructive and local, not a full-pad map.

Solder Paste Stencil Design: Test One Change at a Time

Segmented apertures can change how paste deposits coalesce and how gases escape as solder melts. Do not infer the correct paste coverage from the final void percentage: printed paste and reflowed solder are different measurements. Start with the exact package guidance and verify the actual deposits with solder paste inspection before reflow.

When Unit A repeatedly shows a central void, compare the baseline against one proposed aperture layout with the same paste, package lot, profile and fixture. If the void does not respond, investigate wetting or the measured reflow profile rather than reducing paste until the X-ray looks better. Confirm that the change does not create opens or insufficient attachment at other joints. TI SLUA271C explains exposed-pad stencil considerations for QFN and SON.

Thermal Testing: Verify the Margin Before Release

Test representative assemblies at the specified worst-case operating point. Hold power, ambient temperature, heatsink contact, airflow and measurement method constant between samples. Use the package’s characterized temperature proxy or another approved junction-temperature method; the temperature of the aluminum base alone is not a junction measurement. If Unit A shows worse margin, verify the finding across more units before assigning causality. If both pass, still apply all agreed workmanship and electrical requirements.

A release record should include the PCB and stencil revisions, lot, pad evaluation boundary, total and largest void, location rule, image and thermal test record. IPC-7093A covers design and assembly considerations for bottom-termination components. Use the applicable purchase requirements and verified package guidance to define the inspection method and limits; do not adopt a blanket percentage from an unrelated package.

FAQ

Does 15% voiding always pass?

No. It is an example, not a threshold. Apply the written limits and check the measurement method.

Does more paste always reduce voiding?

No. Changing deposit coverage can change gas escape, component seating and other joints. Test a controlled change.

Is a hot QFN proof of poor solder coverage?

No. Check electrical dissipation and board-to-housing contact as well as the hidden joint.

Can a 2D image show where a void sits through the joint thickness?

Not by itself. A suitable additional view, CT or a cross-section can address the specific uncertainty.

Can I skip paste on a difficult center pad?

Only if the package documentation and approved design permit a different attachment. A ground or cooling function may depend on it.

Can I compare images from different inspection programs?

Only after verifying that the boundary, calibration and segmentation are equivalent for that joint.

Is a central void always worse than an edge void?

No. Risk depends on how heat, current and stress pass through the actual joint.

Does passing the thermal test clear an X-ray reject?

No. Treat thermal performance and agreed inspection criteria as separate release gates.

Discuss Your MCPCB Assembly Review

For a Best Technology review, send the package drawing, MCPCB stackup, pad and stencil files, sample X-rays and test conditions to sales@bestpcbs.com. Identify the heat path and the decision the inspection needs to support.

Tags: MCPCB, Solder Voids, X-ray inspection
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Parallel MOSFET Current Sharing: Why One FET Runs Hot

November 14th, 2026

When one of two parallel MOSFETs runs hotter, do not start by adding more copper or changing the gate resistor. First measure the two branch currents during the flat part of the on-time, then compare the switching edges. A mismatch on the plateau points first to the fully enhanced resistance and power paths. A mismatch confined to the edges points first to gate drive, commutation inductance, or device timing. If current and switching losses are similar, look at the two thermal paths instead.

Two power MOSFET packages on a motor-control circuit board — Two power devices can share one electrical switch position without sharing current equally. Illustrative bench photograph.

MOSFETs in Parallel: When It Pays Off

Parallel MOSFETs share the drain and source nodes of one switch. Splitting current across two devices can lower conduction loss and spread heat. It also adds gate charge, layout area, and more opportunities for one branch to take a bigger share. It does not raise the voltage rating. Do not add two datasheet current ratings to obtain a board rating. If you are new to the device, start with this FET fundamentals guide.

Consider a 24 V motor driver that needs 40 A through the energized low-side switch position. One device might meet the requirement with a stronger package or better thermal path. Two devices are justified if the single device cannot meet the loss or temperature budget, and if the layout and driver can support two independently verifiable branches. This example uses assumed values throughout, not test data.

Parallel MOSFET Current Sharing

In the 40 A example, effective branch resistances of 3 and 4 mΩ give 22.9 and 17.1 A, not 20 A each. This is the fully on, fixed-temperature limit. Both branches see the same terminal voltage, so the lower resistance draws more current: I_A = I_total × R_B ÷ (R_A + R_B). Effective resistance includes the device and the separate copper, vias, solder joints and other interconnects between the common split and join points. Shared copper before the split does not enter this simple division.

At a switching edge, that equation is not enough. The first MOSFET to turn on can momentarily carry most of the load, even when the later plateau is nearly balanced. A device that turns off later can take disproportionate turn-off energy. Check the plateau and edges separately rather than judging the current split from a single average value.

Measurements that distinguish the three likely causes of a hot branch
Where the mismatch appears	First thing to check	What would confirm it?
Fully on, after the edge	Hot branch resistance and actual gate-to-source voltage	Separate millivolt measurements show a resistance difference large enough to explain the current split.
Turn-on or turn-off only	Local gate waveform and commutation path	A branch current peak lines up with a repeatable gate or drain waveform difference.
Temperature only	Heat flow into the board or heatsink	Electrical losses are similar, but the hotter device has a less effective thermal path.

MOSFET On Resistance vs Temperature

Use the expected hot R_DS(on) at the actual gate drive, not the headline room-temperature typical value. For the example, suppose the two device contributions are 2.5 and 3.2 mΩ, with the remainder in the respective interconnects. Using the currents above, device-only conduction losses are approximately 1.31 and 0.94 W during the on-state. For steady PWM plateaus, multiply by on-duty fraction as a first estimate; it excludes switching and reverse-conduction losses. The branch that takes 5.8 A more is not necessarily the branch with the worst junction temperature; heat removal still matters.

A fully enhanced silicon MOSFET often has increasing on-resistance with temperature, which helps steady sharing. Verify the curve for the selected part. Do not assume the same stabilizing effect while the device is only partly enhanced, such as during slow startup or linear current limiting. Check the time-dependent safe operating area for those conditions; a low on-resistance does not qualify a device for linear operation.

Parallel MOSFET PCB Layout

Start by tracing the two drain paths from the common node to the packages and the two source paths back to the common return. Match path resistance and inductance, not just trace length. Layer changes, via arrays, plane neckdowns and unequal pad entry can make two equal-length paths electrically different. Where one device is fed through the other device’s connection point, move the split so each receives a comparable path. Keep the gate loop and the high-current commutation loop short and check both.

For heavy copper, note the finished thickness by layer instead of relying on a nominal ounce designation. Check actual copper at narrowed pads and via transitions, and account for the copper that connects the switch to the local bus capacitor. IPC-2152 addresses copper conductor sizing and temperature rise. It does not prescribe a current-sharing tolerance between devices or certify the full assembly. For the 40 A board, compare four-wire branch drops on the sample and verify temperatures with the actual cooling conditions.

Parallel MOSFET Gate Resistor

Place a separate local series gate resistor at each MOSFET. A single resistor ahead of the branch point limits the overall drive, but does not provide the same damping between the individual gate loops. Start with equal, manufacturer-informed values and comparable gate paths. If one branch switches faster, investigate source bounce and layout before trying to cancel it with different resistors.

A larger gate resistor can reduce ringing and overshoot, but slower edges can increase switching loss. On the example board, adjust one design variable at a time and compare overshoot, branch current peaks and switching loss under the same conditions. Fixing the visible ringing alone is not enough if the switch then exceeds its thermal budget at the actual switching frequency.

Kelvin Source MOSFET: When the Sense Pin Helps

A Kelvin source pin gives the driver a separate source reference. In a three-terminal layout, the same source path often carries gate-return current and power current. A rapid change in the latter produces a voltage across the shared inductance, so the effective gate-to-source voltage at the die can differ from what a driver-side trace suggests.

For a package with a dedicated sense source, route the drive return according to the manufacturer’s recommendation. Do not divert load current into that pin. With a three-terminal package, a separate board return to the source pad can remove some shared PCB impedance, but it cannot remove shared inductance inside the package. Compare gate voltage at the device references before and after the layout change.

Parallel MOSFET Gate Driver

The driver must charge and discharge both gates. For two assumed 45 nC devices at 100 kHz, the mean charge drawn for the pair is about 9 mA per switch position. This is a switching-charge estimate, not a peak-drive specification. Select using the actual datasheet gate-charge conditions and account for driver output resistance, the Miller plateau, thermal limits and the required transition time.

Single MOSFET vs parallel MOSFETs vs a power module
Option	When to use it	What it costs or leaves to verify
One larger MOSFET	One package meets the conduction, switching and cooling targets.	Simpler drive and measurement, but heat is concentrated in one package.
Two discrete MOSFETs	There is room for matched branches and cooling, and the driver can handle both gates.	More gate charge and routing. Verify each branch at hot load and during edges.
Power module	A documented module construction fits the current and mechanical envelope.	Higher integration does not remove external bus or cooling limits. Check its terminal and mounting conditions.

Double Pulse Test Setup

A double-pulse test places a controlled load current in the inductive test circuit, then uses the switching events to reveal overshoot, ringing and switching energy. For a parallel pair, total current alone can hide one overloaded branch. Use repeatable, suitable voltage and branch-current sensing, confirm probe bandwidth and timing alignment, and check that the sensor does not add enough impedance to change the split. Follow the instrument and fixture safety requirements; measurements on energized power stages belong in a qualified lab.

Oscilloscope probes on a low-voltage power-switch evaluation board — Probe each branch with the same measurement setup before comparing its switching events. Illustrative bench photograph, not a test record.

For the 40 A design, establish separate acceptance limits before testing: plateau current per device, peak branch current, V_DS and V_GS excursions, loss and junction-temperature margin. Document the bus voltage, temperature, load, device lot, gate settings and probe positions. Compare cold and hot results, then run continuous PWM in the real assembly: a double pulse does not establish sustained thermal performance. Keep the PCB revision, finished copper specification and the test report together. If the heavy-copper stackup changes, recheck the measured branch balance rather than assuming that equal trace widths preserve it.

FAQ

Can MOSFETs in parallel double the current rating?

No. The circuit is limited by the more heavily loaded branch, its switching and temperature, and the board and cooling constraints.

Can two parallel MOSFETs use one gate resistor?

They can switch with a common resistor, but it does not give each gate loop local damping. Start with a resistor per device and verify the waveforms.

Why does one MOSFET run hotter at the same measured DC current?

Compare switching losses, hot on-resistance and the path into the board or heatsink. Equal mean current does not imply equal dissipation or equal temperature.

Does increasing the gate resistance cure drain overshoot?

It may reduce the switching slew rate, but overshoot can also come from the commutation loop or the measurement setup. Verify those first and retest losses after the change.

Does a Kelvin source pin make both branches equal?

No. It reduces common-source feedback in the gate loop; it does not correct differences in power paths or device parameters.

Can a thermal camera prove current is sharing?

No. Use it to locate hot areas, but compare electrical waveforms and account for surface emissivity and thermal paths. Case temperature is not junction temperature.

Can a sample pass a double pulse test and still overheat?

Yes. The test isolates switching events and does not establish continuous operating temperature. Run the assembled board at sustained duty, temperature and cooling conditions.

Can a second-source MOSFET be mixed into a parallel pair?

Only after comparing the exact part’s on-resistance versus temperature, gate charge, threshold spread, switching behavior, package and thermal conditions, then verifying the populated board. Similar headline resistance does not establish compatibility.

References

Discuss a High-Current PCB Layout

For a heavy copper PCB fabrication review with Best Technology, send the board revision, stackup, finished copper requirements, via arrays and the test points used to compare the two branches to sales@bestpcbs.com. Start with the path that must preserve the validated voltage drop or temperature margin.

Tags: Current Sharing, heavy copper pcb, MOSFET Gate Drive, Parallel MOSFETs
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VNA Time Domain Gating Guide for PCB Reflections

November 14th, 2026

Use VNA time domain gating to investigate a PCB reflection only when the response you want to keep is separable from the response you want to suppress. Start with the ungated measurement and a known reference. If the peaks overlap or the answer changes sharply with small gate adjustments, do not use the cleaner trace to release the board.

RF circuit board connected to a vector network analyzer on a laboratory bench — Illustrative RF bench. The reference plane determines which launches are inside the measured path.

VNA time domain gating

A vector network analyzer records complex values across frequency. The time-domain transform reorganizes that data by delay, so an engineer can look for reflections that arrive at different times. A gate then weights a chosen interval of the transformed response. Returning to the frequency domain shows how the adjusted response differs from the original measurement.

Imagine a 50 Ω RF test board with an SMA launch followed by a layer transition. The measured return loss has ripple. The question is whether a separately identifiable launch reflection contributes to it. The gate can help test that hypothesis, but it cannot make the physical launch disappear from an assembly that actually includes it.

S11 measurement using network analyzer

S11 is the reflection measured looking into port 1, with the other port terminated in the specified reference impedance. Measure magnitude and phase, and keep the port direction and termination fixed. A magnitude-only export loses the phase information needed for a conventional time transform.

For the example board, use the same termination and sweep for a known reference coupon and the board under test. If the launch end and far end look interchangeable, mark the connectors physically and keep the port map with the file. The first response is not necessarily the first board feature; it depends on where calibration stops.

VNA calibration

Calibrate at the plane you intend to use. A calibration at a cable end does not automatically remove an adapter or PCB launch added after that plane. Establish whether each item belongs to the test fixture or the product and keep that decision consistent through comparison and reporting.

After calibration, check a known termination or coupon appropriate to the setup. Reconnect it and check that its response stays within the variability your decision allows. If peaks shift when the cable is moved or an adapter is reseated, first resolve that repeatability issue. Smoothing an unstable connection does not improve its underlying measurement.

VNA frequency range

For the illustrative sweep from 2 to 12 GHz, the span is 10 GHz and the reciprocal-span scale is 100 ps. This is a planning scale, not the guaranteed time resolution. The Keysight time-domain guide distinguishes response resolution from distance range and shows the effects of span, window and transform mode.

Setting or parameter	Example	Check before using the gate
Usable frequency span	2–12 GHz; span 10 GHz	Only use bandwidth supported by the fixture and calibration.
Frequency step	10 MHz; 1,001 uniformly spaced points	Check time range and aliasing using the instrument’s transform settings.
Estimated local propagation speed	160 mm/ns, assumed	Obtain a value from the actual line structure or a reference length if localization matters.
Reflection separation	20 mm gives about 250 ps round trip	Verify that the two responses are resolved, not just farther apart than 100 ps.

For two discontinuities along the same line, the extra round trip gives Δt ≈ 2Δx/v. With the same assumed speed, two features 10 mm apart are only about 125 ps apart. If the window broadens each peak or the reflections overlap, neither the displayed cursor precision nor a narrower gate makes those features reliably separable. These are planning calculations, not instrument or BestPCBs specifications.

Time domain windowing

A frequency-domain window changes how each reflection appears in time. Reducing sidelobes generally broadens the main response. This can expose a weak isolated echo that was masked by sidelobes, yet make two nearby features harder to distinguish. Window type therefore belongs in the report alongside the gate settings.

Use the initial transformed plot to place the gate outside the visible response you want to retain, allowing for the response tails. Vary the setting modestly and inspect the resulting frequency response over the actual requirement band. If it moves enough to change the decision, the result is sensitive to processing. Keysight’s gating reference describes how different gate choices retain or reject selected time intervals.

Time domain reflectometry

Use a reflection-versus-time view to locate candidate discontinuities, then use the appropriate calibrated impedance or physical inspection method to confirm them. A VNA bandpass impulse plot is not a direct step-response impedance profile. In this example the sweep begins at 2 GHz, so a low-pass or DC-equivalent interpretation should not be assumed without a separately validated setup.

Coaxial connector attached at the edge of a bare RF circuit board — Illustrative coaxial launch. Correlate its expected delay with the ungated response before attributing any peak to it.

A second echo can be the result of energy bouncing between discontinuities, not a second component at the distance indicated by a simple ruler conversion. Compare a reference coupon and a known geometry change before assigning an unfamiliar peak.

VNA de embedding

Choose a method based on what the test is meant to prove. Time gating can investigate isolated responses at the existing reference plane; validated de-embedding characterizes fixtures and removes their modeled effect so results can be expressed at another plane. One does not automatically substitute for the other.

Approach	When to choose it	Evidence required
Ungated calibrated result	Product includes the launch or connector under test.	Show the full response at the specified plane and termination.
Time-domain gating	Estimate the contribution of a separately resolvable event.	Preserve raw data, gate and window; verify the result is stable when settings vary modestly.
Fixture de-embedding	Report the DUT at an internal plane with a characterized fixture.	Document the fixture and validate the method across the reporting band.

IEEE 370 addresses electrical characterization of PCB interconnects and related structures. The BestPCBs fixture de-embedding guide covers the separate question of removing fixture effects. Do not treat a gated curve alone as evidence of conformity to a de-embedding procedure.

VNA time domain analysis

For the example board, retain both results and annotate the calibrated reference plane, sweep, transform, window, gate limits and DUT orientation. Repeat the experiment after reconnection. If the ungated response fails and only the gated response passes, report both. Unless the acceptance document explicitly permits that gate and excludes the affected structure, use the specified acceptance result and keep the gated curve as diagnostic evidence.

When the launch and transition cannot be separated, do not keep narrowing the gate until the plot looks better. Consider a suitable wider sweep if the calibration and fixture support it, a reference coupon that isolates the launch, or a validated fixture-removal procedure chosen for the actual test boundary.

Frequently asked questions

Does moving a gate move the reference plane?

No. A gate weights time-domain responses. Reference-plane changes need a separate, appropriate calibration or correction.

Does adding points always separate peaks?

No. At a fixed span more points reduce the spacing between acquired frequencies, which can extend the useful time range. They do not add the bandwidth needed for finer response separation.

Can I use a gate after repositioning an SMA cable?

First check a known reference and repeatability. Cable movement may change the raw measurement before any gate is applied.

Is the largest peak always the faulty connector?

No. Check its arrival time and response to an independently verified fixture or geometry change. A strong reflection can also obscure a smaller nearby event.

Can I determine a distance without knowing the propagation speed?

Report the measured delay. To convert it to physical distance, use a justified speed and the correct reflection or transmission path convention.

Can I infer an impedance in ohms from any VNA time plot?

No. An impedance profile requires the correct calibrated response and processing. A bandpass impulse shows events, not a direct impedance value.

Why does the gated frequency response look worse near an edge of the sweep?

Finite bandwidth, transform and gate processing can affect the resulting response, including at band edges. Compare against the ungated data and the instrument’s guidance before reporting those points.

What belongs in a supplier handoff?

Send the coupon drawing, port map, reference plane, sweep file and acceptance rule. Keep the raw and processed traces separately labeled.

Discuss your RF test coupon

For a Best Technology fabrication review, share the coupon geometry, stackup, connector footprint and test boundary with sales@bestpcbs.com. Identify whether the product specification includes the launch.

Tags: PCB Reflections, RF PCB, Time Domain Gating, VNA Measurement
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Group Delay Guide for PCB Filters: When Ripple Is Real

November 14th, 2026

To decide whether group delay ripple comes from a PCB filter, first specify the passband, test boundaries and VNA aperture. Measure a known reference path and repeat the filter sweep under the same conditions. A flat insertion-loss trace alone does not prove that a modulated waveform passes through without distortion.

RF filter evaluation board beside a vector network analyzer — Illustrative RF test bench, not an actual measurement. Define whether the connectors belong to the device under test.

Group delay definition

Group delay describes how fast the transmission phase changes with frequency. In a band where transmission is strong enough and the phase slope is smooth over the signal bandwidth, it describes the delay of a narrowband signal envelope. The qualifier matters: a filter can delay different portions of a wide signal spectrum by different amounts, so a single number cannot describe what happens to the whole waveform.

Consider an illustrative receive-filter board for a radio near 1 GHz. The engineering question is whether the filter and its intended launches add more delay variation than the receiver allows across the occupied band. It is not whether a second PCB route matches the phase of the first route.

Group delay formula

Group delay is minus the derivative of unwrapped transmission phase with respect to angular frequency. In degrees and hertz, estimate it as −Δφ/(360 × Δf) seconds when Δφ is in degrees. This is a finite-interval estimate, not a guarantee that the slope remains constant between the two points.

For an instructional example, suppose unwrapped S21 phase changes from −82° at 995 MHz to −91° at 1,005 MHz. The difference is −9° over 10 MHz, giving +2.50 ns. If the instrument shows a phase jump at its display wrap boundary, do not use that displayed jump as the physical phase difference. See Keysight’s VNA group delay procedure.

Group delay vs phase delay

Use group delay to judge slope and waveform timing across frequency. Use phase delay only when the absolute phase and its reference convention are defined; a wrapped angle at one tone does not establish an unambiguous delay.

Metric	Evidence and conditions	Use it when
Phase delay	Negative phase divided by angular frequency, with a defined phase branch and reference plane.	You need the equivalent delay of an individual sinusoid under that convention.
Group delay	Negative phase slope, with stated frequency interval, reference plane and usable transmission.	You need envelope transit time or in-band delay variation.
Insertion loss	Transmission magnitude at the same reference planes and terminations.	You need amplitude loss or want to flag low-signal regions where phase becomes unreliable.

Group delay in filters

A filter can meet its amplitude mask and still delay parts of a waveform unequally. Inside the occupied band, variation in phase slope can smear a fast pulse or change the shape of a modulated symbol. Compare the delay curve with the system signal bandwidth instead of averaging over the entire instrument sweep.

For the receive board, check the occupied band with its allowed frequency offsets. A steep delay change outside that window may matter to a different operating mode, but it does not automatically fail the present mode. Conversely, do not arbitrarily trim an in-band peak simply to make the report pass.

Group delay ripple

Peak-to-peak group delay ripple is the maximum minus the minimum delay over the declared band, using the declared measurement setup. On the illustrative board, 2.80 ns maximum and 2.35 ns minimum give 0.45 ns peak to peak. If the project allows 0.40 ns maximum, that sweep exceeds the limit by 0.05 ns. It is not a confirmed defect until the measurement is suitable for separating that margin from setup variation.

Test entry	Example only	Reason to retain it
Acceptance window	990–1,010 MHz	Prevents a different sweep or stopband feature from changing the result.
Peak-to-peak limit	0.40 ns	States the actual release metric; an average is not a substitute.
Aperture and point spacing	2 MHz aperture; 0.25 MHz uniform points	Allows repeat sweeps with the same effective differentiation interval.
Decision conditions	Named reference planes, stable connections, reference sweep and repeat data	Helps judge whether a small apparent failure can be resolved.

VNA group delay measurement

Use a calibrated two-port transmission measurement and define whether connectors and launches belong to the DUT. Start with a known thru or reference coupon rated for the test band. It need not show zero delay; the concern is whether it exhibits unexpected ripple or changes on reconnection.

Keep the cables stable, use the same port power and terminations, and retain complex S21 plus the setup file. If the specification excludes the fixture, use a validated correction for its actual geometry; a simple electrical-delay adjustment is not a substitute for removing mismatch and fixture effects. The PCB fixture de-embedding guide covers how to define that boundary.

Group delay aperture

Aperture is the frequency separation over which the analyzer estimates the phase slope. A larger aperture smooths the curve but can hide a narrow feature; a smaller one resolves finer detail but can make phase noise more obvious. Do not confuse aperture with the spacing between acquired points. The instrument may express aperture as points, hertz or a percentage of span.

Coaxial cables connected to an RF test board on a bench — Illustrative test connection and screen display, not measured data. Keep the cable arrangement and reference planes fixed when comparing aperture settings.

As a diagnostic check, repeat the sweep with two supported aperture settings while keeping the acquisition band and calibration fixed. A sharp spike that moves with settings or follows a noise floor calls for better measurement evidence. A repeatable feature may still shrink under heavier smoothing, so use the prescribed aperture for the acceptance result. Save both traces. Keysight’s aperture note also explains why edge points can disappear for wider intervals.

Group delay dispersion

Before attributing delay variation to the board, check whether the shape persists inside the usable passband, after reconnecting the DUT, and on another representative board if the decision warrants it. Compare the trace with insertion loss and return loss: a feature near a deep transmission null can have unstable phase and should not be used as evidence of passband behavior.

For the example, record the raw S-parameters, selected band, aperture, calibration or fixture file, curve extrema and location of the highest variation. If the reference is stable and the DUT exceeds the fixed limit in repeat tests with sufficient measurement margin, hold disposition for design review. If the reference shows similar variation, resolve the measurement problem before changing the PCB.

Frequently asked questions

Why does the trace drop out at the sweep ends?

The slope calculation may need points on both sides of the reported frequency. Sweep beyond the acceptance band so there are adequate points on either side, while retaining the actual window in the report.

Does flat group delay have to be zero?

No. A uniform delay can shift the arrival time without spreading the envelope. Check any separate latency requirement before deciding that a large constant offset is acceptable.

Can an S21 magnitude-only export be used?

No. It lacks the phase needed for the slope. Export complex S21, with frequency and port information, when the analysis will be repeated off the instrument.

Does more point density always cure phase wrapping?

It can help if large phase steps caused the ambiguity, but extra points do not improve a noisy transmission null. Verify both the spacing and the usable signal level.

Why does reconnecting an adapter change the result?

It can change the effective reference path or introduce a mismatch that was not accounted for by calibration. Record the adapter and verify a reference sweep after the connection change.

Can a negative value alone prove a faulty RF filter?

No. First check the reference convention, transmission level and phase processing. In a strongly dispersive region the phase slope can also yield an apparent negative delay without representing a signal traveling backward in time.

Does a TDR impedance check replace the group delay sweep?

No. TDR can locate impedance discontinuities, while a group delay sweep verifies transmission phase slope over the specified band. Use the two checks for different questions.

What goes in the production handoff?

Send the test boundaries, passband, limit, aperture, point spacing, fixture revision and report format. Link each result to its board revision and test state.

Discuss your RF PCB requirements

For a Best Technology fabrication review, send the stackup, RF launch or coupon geometry, and the intended measurement reference planes to sales@bestpcbs.com. Identify which connector and fixture structures the design includes.

Tags: Group Delay, RF Filters, RF PCB, VNA Measurement
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Ceramic PCB Copper Peel Strength: Can You Compare Two Reports?

November 14th, 2026

Do not approve a ceramic PCB lot from a peel-strength number alone. First match the specimen construction, peel angle, speed, conditioning and reporting interval. Then check where the specimen failed. A copper strip that tears and a strip that separates cleanly at the ceramic interface do not establish the same result.

Suppose two suppliers submit reports for a power-module substrate. One lists 18 N for a 4 mm strip; the other lists 20 N for a 5 mm strip. The second asks you to approve its lot because its force is higher. Before deciding, normalize the force and check whether the tests were equivalent. All example numbers below are hypothetical.

Copper strip above a flat ceramic coupon in a laboratory fixture — Illustrative test setup. Verify which angle the fixture maintains during the evaluated travel.

Copper Peel Strength: What the Number Means

Peel strength is force per unit width under a defined peeling procedure, commonly reported in N/mm. The instrument pulls a prepared strip while the fixture controls its orientation. The recorded force can include bending or deformation of the copper as well as separation from the underlying structure. It is not a material constant or an allowable design load.

Define what the purchase drawing requires. A minimum sustained peel result at a named condition is not interchangeable with the maximum force reached while starting the strip. Ask for the trace or calculation interval when the report gives only one rounded result.

Peel Strength Test Method: Match These Inputs

Before comparing reports, make sure they describe equivalent specimens and the same test. The manufacturing route, ceramic grade and copper thickness all matter when the result is used for incoming acceptance.

Report field	What you need to check
Substrate and copper construction	Exact grade, bonding route, copper thickness and tested face
Peel geometry and speed	Actual angle, fixture arrangement and specified test speed
Specimen geometry	Measured strip width, preparation and position on the coupon
Condition and reported result	Temperature or conditioning, measured interval, statistic and failure location

90 vs. 180 Degree Peel Test: Compare the Geometry

At 90 degrees the peeled strip is drawn approximately perpendicular to the substrate face. At 180 degrees it is folded back along the plane in the opposite direction. The geometries load and bend the strip differently. Use the configuration named by the purchase specification or approved test plan; do not convert one result into the other with a fixed multiplier.

Method	When to select it	What to verify
90-degree peel	The production acceptance plan calls for perpendicular peeling.	The fixture maintains angle through the evaluated travel.
180-degree peel	The approved procedure calls for back-fold peeling and the strip can be prepared accordingly.	The strip does not fail prematurely during preparation or bending.

If neither method can produce a representative strip, ask for an approved alternative assessment and define a separate acceptance criterion. Do not reuse a peel limit for a different loading mode.

Peel Strength Calculation: Normalize Before Comparing

Divide the specified force statistic by the actual strip width. If the two hypothetical reports use the mean over the agreed interval, 18 N divided by 4 mm gives 4.5 N/mm, while 20 N divided by 5 mm gives 4.0 N/mm. The apparent ranking reverses after normalization.

That arithmetic still does not resolve the purchasing decision. If one report used a peak and the other used an average, or their peel angles differ, ask for a matched test. A normalized unit makes the comparison possible only after the method and specimen have been matched.

Peel Test Failure Modes: Inspect the Separated Surfaces

Record whether separation followed the bond, whether ceramic fractured or whether the copper strip tore. Retain photos of both sides with the specimen identifier and correlate the event with the force trace. A change in the trace is a reason to inspect; it does not identify the failure plane by itself.

If the strip tears before the specified interval is complete, do not enter its tear load as a normal bond-strength result. Apply the method’s invalid-test or alternative-reporting rule. If the procedure leaves the treatment unclear, retain the data and agree on a retest before release.

Separated ceramic coupon pieces and copper on an inspection bench — Illustrative specimens. In an actual report, retain images of both fracture faces and the specimen identifier.

DBC vs. AMB: Read the Datasheet Conditions

Rogers curamik technical data sheet 135-004, version 1.19 JP, page 2, lists at least 4.0 N/mm at 50 mm/min for its DBC construction with 0.3 mm copper and at least 10.0 N/mm at the same speed for its AMB construction with 0.5 mm copper. These are supplier-stated results for different constructions, not a controlled experiment isolating the bonding process or universal acceptance limits. See the curamik data sheet, “Copper peeling strength”.

For the power module, compare offers against the same assembly requirements rather than ranking bonding routes by their datasheet numbers. Request evidence for the exact build you would buy.

Thermal Cycling Test: Keep Conditioned Results Separate

An as-received peel result can support an incoming check. It does not establish adhesion after repeated temperature changes or prove the reliability of the assembled module. If conditioning is required, document the profile, number of cycles, specimen state, and acceptance method before the test.

Use matched specimens for the baseline and conditioned checks. Peel testing damages the specimen, so do not describe a before-and-after comparison as repeated measurements on the same already-peeled strip. If the failure location changes after conditioning, report that as well as the force.

Peel Strength Test Report: Decide Whether to Release

First verify that the report applies to the received lot and agreed construction. Then verify the method and calculate the specified result. Release only when the required measurements and failure reporting meet the approved criteria. If the suppliers used different methods, request a matched retest rather than applying an unverified conversion.

The Best Technology DBC yellowing test report is an example of reporting individual peel-force statistics and normalized strength. Its conclusion applies to the specimens in that report, not every discolored ceramic substrate.

Frequently Asked Questions

Is 4 N/mm a universal DBC minimum?

No. Use the limit and test procedure agreed for the actual construction.

Does a higher peak mean a stronger interface?

Not necessarily. The peak may reflect initiation or deformation. Compare the same defined interval and statistic.

Can 90-degree and 180-degree results be averaged?

No. They are different configurations. Report them separately unless a qualified procedure establishes equivalence for the specific application.

Why record copper thickness if the result is already in N/mm?

Dividing by width does not remove thickness-dependent bending or deformation.

What if I cannot peel the thin copper without breaking it?

Document that outcome and agree on a more suitable test and its acceptance criterion. Do not treat the tear load as a direct adhesion result.

Does a good peel result prove a ceramic card will pass insulation testing?

No. Use the agreed electrical test for the insulation requirement.

Can I apply an as-received report after thermal cycling?

No. Request the relevant conditioned evidence if it is required by the qualification plan.

What evidence helps resolve a supplier disagreement?

Send the approved drawing, lot identity, raw force traces, specimen dimensions, fixture details and photos of the failure surfaces.

References

EP4310065A1: ceramic composite substrate, example of perpendicular peel geometry. This is a documented test example, not a universally applicable acceptance standard.

Discuss Your Ceramic Substrate Acceptance Plan

Send the ceramic grade, copper construction, drawing and proposed test method to sales@bestpcbs.com for a Best Technology review. Identify whether the decision concerns a new material qualification or the release of a received lot.

Tags: AMB Substrate, ceramic PCB, Copper Peel Strength, dbc substrate
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Laser Flash Analysis: Can You Trust the Ceramic PCB Report?

November 13th, 2026

A laser flash analysis report for a ceramic PCB material should identify the specimen and show three compatible inputs: thermal diffusivity, density and specific heat capacity. If the report provides only a conductivity number, ask how it was obtained before using it to approve a material change. A bare ceramic coupon does not represent the thermal resistance of the finished power assembly.

Consider a hypothetical power module whose supplier proposes a new alumina substrate. The incoming report lists 36 W/(m·K), and the design team needs to know whether that value is comparable to the existing material. This example follows the decision from the raw report through assembly verification. None of the example values is a Best Technology production limit.

Ceramic test coupons beside a laboratory thermal analyzer — Illustrative lab setting. Establish whether the report tested bare ceramic, metallized material or a different construction.

Laser Flash Analysis: What the Instrument Measures

A short light pulse heats one face of a suitable specimen. The instrument tracks the temperature rise on the opposite face and uses the shape of that response and specimen thickness to infer thermal diffusivity. For a conventional plane-parallel sample measured through its thickness, the result describes that direction. Ask the lab to identify the measurement direction rather than assuming it is in-plane.

Ask for the specimen description and fit method. Heat loss, pulse duration and optical behavior may affect the transient, so a report that says only “laser flash” gives too little context for comparing close results.

Thermal Diffusivity vs. Thermal Conductivity

Thermal diffusivity describes how fast a temperature disturbance spreads. Thermal conductivity describes the heat flow a material supports for a given temperature gradient. Materials can store different amounts of heat per unit volume, so they need not rank the same way on the two metrics.

For the module, use conductivity for a first steady-state heat-path estimate. Keep the measured diffusivity and related properties when evaluating the time response. Do not compare a supplier’s number in mm²/s with another supplier’s number in W/(m·K).

Thermal Diffusivity Units: Check Each Input Before Comparing Reports

To calculate conductivity in W/(m·K) with SI inputs, convert mm²/s to m²/s by multiplying by 10⁻⁶. Convert g/cm³ to kg/m³ by multiplying by 1,000. If specific heat is given in J/(g·K), multiply by 1,000 to obtain J/(kg·K). Keep the original units visible next to each converted value.

Input	Example for one ceramic	What to verify
Diffusivity, α	12 mm²/s = 0.000012 m²/s	Direction and temperature of the test
Density, ρ	3.8 g/cm³ = 3,800 kg/m³	Same material construction and appropriate temperature basis
Specific heat, c_p	0.780 J/(g·K) = 780 J/(kg·K)	Measured or sourced value for the same material and temperature

Thermal Diffusivity Formula: Recalculate the Reported Conductivity

Rearrange α = k/(ρc_p) to get k = αρc_p. In the example, 0.000012 × 3,800 × 780 gives 35.568 W/(m·K), consistent with a rounded result of 36 W/(m·K). This verifies the arithmetic only. It does not validate the test or prove the result is a guaranteed minimum.

If the report cannot be reproduced, ask for the exact inputs, units, temperatures and whether the output describes a homogeneous material or an effective multilayer result. Do not reconcile a mismatch by silently inserting a datasheet value.

Ceramic coupon and micrometer on a materials test bench — Illustrative metrology. Record the measured thickness and any surface treatment before interpreting the transient.

Specific Heat Capacity: Ask Where the Value Came From

Specific heat is the energy needed per unit mass and temperature rise. A lab can use a comparative method to estimate it or use documented material data when appropriate. The source matters: conductivity changes in direct proportion to c_p when the other inputs stay fixed. In the example, a 5% higher assumed c_p gives a 5% higher calculated conductivity.

Request separate provenance for density and specific heat. A literature value for a nominal composition is not automatically a value for the received grade, porosity or operating temperature. If the comparison margin is small, request a matched retest or a defensible uncertainty estimate.

Thermal Conductivity Measurement Methods: Bare Coupon vs. Finished Stack

Use a bare specimen test to qualify ceramic material. A metallized stack or bonded coupon may require a multilayer model, particularly when an interface affects the response. It should not be reduced to a bulk ceramic value by inserting the total thickness into a single-layer calculation.

Specimen	Useful decision	Limit
Unmetallized ceramic	Compare material lots or grades under matched conditions.	Does not include copper or bond interfaces.
Metallized coupon	Compare a controlled stack using an appropriate model.	Does not reproduce the mounted module.
Production assembly	Verify junction or other defined temperature limits under actual mounting and load.	Does not isolate bulk material conductivity by itself.

Alumina vs. Aluminum Nitride Thermal Conductivity: Compare the Actual Grades

When comparing alumina and aluminum nitride, match specimen direction, temperature and reporting method. Compare exact grades rather than generic material names. A material with higher conductivity is worth evaluating if the ceramic accounts for a meaningful part of the heat path, but the assembly may still be limited by a bond, interface or cooler.

For the module, review dielectric isolation, metallization compatibility and mechanical requirements alongside thermal data before approving a substitution. Use a material report to screen candidates, not to qualify every feature of a different construction.

Thermal Resistance Calculation: Set a Separate Assembly Check

For ideal one-dimensional conduction, estimate the slab’s resistance as thickness divided by conductivity times area. At 0.63 mm thickness, 100 mm² area and 35.568 W/(m·K), that gives about 0.18 K/W for the ceramic slab. It excludes spreading, metallization, joints and cooling. The estimate is useful for scale, not as a prediction of junction temperature.

Release the material against the agreed lot-level requirement and the assembly against its own thermal target. Record operating power, measurement endpoints, boundary conditions and method. The Best Technology assembly thermal test guide shows why a change at the mounting interface can alter the measured temperature independently of the substrate.

Frequently Asked Questions

Does laser flash analysis directly measure conductivity?

It typically determines diffusivity from the transient. Conductivity can be derived using compatible density and specific heat.

Can I compare values at two different temperatures?

Do not treat them as equivalent without a justified temperature comparison or a matched test.

Is a graphite coating part of the ceramic’s conductivity?

It may be a specimen preparation aid. Ask the lab to document the coating and account for its influence where relevant.

Does a higher conductivity guarantee a cooler component?

No. Check the complete heat path and mounting conditions.

What if the two suppliers use different specimens?

Use the figures for preliminary screening only until the material construction and test conditions can be aligned.

Can the number prove electrical isolation?

No. Use the specified dielectric or insulation test for that requirement.

Why request the thickness used in the fit?

It is an input to deriving diffusivity. Nominal stock thickness may not represent the measured specimen.

Should I accept a report with no raw values?

If it controls a material release, ask for the input values and evidence needed to apply the agreed decision rule.

References

Discuss Your Ceramic PCB Requirements

Send the ceramic grade, copper construction, thermal report and planned acceptance test to sales@bestpcbs.com for a Best Technology review. Mark which values are purchasing requirements and which are design inputs.

Tags: ceramic PCB, Laser Flash Analysis, thermal conductivity, Thermal Diffusivity
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SPDR Test Guide: Can You Compare Two PCB Laminate Reports?

November 13th, 2026

Before comparing two split-post dielectric resonator (SPDR) reports, match the method, frequency, specimen construction and conditioning. Then check the uncertainty. A small difference in dielectric constant can disappear once the laboratory accounts for specimen thickness. And even a valid material comparison does not predict the complete insertion loss of a finished RF board.

Consider a hypothetical RF filter board. Two suppliers report Dk values of 3.50 and 3.54 for proposed laminates. One lab used a different fixture frequency. The immediate decision is not which number is closer to the layout model. It is whether the two numbers answer the same question and whether the difference is larger than the measurement can resolve.

Illustrative shielded resonator fixture with a dielectric sheet — Illustrative resonator setup. The tested specimen is an unclad sheet, not a completed filter board.

Split Post Dielectric Resonator: What the Fixture Measures

An SPDR fixture has dielectric posts separated by a gap for a sheet specimen. A vector network analyzer observes the resonance of the empty fixture and then the resonance with the specimen installed. The fixture model uses the frequency shift and measured sheet thickness to estimate relative permittivity, and the resonance quality factor to infer loss tangent. The electric field is primarily parallel to the sheet, so check the reported orientation before using the value for a through-thickness model.

A fixture measures around its chosen resonance, not across every frequency that the VNA can sweep. For a frequency-dependent comparison, request the relevant fixtures and measurement points rather than extrapolating from one number.

Dielectric Constant Measurement: Check the Specimen First

IPC-TM-650 2.5.5.15 covers nominal fixtures from 1 to 20 GHz. As one example, its 10 GHz case uses an 80 × 80 mm specimen no thicker than 0.9 mm. The method calls for at least 24 hours of conditioning after etching at 23 ± 2 °C and 50 ± 5% relative humidity. These requirements describe the cited method, not every resonator or every supplier’s product limits.

Report item	Decision it supports
Grade, lot and specimen construction	Verify that the sample represents the material being offered.
Measured thickness and specimen stacking	Compare the actual input to the extraction, not a catalog nominal value.
Fixture frequency, orientation and conditioning	Identify differences that prevent a direct comparison.
Individual results and uncertainty	Determine whether the observed difference is resolvable.

Resonant Frequency Measurement: Start With the Empty Fixture

The empty and loaded frequencies must correspond to the same intended resonant mode. A material with relative permittivity above one generally shifts that mode down. The amount of shift also depends on sheet thickness and how strongly the field interacts with the specimen. A thicker sheet can shift the frequency farther even when its Dk is unchanged.

Ask for the empty and loaded resonance values and the thickness used in the calculation. If one report records only the loaded peak, ask the lab for the missing baseline and fixture identification before interpreting a difference between suppliers.

Quality Factor Measurement: Do Not Treat the Full Change as Material Loss

A higher Q means that the resonance stores more energy relative to the energy lost per cycle. The measured response includes losses in the fixture as well as in the specimen. Use the fixture method to estimate unloaded Q and account for the fixture’s contribution; simply subtracting two displayed Q values is not a loss-tangent calculation.

At very low Df, the sample-induced change can be small relative to setup drift or fit variability. Ask for repeat readings or a suitable reference specimen if a purchasing decision depends on the last displayed digit.

Thickness measurement setup with unclad dielectric coupons — Illustrative specimen handling. Record the thickness used for extraction and how it was measured.

Loss Tangent Measurement: Identify the Boundary of the Result

Df is the dielectric loss tangent, a dimensionless material result at the reported test condition. A low Df can help a design meet its loss budget, but it does not remove losses from copper roughness, conductor resistance, launches or radiation. The unclad SPDR sample intentionally does not reproduce those effects.

For the filter board, use the material test to compare equivalent specimens and a representative routed coupon to check the manufactured line. If the material results agree but the routed loss differs, check the copper profile, actual line geometry and launch reference planes before rejecting the laminate.

Dielectric Constant Measurement Methods: SPDR vs. a Routed Coupon

Choose the method by the decision. SPDR is useful for comparing incoming dielectric material at a nominated frequency. A routed coupon is useful when the question is whether a real stackup and conductor geometry give the intended phase or loss.

Test	Use it for	Do not infer
SPDR on an unclad sheet	Relative permittivity and dielectric loss at the reported resonance	Finished board insertion loss or broadband Dk from one point
VNA measurement of a routed line	Phase and transmission for the measured stackup and reference planes	Pure dielectric loss without separating other contributions

The Best Technology fixture de-embedding guide explains how to keep the measurement planes consistent for the routed coupon.

Dielectric Constant of PCB Materials: Check Whether the Difference Is Resolvable

In an illustrative application of the thickness term in IPC 2.5.5.15 §7.2, take a 0.400 mm specimen with thickness uncertainty of ±0.003 mm. The relative estimate is ±(0.0015 + 0.003/0.400) = ±0.009, or ±0.9%. At Dk 3.50 that is about ±0.032. This illustrates sensitivity to thickness; it is not a complete laboratory uncertainty budget or a factory tolerance.

If both hypothetical reports have about that scale of uncertainty, the intervals for 3.50 and 3.54 overlap. That does not prove the materials are identical. It means the figures alone do not establish a clear difference. First bring both specimens to the same method and frequency, then ask for repeatability and a documented comparison.

Dielectric Constant Test Method: Turn the Report Into a Release Decision

Before placing the order, specify the grade, lot documentation, test method, target frequency, specimen condition and the acceptance rule. Do not turn a datasheet typical into a contractual minimum or maximum without agreement. If the lab cannot reproduce the named test, decide whether an approved equivalent method or a matched retest is needed before comparing results.

For the example board, release the material only against the agreed material criterion. Release the design separately when the representative RF structure meets its specified phase and loss over the operating band. Save the raw curves and reference-plane description so a later laminate or stackup change can be tested on the same basis.

Frequently Asked Questions

Can I test a copper-clad sheet directly in the SPDR fixture?

Use the specimen specified by the method; the IPC base-material method uses the dielectric without metal cladding. A completed board is a different test specimen.

Can one fixture measure Dk continuously from 1 to 20 GHz?

No. That range describes the method’s supported fixtures. Each result belongs to the relevant resonance and fixture.

Why do the two reports give different Dk numbers?

Check frequency, conditioning, specimen construction, orientation and thickness before assuming the materials differ.

Does a lower Df guarantee a lower-loss PCB?

No. The conductor, launch and geometry also affect loss. Verify the finished construction with a suitable coupon.

Should I enter the SPDR number directly into a field solver?

Check the solver’s material model, direction and frequency first. Correlate with a representative structure when accuracy matters.

Can the lab stack thin samples?

The IPC method describes stacking thin specimens under its conditions. Ask the lab to record the stack and measured thickness.

Is more precision in the printed Df enough to rank suppliers?

No. More digits do not establish lower uncertainty. Ask for repeatability and conditions comparable across both reports.

What should I send if a filter prototype misses its target?

Send the laminate reports, actual stackup, conductor dimensions, raw S-parameters and calibration planes. These help distinguish a material mismatch from a board or test issue.

References

Discuss Your RF PCB Stackup

For a Best Technology stackup review, send the operating band, laminate report, proposed geometry and acceptance plan to sales@bestpcbs.com. Mark whether your unresolved question concerns the dielectric material or the finished RF channel.

Tags: Dielectric Constant, PCB laminate, RF PCB, SPDR
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LED Thermal Transient Test: Is the Aluminum PCB at Fault?

November 13th, 2026

If an LED runs too hot on an aluminum PCB, change the board-to-heatsink interface while keeping the board, LED, and test power the same. Compare the junction-temperature response. If the response changes, the interface is a useful place to investigate before ordering a different substrate. If it does not, first check test sensitivity and repeatability; two matching curves do not prove the board is at fault.

Consider a hypothetical industrial inspection lamp: a new aluminum-core PCB and LED meet the electrical requirements, but the estimated junction temperature exceeds the design target in the closed housing. The team must decide whether to improve the board or correct its contact with the heatsink. A controlled thermal transient test can narrow that decision without treating the heatsink temperature as the junction temperature.

Round aluminum-core LED board on a finned black heatsink — An aluminum-core LED board and heatsink. Illustrative setup, not a measured sample.

Thermal Transient Testing: Start With the Heat Path

A thermal transient is the temperature change after heating power changes. In this lamp, heat flows mainly from the LED junction through the package and solder joint, then through the board, interface material and heatsink. Some heat also leaves by other paths. Measuring how the junction cools after power is reduced gives more information than a single final temperature.

Draw the suspected main path before testing. Mark where the junction temperature is inferred, where a thermocouple can go, and which interface can be changed without disturbing the rest. If the module has several powered LEDs, hold their operating states fixed or measure them separately. Neighbor heating can otherwise look like a change in the board under test.

LED Junction Temperature Measurement: Choose the Right Reference

Use a calibrated forward-voltage method when you need the junction cooling curve. Establish the relationship between forward voltage and temperature at a low sensing current for the device or qualified sample group. After the heating phase, switch to the sensing current and record voltage versus time. Log the switching delay: the earliest part of a fast transient can be obscured by electrical settling.

A thermocouple at the manufacturer-defined solder point serves a different purpose. It can support a steady-state junction estimate using the exact datasheet thermal parameter and power convention. It does not capture the fast junction transient. A temperature taken on the shiny aluminum back or heat sink is farther away and cannot be substituted for the specified point. For probe placement, see the Cree LED solder-point temperature note.

LED Thermal Resistance: Check the Endpoints and Power Basis

Thermal resistance in K/W is a temperature difference divided by the power used by the stated method. The endpoints matter: junction-to-solder-point is not junction-to-ambient. For heat-flow calculations, heat from the LED is electrical input minus emitted optical power. Some manufacturer data instead uses an electrical-input convention; pair the power term with the definition in the same datasheet or test report.

Report field	What to check	Why it matters
Temperature endpoints	Junction, solder point, case or ambient	Different endpoints include different parts of the heat path.
Power basis	Electrical input or heat after accounting for light	The denominator must match the thermal resistance convention.
Mounting and boundary conditions	Board construction, interface, clamping, airflow	Assembly values do not transfer unchanged to another fixture.
Acquisition and repeatability	Sense current, delay, thermal baseline, run-to-run spread	Small differences can be measurement artifacts.

Thermal Resistance vs. Thermal Impedance

Use steady thermal resistance for an equilibrium temperature rise at fixed power and boundary conditions. Use transient thermal impedance, Z_th(t), for the time-dependent response to a defined heating step. For an appropriate linear approximation, the rise after a heat step is the step power multiplied by Z_th(t). The curve approaches the steady resistance if the same thermal endpoints and conditions apply.

That distinction changes the test. A long continuous run checks the lamp’s final temperature in its enclosure. A pulse may end before the full assembly warms; using only average power can hide junction peaks. Conversely, a single-pulse curve starting cold does not represent repetitive pulses starting from a warm baseline. Validate the actual waveform and operating state.

Transient Thermal Impedance Curve: What a Split Can Tell You

Run the same LED board twice with two controlled interface conditions. Keep the heatsink, power, sensor calibration and ambient fixed; document each mount. Compare repeat runs before comparing the two conditions. If early responses agree within repeatability but later responses differ, the changed boundary affected the later response. This supports investigating the interface or related heat path. It does not make every bend in a curve the location of a named layer.

In a hypothetical steady-state comparison, both runs dissipate 4.0 W of LED heat. With the existing mount the late impedance approaches 3.0 K/W; with the comparison mount it approaches 2.5 K/W. The difference is 0.5 K/W, equivalent to a 2 °C steady junction-rise difference at the same heat load. If repeat runs vary by roughly that much, the experiment cannot separate the mounts confidently. These are illustrative values, not a measurement or a product limit.

Two aluminum-core LED boards with samples of thermal interface pads — For a mount comparison, document the interface material, its installed thickness and the clamp condition. Illustrative components.

Thermal Interface Material: Change One Thing at a Time

Compare a production mount with a controlled reference mount on the same board first. Differences in compressed thickness, wetting, flatness and clamp load can outweigh a catalog conductivity figure. Do not treat a grease reference as a drop-in production substitute: the design may require electrical isolation, gap accommodation, or mechanical retention that the reference cannot provide.

Controlled comparison	Signal to look for	Next decision
Same board, different interface	Repeatable change larger than remounting spread	Investigate interface, clamp and flatness before changing the PCB.
Same interface and package, two board constructions	Consistent difference after controlling the solder attach and mount	Review dielectric thickness, construction and spreading before attributing the difference to the metal core.
Same assembly, different airflow	Late response changes with airflow	Check enclosure cooling and repeat in the intended operating orientation.

For the mechanical checks that precede this comparison, see the aluminum PCB enclosure and thermal pad gap guide.

Transient Thermal Impedance Measurement: Know the Limits of Layer Attribution

Use a qualified transient dual-interface method when the goal is a package-level thermal resistance. The method uses a controlled change at an interface and evaluates where two responses separate, under its specified assumptions. A structure function represents the distributed thermal response; it is not a cross-section image. Parallel heat paths, calibration errors and noisy early data can undermine a one-layer-per-feature interpretation.

For the lamp, a practical mount A/B test supports a redesign decision, but it is not automatically a JESD51-14 package characterization. If the interface comparison is inconclusive, keep it fixed and compare a second board construction with the same LED and documented solder attach. If that change is inconclusive too, check the baseline, power normalization and whether the instrument resolves the temperature difference you need to see.

LED Maximum Junction Temperature: Set the Release Limit Before Testing

Start from the exact LED’s datasheet and the product’s lifetime and optical requirements. An absolute maximum is not a normal target. Agree on an operating ceiling that leaves margin for ambient variation, assembly spread and measurement uncertainty. Then define the duty cycle, orientation, enclosure, warm-up condition and worst-case neighboring heat load for the acceptance run.

For example, if the lamp’s engineering ceiling is a hypothetical 95 °C and the corrected build estimates 94 °C with ±3 °C measurement uncertainty, the result cannot demonstrate compliance with a conservative upper-bound rule. Improve the thermal margin or the measurement before release. Repeat on production-representative assemblies and record the actual stackup, interface condition and acceptance calculation.

Frequently Asked Questions

Does a cool heatsink mean the LED is safe?

No. A high resistance upstream can leave the heatsink cool while the junction runs hot. Measure or estimate the junction using the specified temperature reference.

Can a thermal camera measure LED junction temperature?

It observes accessible surfaces, not the buried junction. Surface emissivity and reflections also affect a reading, especially on bare metal.

Do I always subtract optical power from the electrical input?

Subtract it when calculating heat power for a heat-based method. When using a vendor thermal value, first check whether it was defined with heat power or electrical input.

Does a larger aluminum core always improve the curve?

No. The bottleneck might be the dielectric, solder joint, mount or heatsink. Use controlled comparisons to see whether a board change affects the target condition.

Should I use grease instead of a thermal pad?

Not automatically. Compare installed behavior and keep the product’s isolation, mechanical and aging requirements. A lab reference interface need not be suitable for production.

Can I find the faulty layer from one transient trace?

Usually not. Use controlled changes, repeat runs and construction evidence; a bend alone is not proof of a particular layer.

What if the curves separate only near the end?

Check mounting or cooling changes and confirm the difference is larger than run-to-run spread. Late separation is useful evidence about the boundary condition, not a unique diagnosis.

Can I qualify the board with the housing open?

An open test can help isolate a cooling problem. Use the intended closed configuration for release if that is how the lamp operates.

References

Discuss an Aluminum PCB Review

If the comparison points to the board, send the LED part number, PCB stackup, mounting drawing, heat load and temperature traces to sales@bestpcbs.com. Best Technology can review the proposed board construction with those inputs; the final assembly still needs to pass its own thermal validation.

Tags: aluminum pcb, LED Thermal Testing, Metal Core PCB, Thermal Impedance
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Oscilloscope Probe Loading: Is the Ringing on Your PCB?

November 13th, 2026

Oscilloscope probe loading occurs when the probe changes the signal at the point you are measuring. Before changing a PCB that appears to have clock ringing, repeat the capture at the same node with a shorter, appropriate ground connection and then compare a suitable lower-capacitance probe. A change in the waveform is evidence that the setup matters; it is not proof that the original PCB waveform was clean.

Consider a hypothetical low-voltage controller whose clock shows overshoot near the receiver. The task is to tell apart three possibilities: the circuit actually rings, the probe changes the circuit, or the measurement connection adds an artifact. Each calls for a different next step.

Oscilloscope probe resting beside an unpowered digital PCB — Illustrative probe and PCB. No connection or measured waveform is shown.

Oscilloscope Probe Loading Effect: What Changes?

A probe is an electrical load. Its resistance draws some current, and its capacitance draws additional current as the voltage changes. The connection to the reference node also has inductance. On a fast edge, the load can slow or reshape the actual node voltage, while the probe loop may introduce ringing in the displayed waveform.

Keep those effects separate. If connecting a second probe changes what a fixed reference probe sees, it supports the hypothesis that the circuit is being disturbed. If only the probe with a long ground connection shows strong ringing, the connection may be contributing an artifact. Neither result identifies every source of error; use the same signal event and comparable bandwidth for both captures.

Oscilloscope Probe Input Impedance: Check More Than Megohms

The resistance printed on a probe is not its complete impedance at high frequency. The input capacitance presents a lower impedance as frequency rises, so a nominally high-resistance probe can still load a fast or high-impedance node. Read the probe specifications at the tip and with the actual accessory, not just the oscilloscope’s front-panel input rating.

Check whether the probe expects a 1 MΩ or 50 Ω instrument input and whether the selected attenuation is supported. Connecting a scope’s 50 Ω input directly to a node that cannot drive that load changes the circuit. Use a suitable buffered or engineered measurement interface when the node cannot tolerate the proposed load.

Oscilloscope Probe Capacitance: A Worked Loading Estimate

In a hypothetical lumped circuit with a 50 Ω source resistance, 12 pF of added probe capacitance gives an RC time constant of 0.60 ns; 2 pF gives 0.10 ns. For an ideal voltage step into this first-order model, the respective 10–90% rise times due to that pole alone are about 1.32 ns and 0.22 ns. These are not actual probe specifications or measured PCB results.

Assumed tip capacitance	Calculated effect with 50 Ω
12 pF	50 × 12 pF = 0.60 ns; 2.197 × RC ≈ 1.32 ns.
2 pF	50 × 2 pF = 0.10 ns; 2.197 × RC ≈ 0.22 ns.

Use the estimate to screen for sensitivity, not to subtract time from a real waveform. The true driver has a finite edge, and PCB traces and probe leads may behave as distributed structures. This RC model cannot predict ground-loop ringing or diagnose reflections. Tektronix’s probe-loading note illustrates why capacitance can matter even when resistance looks high.

Oscilloscope Probe Compensation: Check the Instrument First

For a compatible adjustable passive probe, use the scope’s compensation output and the probe maker’s procedure. Under- or over-compensation can round the edge or add a leading bump. Correct that behavior before comparing board captures.

Compensation aligns the probe with the instrument input; it does not remove capacitance from the circuit or repair an unsuitable ground lead. Repeat the check after changing channels or attenuation when the equipment instructions call for it.

Oscilloscope Probe Ground Spring: Shorten the Loop

On a low-voltage ground-referenced PCB where the connection is safe, use a short spring or other recommended local ground connection. Compare the same clock pad with the long lead and short connection without changing the stimulus. If ringing amplitude or frequency shifts substantially, suspect the measurement loop and investigate before touching the board design.

Bench-scope ground clips are commonly earth referenced. Do not connect one to a switching node, floating rail or isolated return that must not be grounded; never defeat protective earth. Choose a suitably rated differential or isolated measurement arrangement when needed. See the Tektronix probe primer for why the ground lead and tip capacitance can form a resonant circuit.

Two oscilloscope probe heads and accessories beside an unpowered PCB coupon — Illustrative probe options. Check the specifications for the exact probe, tip and connection.

Active vs Passive Oscilloscope Probes

Choose the probe by allowed loading, bandwidth, amplitude and reference conditions, not by the active or passive label alone. A low-capacitance active probe can preserve a fast node better, but an active probe may have a narrower input range or tighter common-mode limits. A compatible low-capacitance passive probe can be adequate on the same node if its loading is acceptable.

Option	What to verify
Passive voltage probe	Tip capacitance, compensation, safe ground and short connection.
Active single-ended probe	Tip loading, dynamic range, offset and local reference compatibility.
Differential probe	Input and common-mode ranges, bandwidth and balanced connection.

Oscilloscope Probe Bandwidth: Compare Like With Like

Use the bandwidth of the complete scope, probe and connection. A lower bandwidth limit can make overshoot or fast ringing look smaller by filtering it. That may help when the measurement specification calls for a limited band; it does not show that the PCB physically improved.

Record the settings, sampling, probe accessory and approximate node reference. Compare the suspected ringing with the same bandwidth setting where possible. If one probe cannot cover the required band, do not accept a cleaner plot from it as proof of the fix.

Oscilloscope Probe Noise: Prove the PCB Fix Separately

If the suspected ringing remains under a validated setup, compare the driver and receiver relative to appropriate local references, with the intended load connected. Persistent ringing or incorrect receiver timing can justify reviewing termination, return geometry or the test pad’s own branch. The BestPCBs eye diagram guide covers related receiver-level evidence.

Change one board variable only after fixing the measurement method. Then repeat the same observation and check functional operation against the receiver’s actual limits. Save before-and-after captures with the point, probe, ground, bandwidth and board revision. A quieter plot alone is not a pass if the receiver still violates its timing or voltage requirements.

Frequently Asked Questions

Does 10× always mean low capacitance?

No. Check the specifications for the probe model, switch setting and accessory. Attenuation alone does not specify tip loading.

Can two probes on the same pad change the result?

Yes. Both contribute load, and ground connections can introduce additional paths. Use the second probe only as a controlled check and document what changed.

Should I probe the source or the receiver?

Start where the decision is made. For receiver margin, observe the receiver relative to its reference; compare the driver separately to investigate the source of the disturbance.

Can a solder-in probe tip solve every ringing problem?

No. It can shorten the connection but still has loading, bandwidth and voltage limits. It cannot fix a real board discontinuity.

Does a high sample rate replace probe bandwidth?

No. Sampling a filtered or distorted signal more often does not recover information lost in the analog measurement path.

Can the test pad itself cause reflections?

Yes. A branch to a test pad can become a discontinuity on a fast net. Include the pad and branch in the interconnect review, even if no probe is attached.

Does changing the vertical scale correct probe loading?

No. It changes how the acquired waveform is displayed or acquired, not the electrical impedance presented by the probe at the node.

What if the board only fails when I attach the probe?

Treat the probe as a possible cause. Compare supported lower-loading access and monitor function without the suspect connection before concluding the board fails on its own.

Prepare the PCB Measurement Review

For a Best Technology PCB fabrication discussion, send the board revision, stackup and test-access geometry to sales@bestpcbs.com. Include any controlled coupon requirements and keep the scope setup and receiver acceptance conditions with the design validation record.

Tags: clock ringing, oscilloscope probe loading, PCB signal integrity, probe capacitance
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