LVDS Termination Resistor Guide: Value, Wiring and Layout

November 10th, 2026

Key Takeaways

A conventional point-to-point LVDS link usually uses one differential termination at the receiver, commonly 100 Ω.
The termination both develops the received differential voltage and reduces reflections by matching the transmission line.
A representative 3.5 mA current through 100 Ω produces 350 mV; these are nominal teaching values, not universal guaranteed specifications.
Internal termination can replace an external resistor only when the exact device, I/O bank and active configuration support it.
Two ideal 100 Ω loads in parallel produce 50 Ω. Whether two loads are correct depends on the topology.
AC coupling needs appropriate transmitter-side loading, receiver bias and signal behavior—not just two capacitors.
Approve the channel using the receiver waveform and timing requirements, not a resistance reading alone.

An LVDS termination resistor is a resistor connected across the two signal conductors at the receiving end of a typical LVDS link. A common value is 100 Ω, selected to match the differential transmission-line impedance and convert the driver’s steered current into a small voltage that the receiver can detect.

Getting it right involves more than selecting a 100 Ω part. The receiver may already contain termination, a connector may extend the electrical path, and AC-coupled or multipoint links need different arrangements. This guide explains the principles, calculations, connection options and PCB decisions so a schematic can become a testable design.

Circuit-board differential traces and a small part near a receiver package — Illustrative rendering, not a reference footprint or validated routing.

what is lvds

LVDS means low-voltage differential signaling: information is represented by the voltage difference between two conductors, rather than by either conductor’s voltage to ground alone. The receiver decides whether P is above or below N.

Define the differential voltage as V_diff = V_P − V_N. The common-mode voltage is their average:

$V_{CM} = \frac{V_{P} + V_{N}}{2}$

A positive differential voltage does not require either pin to go negative relative to ground. In an illustrative 1.2 V common-mode system, P = 1.375 V and N = 1.025 V give +350 mV differential. Swapping these levels gives −350 mV. The two states span 700 mV differential peak-to-peak—not 350 mV peak-to-peak.

Consider a hypothetical data-acquisition board carrying ADC data to an FPGA. Each lane needs an electrically compatible receiver and a defined load; successful data capture also depends on clock-to-data timing. LVDS specifies electrical signaling, not the complete data protocol. See TI’s LVDS technology overview.

lvds termination resistor

In the usual DC-coupled point-to-point circuit, the resistor connects from P to N, directly across the receiver input pair. It is not inserted in series with either conductor and is not a pull-down to ground.

The driver steers current out along one conductor, through the load, and back along the other. Reversing the current direction reverses the differential voltage. The high-impedance receiver observes that voltage while the resistor provides the intended current path.

The same resistor is the load at the end of the transmission line. Matching the load to the line helps prevent an arriving edge from reflecting back along the pair. These are related functions: replacing the resistor with an open circuit removes the intended DC load and also creates a large impedance discontinuity.

For the ADC-to-FPGA example, trace the two nets all the way through adapters and connectors before drawing the termination symbol. A resistor already on a mezzanine card is still part of the circuit. Analog Devices explains receiver-end LVDS termination.

lvds termination resistor value

The familiar 100 Ω value follows from the intended differential line impedance and the driver’s operating load. It is a common starting point, not a resistor value to apply indiscriminately to every differential interface.

A nominal current-source model gives:

$| V_{diff} | \approx I R_{T} = 3.5 mA \times 100 Ω = 350 mV$

TI’s LVDS Owner’s Manual uses this representative model. Actual guaranteed output levels come from the selected driver’s electrical table.

Parameter	Value and scope
Differential termination	100 Ω; common design value
Steered current	3.5 mA; nominal model
Differential magnitude	350 mV typical; SN65LVDS1, 100 Ω
Specified output magnitude	247–454 mV; conditions below
Specified output common mode	1.125–1.375 V; SN65LVDS1
Nominal integrated load	110 Ω; SN65LVDT2 only

The SN65LVDS1 range above applies with R_L = 100 Ω and 3 V ≤ V_CC < 3.6 V under the datasheet’s specified conditions. At lower supply voltage, its minimum differs. The typical value is not a guaranteed minimum, and the nominal 1.2 V teaching example is not a universal input requirement. See the Rev M electrical tables.

lvds impedance matching

Match the termination to the pair’s differential characteristic impedance—not to the resistance of the copper traces. Characteristic impedance describes how a traveling wave relates voltage and current along the interconnect; a multimeter cannot measure it as a DC resistance.

For an ideal uniform line with real differential impedance Z_diff and a resistive termination R_T, the load reflection coefficient is:

$Γ_{L} = \frac{R_{T} - Z_{diff}}{R_{T} + Z_{diff}}$

These calculations assume a 100 Ω line and an ideal 3.5 mA driver for the separate steady-state voltage estimate:

Load	Load reflection	Ideal settled magnitude
90 Ω	−5.26%	315 mV
100 Ω	0%	350 mV
120 Ω	+9.09%	420 mV
50 Ω	−33.33%	175 mV

A positive coefficient means the reflected voltage has the same polarity as the incident wave; a negative value means opposite polarity. The percentage refers to the incident traveling voltage, not to bit-error rate or total signal loss. The settled-voltage estimate is not a prediction of the complete transition waveform.

A 120 Ω load can increase ideal settled amplitude while worsening the match to a 100 Ω line. That is why “more voltage” is not automatically better. Nonstandard values require both a device-load check and a channel assessment. The underlying reflection model is described in TI’s LVDS Application and Data Handbook.

lvds termination resistor power rating

Normal LVDS termination dissipation is small, but select the resistor using voltage across the load, not the IC supply voltage. For an ideal 350 mV differential magnitude across 100 Ω:

$P_{R} = \frac{V_{diff}^{2}}{R_{T}} = \frac{(0.350 V)^{2}}{100 Ω} = 1.225 mW$

Both polarities produce the same resistive dissipation. Using the 700 mV differential peak-to-peak value in this formula would overestimate the ideal two-state dissipation by four times.

A 1% external resistor is a practical starting choice when the design does not specify otherwise. Its package, temperature coefficient, rated-power derating and parasitic behavior still matter. A smaller package can simplify a short, symmetric connection, but assembly capability and inspection access also constrain the choice. Calculate margin from the actual maximum operating differential voltage and resistance limits; fault conditions need a separate review.

lvds termination resistor placement

Place an external termination close to the receiver input pins, with short and balanced connections to P and N. The electrical route from the resistor to the input matters more than the distance between component outlines.

If the resistor sits beside a connector but the receiver is farther inside the board, the segment beyond the resistor becomes an unterminated branch of the intended load point. It can still disturb the receiver even though the schematic shows a correct resistor value.

For scale, assume a 20 mm post-termination segment and a propagation delay of 6 ps/mm. Its one-way delay is 120 ps and its round-trip delay is 240 ps. Against a hypothetical 500 ps edge, that is not automatically negligible. These are teaching assumptions, not a universal length limit.

Place the resistor across the incoming pair without a long tee, an asymmetric detour or an avoidable via. A selectable footprint should remain compact even when unpopulated.

lvds internal termination

Internal termination replaces the external load only when the selected receiver actually provides it in the intended operating state. “LVDS-capable input” does not by itself establish that termination is present or enabled.

For example, AMD’s DIFF_TERM documentation describes enabling built-in 100 Ω differential termination. Availability and valid conditions depend on the FPGA family, bank, I/O standard and supply requirements. Treat those conditions as part of the hardware design, not just a software detail.

Choice	Trade-off
Internal load	Near input; device, bank and settings matter
External resistor	BOM controlled; placement and tolerance matter
Selectable	Flexible; document the active option

On the ADC board, record the FPGA input standard, bank supply and active termination setting alongside the BOM population option. Check reset and configuration behavior if the ADC starts driving before the FPGA is ready. Do not infer powered internal resistance from an unpowered ohmmeter reading.

lvds double termination

A conventional single-receiver link is overterminated if an external load duplicates the intended internal load. For two ideal 100 Ω resistances at the same receiving point:

$R_{eq} = \frac{100 \times 100}{100 + 100} Ω = 50 Ω$

The ideal 3.5 mA model then gives 175 mV rather than 350 mV. A real driver may depart from that model, and separated loads introduce transmission-line effects. Reduced amplitude alone therefore suggests a loading problem; it does not prove one.

Establish the active receiver setting and populated components, restore the intended load, then compare measurements using the same pattern and probe setup. A different topology, such as M-LVDS, can intentionally require two terminations; “two resistors” is not a universal fault diagnosis.

lvds ac coupling termination

AC coupling blocks the transmitter’s DC common-mode voltage, allowing the receiver side to establish another bias level. It also changes the DC current paths, so it must be designed as a complete interface.

Review three things together:

Transmitter operation: Does the driver need a DC differential load, and where is that path maintained after adding capacitors?
Receiver bias: Is the input internally biased, or does it need an external common-mode network?
Signal behavior: Can the clock or data tolerate startup charging and baseline movement during long intervals without transitions?

TI’s LMK00301 datasheet, AC-coupled differential operation shows arrangements that differ according to receiver termination and bias. Some maintain a driver-side DC load and accept the resulting swing reduction when a receiving load is also present. That is a designed network, not the accidental duplication discussed above.

DC-balanced data or a suitable continuous clock is easier to AC couple than an arbitrary static level. For the ADC example, consider idle patterns and clock stoppage as well as the normal stream. Do not copy a capacitor value without checking the longest transition-free interval, startup requirement and both devices’ input/output conditions.

lvds split termination

Split termination uses two resistors whose series sum provides the differential load. Two 50 Ω resistors connected from P through a midpoint to N present 100 Ω to an ideal differential signal.

The midpoint determines what else the circuit does. A capacitor from that midpoint to ground can provide a common-mode AC return. A prescribed bias network can establish a DC level in an appropriate AC-coupled implementation. A capacitor alone does not establish a DC bias because it is open at steady DC.

With equal 50 Ω resistors and identical common-mode movement on both lines, the resistors appear in parallel toward the midpoint: 25 Ω before the midpoint network. This differs from their 100 Ω differential series path. Mismatched parts or asymmetric routing can spoil that symmetry.

TI SLAA840 includes split-termination examples. Use them when the common-mode or bias requirement justifies the network; adding a midpoint capacitor is not a generic cure for poor differential routing.

lvds multidrop

One driver feeding several receivers is not the same as several devices taking turns driving a bus. Establish that distinction before deciding how many loads to fit.

Topology	Load arrangement
Point-to-point LVDS	One load at receiver
Single-source LVDS multidrop	One far-end load; short taps
Multipoint M-LVDS	Both bus ends; matched devices

In the single-source multidrop arrangement described by TI SLAA840, the driver is at one end and the load is at the farthest receiver. Intermediate receivers must not each add another parallel termination. Their capacitance and branch lengths still affect the waveform.

M-LVDS drivers are designed for the heavier loading associated with two bus-end terminations. Two 100 Ω end loads give a 50 Ω DC equivalent, but the distributed bus is not simply a point-to-point LVDS circuit with another resistor added. Use devices and a topology intended for that service. Analog Devices AN-1177 explains the distinction.

lvds pcb layout guidelines

Route the interconnect as a controlled electrical structure, preserving its geometry and reference environment through the entire path. A correct load cannot repair an inconsistent pair.

Impedance: derive trace width and gap from the proposed finished stackup, not another board’s nominal dimensions.
Reference planes: keep the intended reference continuous beneath the pair; review every layer change and return-path transition.
Symmetry: use comparable pad exits, vias, connector paths and protection on P and N.
Stubs: keep optional footprints and test connections compact. A long measurement branch becomes part of the circuit.
Timing: meet the device’s intra-pair and clock-to-data timing requirements without unnecessary tuning structures.

“100 Ω differential” does not mean any two individually 50 Ω routes will remain a 100 Ω pair when brought together. Coupling changes the result. Finished copper, dielectric height, pair spacing, solder mask and the nearby copper environment must agree with the impedance model.

For a concrete manufacturing handoff, see the Best Technology LVDS PCB routing example; its dimensions are an example, not a universal recipe.

Oscilloscope and differential probe beside a small PCB — Illustrative rendering of a test bench, not a waveform or compliance result.

how to measure lvds signal on oscilloscope

Measure the differential signal at the receiver using a suitable low-loading differential probe, and examine both amplitude and timing. A clean waveform at the transmitter does not establish what arrives at the input.

Record the data pattern, line rate, termination state, supply condition and probe point.
Use bandwidth appropriate to the edge speed, and keep the probe connection short and symmetric.
Measure differential magnitude, ringing and timing; assess common mode with an appropriate setup.
Use an eye diagram and functional error testing where the interface requirements call for them.
Compare results with the selected devices’ input limits and the project’s timing or eye criteria.

Do not attach ordinary grounded probe clips to the signal conductors. Nor should two 50 Ω-to-ground scope inputs be assumed harmless: they can introduce another 100 Ω differential load and alter common mode. Probing can create the fault you are trying to diagnose.

Power-off resistance measurements can identify accessible passive paths when the circuit allows it. They cannot establish characteristic impedance or prove powered internal termination. A TDR coupon checks representative fabricated geometry; the receiver measurement checks the operating channel.

lvds signal integrity

Signal integrity is the combined result of loading, interconnect geometry and timing—not a property established by one resistor reading. Before manufacturing, align the schematic, layout, assembly choices and receiver configuration.

For the hypothetical ADC-to-FPGA board, the release record should identify the exact endpoints, selected input standard, intended termination and population option, approved stackup, target impedance and tolerance, timing constraints, and verification plan.

Observed result	Useful next investigation
Unexpectedly low amplitude	Effective load and probe loading
Ringing near transitions	Stubs, connectors and impedance steps
Good amplitude, capture errors	Clock alignment, jitter and timing
Failure only at startup	Bias, reset and configuration sequence

These are starting points, not diagnoses. Close the loop by testing the same board revision and operating conditions against defined pass criteria. If a load change improves amplitude but worsens the eye or error rate, the job is not finished.

Frequently Asked Questions

Can a 100 Ω termination make a 3.3 V transmitter compatible with a 1.8 V receiver?

Not by itself. Supply voltage and signal voltage are different quantities. Compatibility depends on differential swing, common-mode range, pin limits and the receiver’s bank rules. Termination does not replace a required level translator.

Can a short LVDS link omit the resistor?

Do not remove it just because the traces are short. A current-steering driver may still require the load to establish its output voltage. A termination-free implementation needs explicit support from the selected device documentation and validation.

Is LVDS a communication protocol like SPI?

No. LVDS describes electrical signaling. The interface still needs defined data organization, clocking and timing. Two devices can both use LVDS levels without exchanging compatible data.

Does an idle receiver automatically produce a known logic state?

No. Failsafe behavior depends on the device and the fault condition: open inputs, shorted inputs and an undriven terminated line are different cases. Select a receiver with the required behavior or use its recommended bias arrangement.

Should every unused receiver input get 100 Ω?

Not automatically. Follow the device’s unused-input instructions. A resistor across an unused input does not necessarily establish a valid logic state, while adding loads to connected bus taps can overterminate the bus.

Can an ordinary series resistor replace the parallel termination?

No. Series source termination is a different method. A resistor inserted in one or both conductors does not provide the receiving-end current path and load required by a conventional LVDS circuit.

Does a working clock prove that the data lanes are correct?

No. Each lane can have a different load, interconnect or timing relationship. Verify the affected lanes and their relationship to the sampling clock rather than approving the interface from one clock trace.

When is AC coupling the wrong starting point?

When the interface must convey a static state indefinitely, has uncontrolled long idle intervals, or lacks a defined bias and startup plan. Begin with the device-supported DC-coupled arrangement unless there is a specific reason to isolate common-mode levels.

Conclusion

For a conventional LVDS link, start with the intended differential impedance, one receiving-end load and compatible input conditions. Then make the resistor value, placement, internal configuration and PCB geometry describe the same circuit. For a Best Technology PCB fabrication discussion, send the stackup, controlled net list, impedance requirements and receiver-area routing to sales@bestpcbs.com. Bare-board manufacturing checks and complete-channel electrical validation serve different purposes; define both where the application requires them.

Technical References

Tags: Differential Impedance, LVDS, Signal Integrity, Termination Resistor
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USB 2.0 Common Mode Choke: Check EMI and the Eye

November 10th, 2026

Add a USB 2.0 common mode choke only if the evidence points to noise on the data pair and the part improves emissions without consuming too much High-Speed signal margin. Compare a populated choke and a qualified bypass under the same test conditions. If emissions improve but the eye fails, the choke is not ready for production.

USB connector and a nearby small component on a circuit board — Illustrative rendering of a USB connector region, not a validated layout.

usb 2.0 common mode choke

A two-line choke uses coupled windings in series with D+ and D−. Ideally, signals flowing in opposite directions see little added impedance, while noise flowing in the same direction on both lines sees more. Real devices also have parasitics and differential loss. The part does not replace ESD protection, nor does it establish the pair’s PCB impedance.

usb common mode noise

First decide which path is carrying the noise. In a hypothetical USB service port, a radiated peak appears only when the cable is attached. That makes the cable a useful clue, not proof that D+ and D− are the source. Compare activity with controlled traffic and examine the shield and power paths. A data-pair choke will not necessarily address noise predominantly carried on VBUS or the shield.

common mode choke impedance

Read common-mode impedance versus frequency, then check the differential transmission and balance data. For example, Murata lists 90 Ω ±25% at 100 MHz for DLW21SN900SQ2 under its specified test conditions. That number is common-mode impedance at one frequency; it is not a differential routing target, bandwidth, or guarantee of attenuation in the product.

Parameter	What to compare
Common-mode impedance, Ω	Curve around the suspect frequency
Differential loss, dB	Curve across the relevant signal band
DC resistance, Ω	Maximum and balance between lines
Package and pinout	Channel mapping and footprint

usb common mode choke selection

Prefer a device with relevant mixed-mode data and enough signal margin in the implemented layout. A higher catalog impedance at one frequency can still be the wrong choice if loss or imbalance increases. Keep a qualified bypass option where practical, but do not assume a jumper footprint is electrically invisible. Compare the routing geometry and inspect the built boards.

usb common mode choke placement

Follow the actual PHY and protection guidance. TI’s TUSB121x example places the choke close to the receptacle, on the PHY side of the ESD devices. That is a named implementation, not a universal placement rule. Preserve the shortest protection path from the connector and review the two parts together. See the USB 2.0 ESD placement guide for the separate transient-path check.

usb differential pair routing

Keep the pair symmetric through the connector, protector, choke pads and layer changes. If you provide bypass footprints, avoid an unused branch hanging from only one line. A common-mode problem can be aggravated by imbalance in the routing, so compare both the footprint and the continuous reference before asking the choke to hide a layout problem.

usb 2.0 radiated emissions

Compare the two builds using the same cable, orientation, equipment arrangement and representative activity. In the example, suppose the suspect peak falls by 4 dB after fitting the choke. That is an illustrative comparison, not a lab result or a compliance claim. Confirm the absolute result against the project’s applicable limit and check repeatability before crediting the component.

Outcome	Decision
Emissions and eye both meet limits	Confirm repeatability before release
Emissions improve but eye fails	Reject; revisit part or routing
Eye passes but emissions do not improve	Trace the actual noise path

usb 2.0 eye diagram

Verify the 480 Mbit/s High-Speed eye in the applicable test mode and fixture, not just enumeration or a short file transfer. A tight result with one cable is a reason to repeat the approved test under the required conditions, not to declare the change safe. For the controller example, release the choke only after the emissions result and the applicable USB electrical result both meet the agreed criteria.

USB test fixture and cable on a bench beside an oscilloscope — Illustrative rendering of a test bench. Use the specified USB test fixture and real capture for acceptance.

FAQ

Is the choke needed on every High-Speed port?

No. Use evidence from the intended system and the device guidance. A correctly working port need not add unnecessary loading.

Can I select a choke using only its 100 MHz impedance?

No. Compare frequency-dependent common-mode behavior, differential loss and the actual board measurements.

Can a bypass trial leave the pads empty?

Not if that opens the signal lines. Use the qualified bypass connection for the designed footprint.

Does enumeration show the High-Speed eye passes?

No. Enumeration is a functional observation. Use the applicable electrical test for the eye and signal limits.

Will the choke fix ESD resets?

Not by default. Inspect the discharge path and protection design separately, then verify the system’s ESD behavior.

Should I compare different cables in the first A/B test?

Keep the cable fixed for the first comparison. Test additional required cables separately to verify system robustness.

Can a data-pair choke fix VBUS noise?

Only if the coupling path involves the data pair and the change is shown to help. Inspect the power path if that is the dominant source.

Does a lower measured peak mean the product is compliant?

No. Check the applicable limit, modes and repeatability. A relative improvement and a compliance result are different claims.

Sources

TI TUSB121x board guidelines; TDK: USB 2.0 EMC practice; Murata DLW21SN specifications.

Project Review

For a Best Technology fabrication discussion, send the stackup, D+/D− geometry, connector footprint and choke or bypass options to sales@bestpcbs.com.

Tags: Common Mode Choke, EMI Testing, Signal Integrity, USB 2.0
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Microvia Reliability: Read the Reflow Resistance Trace

November 10th, 2026

Don’t release an HDI lot on the strength of a cold continuity check alone when the purchase requirements call for reflow-monitored resistance. First verify that the coupon reproduces the critical via structure. Then compare its resistance trace with the agreed reference and temperature profile. A chain can read normally after cooling even if it opened during heating.

Mounted PCB cross-section with copper interconnections and dielectric layers — Illustrative rendering of a cross-section specimen. Use the actual stack drawing and coupon record to identify via geometry.

microvia reliability

Microvias connect adjacent PCB layers in dense layouts. During soldering, the board expands and contracts, stressing these connections. A room-temperature continuity result answers whether the path conducts at that moment. It does not reveal an interruption that occurs only at elevated temperature. Ask for the evidence that matches the anticipated assembly exposure.

stacked vs staggered microvias

A stacked design places one microvia above another. A staggered design offsets them and joins the paths on a shared layer. When the board uses both, identify which geometry each coupon actually represents. A result from a staggered chain should not be used to approve an unrepresented stacked interface. For routing and construction trade-offs, see the BestPCBs comparison guide.

Board feature	Check on the coupon
Stacked microvias	Same layer spans and stacked interface
Staggered microvias	Correct layer spans and offset pattern
Mixed connections	Coverage of each structure required for release

pcb daisy chain

A daisy chain connects many via structures in series so that a change anywhere in the path can appear in the resistance record. Ask for the chain ID, layer pairs, structure count and panel-to-coupon relationship. The resulting trace describes the chain, not the resistance or failure location of an individual via. A chain that includes other structures may require fault isolation.

Bare test coupon and measurement leads on an electronics lab bench — Illustrative rendering of a coupon setup, not a test log or a pass result.

pcb reflow profile

Compare traces only under the approved profile and measurement convention. Record the test method and revision, profile, cycle count, temperature measurement location and reference resistance. For a performance-based evaluation under IPC-TM-650 2.6.27, use the reference and acceptance criteria in the applicable revision and procurement agreement. Do not silently substitute a cold baseline for a specified hot reference.

Report field	Why it matters
Profile and cycle	Matches the specified exposure
Resistance in Ω or mΩ	Identifies the measured chain and reference
Change in %	Shows the result at the specified comparison point
Temperature and time	Locates the event within the cycle

microvia failure

Consider an illustrative chain with a specified hot reference of 0.500 Ω. A comparable point in a later cycle reads 0.530 Ω. The relative rise is (0.530 − 0.500) ÷ 0.500 = 6%. If the project limit were 5%, the reading would exceed it. A normal cold reading afterward does not cancel the event. These values are a worked example, not a test report or a universal limit.

Check whether the event is synchronized with temperature and whether other channels show a simultaneous fixture disturbance. Preserve the original trace and reference coupon. When instrumentation remains a plausible cause, use the documented investigation or retest procedure instead of deleting the event or releasing on the final reading alone.

pcb microsection analysis

Use the electrical record to choose where to section. A section can show a physical discontinuity at a sampled interface, but a clean section elsewhere cannot rule out a hot-only failure in the chain. Ask the lab to correlate the section location with the failed net, stack and panel rather than accepting an unlabeled image.

interconnect stress test pcb

Convection reflow simulation reproduces an agreed assembly heat exposure. DC current-induced thermal cycling is a different test method with a different heating mechanism and protocol. Don’t accept one in place of the other simply because both include resistance readings. Match the report to the contracted exposure, specimen and evaluation method.

pcb thermal cycling test

Specify separately any cycling needed to qualify the board for service. A reflow simulation result alone does not establish lifetime under operational temperature changes. For lot release, verify the approved coupon map, profile, complete trace and disposition of any anomalies. If the controlling geometry or hot record is missing, mark the evidence incomplete rather than treating the omission as a pass.

FAQ

Is the final resistance value enough?

No when the requirement covers behavior during the cycle. Inspect the agreed measurement interval and preserve any anomalous excursion.

Can an unmarked coupon represent every panel?

Not without documented traceability and an agreed sampling plan. Link its identity to the appropriate panel, lot and build.

Does a resistance excursion prove a microvia crack?

No. It locates a suspect time and chain. Check the test setup and use targeted failure analysis before assigning a cause.

Can I compare two chains with different numbers of vias directly?

Not by raw resistance alone. Geometry and chain length affect the value. Use the prescribed baseline and compare equivalent structures where possible.

Does a passed stacked coupon qualify a deeper stack?

Not automatically. Additional interfaces and different layers can change the behavior. Confirm that the evidence represents the intended construction.

Does the oven setpoint equal coupon temperature?

No. Confirm the recorded measurement convention and coupon temperature rather than assuming the displayed setting is the specimen profile.

Can I approve the lot if the report only says pass?

Only if that is sufficient under the agreement. When the purchase requires traces, conditions or specimen details, request the missing evidence before release.

What should I retain for a repeat order?

Keep the approved stack, coupon ID and drawing, reference convention, test profile, original records and disposition together with the production revision.

Sources

IPC-TM-650 2.6.27B: convection reflow assembly simulation; IPC-TM-650 2.6.26A: DC current-induced thermal cycling.

Project Review

For a Best Technology fabrication discussion, send the critical via stack, intended assembly exposure and coupon acceptance requirements to sales@bestpcbs.com.

Tags: HDI PCB, Microvia Reliability, pcb test coupon, Reflow Simulation
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PCB Thermal Relief Troubleshooting: Find the Hot Spot

November 10th, 2026

If a power terminal runs hot, don’t replace its thermal relief with a solid connection until you know where the voltage is lost. Under a controlled load, compare the terminal and joint with the pad-to-plane transition and the downstream copper. Only change the relief when the evidence points to that transition, then retest both solder quality and operation.

Bare PCB showing a through-hole pad connected to a copper area through relief spokes — Illustrative rendering of a relief connection. Use the actual exported copper to count and measure spokes.

what is thermal relief in pcb

Thermal relief leaves a gap between most of the pad perimeter and its same-net copper plane, with short copper spokes bridging that gap. Less copper cross-section slows heat flow out of the pad while soldering. The same restriction remains in service, so easier soldering and lower operating resistance are separate goals.

thermal relief vs direct connect

A direct connection is a useful comparison build when the suspect span is the pad-to-plane transition. Keep the connector, copper build and load the same. Changing the connector and the pad in the same trial makes it hard to tell which part of the current path improved. The general thermal relief design guide covers first-pass layout decisions; this article starts with a board that is already running hot.

Connection	When to consider it	Verify
Relief spokes	Plane slows joint heating	Joint, drop and heat
Direct copper	Spokes limit current path	Joint and copper neck
Revised spoke geometry	Both constraints matter	Actual fill and tests

thermal relief spoke width

Use finished width, length and copper thickness when estimating a spoke path. Increasing width or adding equivalent spokes can lower its resistance but also lets more heat leave the pad during assembly. In an ideal group of equal spokes, their conductances add in parallel. Real current distribution depends on where the plane is fed, so a layout with four spokes drawn does not necessarily share current evenly.

Parameter	What to verify
Spoke width and length, mm	Finished geometry on each connected layer
Remaining spoke count	Connections after zone refill and export
Copper thickness, µm	Applicable layer and fabrication build
Drop and temperature	Named points and defined load conditions

pcb thermal relief gap

The relief gap separates the rest of the pad from the plane. A larger gap can lengthen the copper bridge; a nearby clearance can remove a spoke entirely. Refill the zone after a routing change, run the connection checks and inspect the released copper layer. A net name or a schematic check cannot establish what was fabricated.

pcb thermal relief high current

Use the actual operating load and allowable drop to judge the power pad. In a hypothetical 8 A terminal comparison, suppose a four-wire measurement across matched pad-to-plane points gives 3 mΩ for one build and 1 mΩ for another. The corresponding drops are 24 and 8 mV; calculated dissipation in that measured span is 0.192 and 0.064 W. These values are not ratings or measured results. They show why a milliohm-scale restriction can matter.

Plan accessible, named voltage-sense points before energizing the setup. If the board exposes them, use the terminal metal, the PCB pad and the plane just beyond the relief as three successive references. Put the load-current leads outside the sense span. A large terminal-to-pad drop points to the joint and intervening metal; a large pad-to-plane drop points to the PCB transition. If the pin-to-pad boundary is not accessible, report the combined span instead of assigning the loss to the joint. A distant point on the plane can add the loss of an unrelated narrow region.

Compare like-for-like at the same load and thermal state. If the hot spot remains but all measured local voltage drops are small, check for a nearby heat source or an unsuitable surface for infrared temperature measurement before blaming the spokes. The busbar joint resistance guide shows the same principle of separating a joint from its conductor.

thermal relief soldering

Check the actual assembly method before treating a solid connection as a defect. A joint that is hard to make by hand may be acceptable under a qualified production process. Conversely, a low-resistance layout is not ready if the joint fails the required inspection. Compare the relief and direct options using representative boards and the intended process; don’t compensate with unapproved soldering conditions.

Power terminal on a circuit board with copper areas and nearby through-hole pads — Illustrative rendering of a power terminal. A real comparison requires the same load, assembly process and measurement span.

pcb copper pour

Trace the current from the connector through the pad, spokes or direct entry, layer transitions and the next component. The useful width is the narrowest effective path, not the largest patch of copper in the layout view. Keep unrelated pads on the chosen general rule; apply a documented override only where the individual connection needs it.

pcb thermal relief guidelines

Decide what to change based on the span that failed. For a joint issue, review solder fill and the assembly method. For a PCB transition issue, compare wider spokes or direct copper. For loss downstream, fix the neck or layer transition and leave a sound pad unchanged. Release only after the revised joint, drop and temperature rise meet the agreed limits at the intended load, ambient and enclosure conditions.

FAQ

Are four spokes always better than two?

No. More effective copper can lower resistance, but the result depends on geometry and feeding. It also changes heat flow during soldering.

Does increasing board copper weight fix a missing spoke?

No. First fix or qualify the actual connection. Extra copper cannot replace a segment removed by the pour clearance.

Can I apply the same relief to every ground pad?

Not by default. A signal return, power terminal and heat-dissipating pad may have different connection needs even when they share a net.

Is an exposed package thermal pad the same as thermal relief?

No. A package thermal pad may need to conduct heat away in service. Relief spokes deliberately reduce the copper path around a pad.

Can I use a trace-width calculator as the final acceptance test?

No. It can help screen the layout, but it does not capture every local bottleneck or reproduce the full assembly and load conditions.

Should I measure resistance cold or after loading?

Record both when useful and keep the measurement span fixed. The operating drop and temperature should be checked under the specified load.

Why does my CAD tool report incomplete relief?

A zone rule or nearby clearance can prevent the required number of spokes from connecting. Refill and inspect the actual copper before changing the rule.

Can the same choice be reused after a connector change?

Recheck the pad geometry, copper path, current and assembly conditions. The prior result applies to the tested construction, not automatically to a new footprint.

Sources

KiCad PCB Editor: zone and pad connection settings.

Project Review

For a Best Technology fabrication discussion, send the finished copper thickness, high-current pad geometry, expected load and intended assembly process to sales@bestpcbs.com.

Tags: Copper Pour, High Current PCB, PCB Thermal Relief, solderability
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CAN FD Termination Guide: Check Resistance and Ringing

November 10th, 2026

Start with two matched end terminations on a conventional linear CAN FD bus. With the bus safely de-energized and the applicable network isolated, about 60 Ω across CANH and CANL is a useful check for two nominal 120 Ω ends in parallel. It cannot tell you where those resistors are or whether a long stub is causing ringing. Check the physical ends next, then measure the differential and common-mode waveforms separately.

CAN controller PCB beside a twisted pair connected to a terminal block — Illustrative rendering of a CAN interface, not a validated circuit or a compliance result.

can fd termination

Termination matches the end of a transmission line to reduce reflected edges. The physical ends of the trunk are the ends that matter, not the two nodes with the lowest software addresses. Confirm the bus topology and cable impedance before applying the conventional two-end model. An engineered non-linear network needs its own analysis rather than extra resistors added by trial and error.

can bus termination resistor location

Walk the actual harness and mark both ends, every branch and any switchable termination. A termination at an intermediate node can still contribute the expected DC resistance while leaving a length of cable beyond it unterminated. In a hypothetical controller and sensor harness, a service node is plugged in midway and accidentally has termination enabled. If the far end is also missing its resistor, the meter can still show 60 Ω, yet the far end remains electrically open to an arriving edge.

can bus termination resistor value

For the conventional 120 Ω network, use a nominal 120 Ω differential termination at each physical end. In a split arrangement, two matched nominal 60 Ω resistors form one 120 Ω end. The midpoint capacitor adds a path for common-mode AC energy without adding a DC resistor across the pair.

Parameter	What to verify
Nominal end resistance	120 Ω for the conventional cable
Split pair	Two matched 60 Ω resistors per end
Midpoint capacitor	Value, rating and return for this design
Resistor power	Check fault voltage, duration and part rating

can bus termination resistance

With power removed and the network in the intended measurement state, compare the reading with the expected parallel combination. Two 120 Ω resistors give 60 Ω, one gives 120 Ω and three give 40 Ω in the ideal calculation. Treat those as clues, not acceptance limits: tolerances, other DC paths, internal switches and the connected harness can change the reading. Segment the harness as permitted and identify each termination before concluding that a board needs rework.

can fd split termination

Use a single resistor when the end is correctly matched and the common-mode behavior meets requirements. Consider split termination when the end match is right but common-mode disturbance remains an issue. It adds parts and a return path to review. It does not move a termination to the right place or shorten a stub.

Option	Use when	Verify
Single resistor	End match and emissions are acceptable	Value and physical location
Split pair plus capacitor	Common-mode improvement is needed	Matching, return and EMC result
Topology correction	There is an incorrect end or long stub	Reflection at the affected receiver

can bus split termination capacitor value

Choose the starting value from the transceiver and system guidance. NXP’s FS2400 example lists 4.7 nF as a nominal option, not a universal requirement. In a simplified common-mode model, the two 60 Ω branches act in parallel, so the effective resistance is 30 Ω. Together with 4.7 nF that gives about 1.13 MHz for the ideal RC corner. Cable and return impedances, parasitics and other components change the real response. That number is not a CAN FD data-rate limit and cannot predict compliance.

can bus signal reflections

If errors cluster after edges or at the faster data phase, look for timing and topology clues before changing the capacitor. On the hypothetical service harness, restore termination at the physical far end and disable the misplaced branch termination. Repeat the same capture. If ringing persists at one branch, compare the branch connection and length against the approved network design. A changing common-mode signal alone is not proof of a differential reflection.

can bus oscilloscope waveform

Measure CANH minus CANL for differential behavior and, with a suitable referenced and matched setup, use their average to inspect common mode. Follow the instrument and equipment safety instructions and avoid grounding a floating bus through the probe. Compare the same receiver, harness, traffic and supply conditions before and after changes. Release only when the correct end map, resistance, waveform or timing limits, error behavior and any required system EMC tests meet the project plan.

CAN evaluation board and twisted pair on a bench near an oscilloscope — Illustrative rendering of a scope bench. Use calibrated measurements and the actual receiver location for comparison.

FAQ

Why do I see 60 Ω but still get errors?

The meter cannot locate the resistors or see stubs, receiver timing or interference. Confirm the end map, then capture signals at the failing receiver.

Should every node include an enabled 120 Ω resistor?

No. In a conventional linear trunk, enable termination at the two physical ends. An optional resistor footprint on an intermediate node can remain unpopulated or disabled.

Does split termination change the nominal differential DC resistance?

Not when each end still sums to the specified end resistance and the midpoint capacitor has no DC conduction path under the measurement conditions.

Can I choose capacitor size by looking at the data rate?

Not alone. The midpoint network targets common-mode behavior. Start from the device guidance and verify it against the actual noise and immunity requirements.

Does unplugging a node always leave the resistance unchanged?

No. The unplugged module may contain an end resistor or active termination. Identify what was removed and re-evaluate the expected reading for that configuration.

Should I fit a common-mode choke before changing the layout?

Check the failure mechanism first. A choke may help a specific emissions or immunity issue, but it will not correct an unterminated cable end or an overly long stub.

Is a clean waveform at the transmitting node enough?

No. Check the receiver that sees errors and other electrically distinct points. A reflection that is mild at one location may be significant at another.

What if the conventional 60 Ω rule does not fit this network?

Use the network designer’s topology and expected measurement state. Switched termination, active networks and branches require interpretation beyond the simple parallel model.

Sources

NXP AN14183: CAN components example; TI: TCAN evaluation module termination options; TI: split termination and common-mode behavior.

Project Review

For a PCB fabrication discussion, send Best Technology the board stackup, connector region and proposed termination footprints at sales@bestpcbs.com. If the protocol itself is still being selected, see the CAN bus vs LIN bus guide.

Tags: CAN FD, PCB Layout, Signal Integrity, Split Termination
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USB 2.0 ESD Protection: Where to Put the Diode on a PCB

November 10th, 2026

For a USB 2.0 High-Speed port, start with a low-capacitance ESD diode close to the connector. Route D+ and D− past the protection pads without long branches, and give the diode a short return into the intended reference. Verify both USB signal quality and system ESD behavior: a board can enumerate and still reset during a discharge, or survive a strike and still fail the High-Speed eye test.

USB-C receptacle with small protection components at the edge of an assembled PCB — Illustrative rendering of a connector area, not a reference layout or a test result.

usb 2.0 esd protection

Protect the path from the exposed connector to the USB transceiver. When a transient exceeds the diode’s operating region, the diode conducts current into its return path instead of allowing all of the pulse to continue toward the transceiver. During normal signaling the device should remain off, but its capacitance still loads the pair. The goal is to minimize both the discharge loop and the disturbance seen by the data signals.

usb esd protection circuit

Draw two paths before choosing the footprint: the D+/D− signal path from the connector to the PHY, and the transient current path from each exposed data line through its protector into the designated return. The reference circuit for the selected part determines which pin is the return and whether the device uses a rail reference. A D+/D− protector does not establish protection for VBUS, CC or SuperSpeed pairs. For the rest of the interface, see the USB-C PCB design guide.

usb 2.0 esd protection diode

Choose a device against the PHY and connector requirements, not the largest advertised discharge rating. For example, TI’s USB application note lists ESD122 as a dual-channel D+/D− option with a 3.6 V reverse working voltage and 0.2 pF listed capacitance. Those figures belong to that device; use its current datasheet for test conditions and limits, then check actual layout and system behavior.

Parameter	Decision check
Working voltage, V	Check against normal line voltage
Line capacitance, pF	Use stated test conditions and PHY budget
Clamping voltage, V	Compare only at matching pulse conditions
Channel and package	Confirm pin map and a routable return
Discharge rating, kV	Check method; verify on the complete product

esd diode placement

Put the protector at the first practical point after the connector and keep both the connection to the data pads and the discharge return short. A component can look close in the placement view while its ground trace makes a long trip around a cutout. Check the copper layers and return vias, not just the component outline. Do not route the unprotected connector segment alongside sensitive circuitry if it can be avoided.

Close-up of a board-edge USB-C receptacle and a nearby black leadless component — Illustrative rendering. Verify the chosen footprint and discharge return on the actual PCB.

usb esd protection layout

Prefer flow-through routing when the part and footprint allow the data traces to pass directly through the protection-pad area. The diode remains a shunt element; the name describes the routing, not a series electrical connection. A short branch can be an alternative if the pinout forces it and the implemented design passes both signal and system ESD tests.

Routing option	Use and trade-off
Flow-through	First choice when pad map and return align
Very short branch	Possible when constrained; measure the result
Long branch or remote clamp	Revise: extra stub and transient loop

usb differential pair routing

Keep the two data paths physically similar through the connector, protector and first layer transition. Review reference continuity and avoid adding a long test stub to only one member of the pair. In a hypothetical compact service-port board that resets during cable-side testing, first inspect the discharge route and nearby reset or power circuits. If the same board also shows poor High-Speed signaling, check the diode capacitance, pad discontinuities and pair asymmetry before choosing a different clamp rating.

usb 2.0 differential impedance

The usual High-Speed differential routing target is 90 Ω nominal; confirm the tolerance and stackup requirements for the design. A calculated trace width covers the uniform section, not the pad and via transitions. Review those transitions separately, and include the protection device’s capacitance. The relevant data rate is 480 Mbit/s in High-Speed mode, but edge behavior is not determined by the bit rate alone.

usb 2.0 eye diagram

After a layout revision, verify the applicable High-Speed electrical test separately from the system ESD test. Use the specified USB test mode and fixture for the electrical test; for ESD, record the strike point, polarity, operating mode and allowed recovery behavior under the product test plan. Monitor real data traffic, resets and re-enumeration. Release only when the electrical result meets its applicable limits and the product meets its own ESD performance criterion. Successful charging or idle enumeration is not a substitute for either check.

FAQ

Can one array cover VBUS and the two data lines?

Some products can, but check the channel specifications and routing. VBUS operating voltage and exposure may differ from the data lines.

Is a larger TVS diode always a safer upgrade?

No. A larger part may add capacitance or create a worse return path. Check clamp behavior under comparable pulse conditions as well as link quality.

Can I place the protector on the bottom side?

Sometimes. Compare the complete path including signal vias, return vias and loop geometry. Verify the actual implementation rather than judging it by distance in a top view.

Should the common-mode choke go before the diode?

In TI’s TUSB121x example it follows the ESD protection. Confirm the sequence in the PHY and protector references and qualify it on the actual board.

Does a connector shield replace the data-line protector?

No. Shield bonding and signal-line protection address different paths. Follow the intended chassis and board grounding architecture rather than assuming they are interchangeable.

Why might the port restart even though no diode failed?

A transient can disturb the supply, reset path or reference. Capture the symptom and investigate the current route and nearby sensitive circuits before replacing the diode. The PCB ground bounce guide explains how a changing local reference can show up in a measurement.

Is a device-level rating proof of system compliance?

No. The assembled product adds connector, enclosure, layout and grounding variables. Verify it with the applicable system test and performance criteria.

Does this placement apply unchanged to USB SuperSpeed?

No. Check the separate transmit and receive paths, channel budget and AC coupling architecture. This guide addresses USB 2.0 D+ and D−.

Sources

Texas Instruments: ESD and Surge Protection for USB Interfaces; Texas Instruments: TUSB121x board guidelines; Nexperia: ESD protection for USB 2.0 interfaces.

Project Review

For a PCB fabrication discussion, send Best Technology the proposed stackup, pair geometry and connector-to-protector region at sales@bestpcbs.com.

Tags: Differential Routing, esd protection, Signal Integrity, USB 2.0
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Busbar Joint Resistance: Find the Missing Millivolts

November 10th, 2026

If a thicker PCB busbar does not fix voltage drop, measure the straight copper and each connection separately. A larger cross section lowers the bar’s bulk resistance, but it does not remove contact resistance at bolts, press-fit transitions or board terminals. Fix the segment that consumes the budget, then repeat the hot test.

Copper busbars attached to terminals on a power PCB — Include the attachment and board transitions in the complete path. Illustrative rendering; not a production or test record.

Busbar Joint Resistance

Busbar joint resistance is the electrical resistance of a connection between current-carrying parts, as observed over a defined measurement span. A reading across a joint often includes some adjoining copper. Put the sense points in the drawing so another engineer can reproduce what the number represents.

Consider a hypothetical low-voltage power board that misses an 8 mV path budget at 40 A. The route includes a short copper bar and two connections. The next revision should not add more copper until the test identifies where the drop occurs.

Copper Busbar PCB

A copper busbar can carry current separately from an etched board trace. The feed, contact and exit still need to carry the same current. A press-fit, bolted or soldered connection has its own construction and verification requirements. Do not generalize current or torque limits across connection types.

Draw the path from supply to load and mark the intended measurement spans. If the board uses an embedded busbar, check the transitions into and out of it as well as the main copper. The Best Technology embedded busbar design guide covers related construction choices.

Heavy Copper PCB

Compare a heavy copper PCB path and a busbar by their complete current paths. Heavy copper can avoid a separate mechanical interface over part of the route, but narrow necks, vias and terminals can still dominate. A bar offers a separate copper cross section while adding transitions that need qualification.

Option	Check first
Heavy copper PCB	Narrowest trace, via bank and terminal
Board-mounted busbar	Straight bar and every attachment
Embedded busbar	Copper insert and board transitions

Choose by drop, temperature, assembly and service requirements, not the nominal copper area alone.

Copper Busbar Resistance Calculator

Estimate only the uniform copper section with R = resistivity × length ÷ area. Use matching units. For an illustrative room-temperature copper resistivity of 0.0172 Ω·mm²/m, 0.050 m length and 20 mm² area, the bar is about 0.000043 Ω, or 43 µΩ. The estimate excludes both joints and nearby constrictions.

Use actual material, dimensions and operating temperature when the budget is tight. The calculated 43 µΩ is not a current rating or a measured property of the hypothetical assembly.

Busbar Voltage Drop Calculation

Convert each resistance to voltage drop with V = I × R. In the example, assume two measured-span resistances of 100 µΩ each, excluding the straight segment. At 40 A they account for 8.00 mV together. The 43 µΩ straight section adds 1.72 mV, so the full path is 9.72 mV and exceeds the illustrative 8 mV budget.

Path segment	Resistance used	Drop at 40 A
Straight bar	43 µΩ	1.72 mV
Joint span A	100 µΩ	4.00 mV
Joint span B	100 µΩ	4.00 mV
Full path	243 µΩ	9.72 mV

These are teaching inputs, not field results. Even doubling the bar area would leave about 8.86 mV if the two connections were unchanged.

Four Wire Resistance Measurement

Use separate current and sense connections to reduce the influence of lead resistance. In a qualified low-energy resistance setup, place the sense contacts at the named points and use the instrument’s appropriate method. A two-wire reading can be dominated by test leads and contacts at this resistance scale.

At very small voltages, thermoelectric offsets can matter. Use a suitable measurement method, such as current reversal when the equipment and test procedure support it. Document what copper is inside each span and do not sum overlapping spans as separate resistances.

Bolted copper overlap joint in a bench test fixture — Define the voltage-sense span around the connection. Illustrative rendering; not a production or test record.

Busbar Temperature Rise Test

Repeat the temperature and voltage checks in the approved operating setup. At 40 A and 100 µΩ, each illustrative joint span dissipates I²R = 0.16 W. Whether that creates a hot spot depends on the local heat path, contact area, airflow and enclosure. A room-temperature resistance pass does not establish operating temperature.

Measure at consistent points after the agreed dwell or steady-state condition. Use only a rated, guarded setup under the approved procedure. If the joint heats more than the bar, inspect its construction and nearby constrictions before adding copper to the straight section.

Busbar Joint Resistance Test

Release the design when the assembled path meets the specified voltage and temperature limits and the connection can be built repeatably. Record joint type, materials, assembly instructions, sense locations, current and thermal conditions. For bolted joints, follow the approved hardware and torque specification rather than a general table.

After a correction, rerun the same segment and full-path checks. If voltage drop is still above target, confirm whether the remaining loss moved to a different transition before selecting another design change.

Frequently Asked Questions

Does a thicker copper busbar fix every voltage-drop problem?

No. It lowers the resistance of the uniform copper segment, but contacts, vias and terminal transitions may account for most of the loss. Measure the sections separately and compare them with the path budget. Increase copper only when the measured or modeled bottleneck justifies it.

Where should voltage sense points go?

Place them at repeatable points that bracket the segment you intend to measure. Include the positions on a drawing and note any adjoining copper inside the span. Changing the points can change the apparent joint resistance even when the physical connection has not changed.

Can I use a standard two-wire multimeter for a micro-ohm joint?

A two-wire reading includes lead and contact resistance, which may be larger than the joint itself. Use a suitable four-wire method and instrument for the expected range. Verify the setup and its offset before interpreting small differences between two joints or two assembly revisions.

Can a good cold measurement rule out a hot joint?

No. Temperature, contact condition and the operating environment can change the result. Use the cold measurement to locate and compare segments, then perform the required operating-current thermal test in an approved setup. Check both voltage drop and temperature against their separate limits.

Why can two identical-looking joints read differently?

Contact preparation, hardware, fit, plating and assembly variation can change the interface. First verify that the sense spans and test conditions match. If the difference remains, compare the controlled build records and examine the actual joint rather than assuming the bar dimensions are wrong.

Should I increase bolt torque to lower resistance?

Use only the approved joint specification for that hardware and construction. Extra torque is not a general fix and may damage parts or change the interface. Review the contact surfaces, assembly method and approved limits with the process owner, then verify the corrected build.

Can I compare a press-fit joint directly with a bolted joint?

Compare them against the same product requirements and use equivalent measurement boundaries. The assembly controls and local geometry differ, so document what each reading includes. Check resistance, temperature and mechanical reliability for the actual connection rather than ranking the joining methods by name.

What evidence is useful for a PCB busbar review?

Send the bar and terminal drawings, current and drop limits, stackup, connection method and intended operating conditions. Include a marked sense-point map and any measured segment voltages. That lets the reviewer distinguish copper cross section, board transitions and joint behavior before recommending a change.

References

Discuss Your PCB Requirements

For a Best Technology fabrication review, send the current path drawing, busbar and terminal geometry, and your voltage and temperature limits to sales@bestpcbs.com. If you have measured drop, mark the actual sense points.

Tags: Busbar Joint Resistance, Copper Busbar Drop, Four-Wire Joint Test, High Current PCB Connections
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PCIe AC Coupling Capacitor Placement: Check Both Paths

November 10th, 2026

Place PCIe AC coupling capacitors only after checking which part of the link is responsible for each transmit path. Then place the two parts as a matched pair and verify their pad transitions in the actual stackup. A capacitor can be correct in the schematic and still introduce an avoidable discontinuity on the board.

Pair of ceramic capacitors placed on two differential PCB traces — Check each series part and its placement in the complete lane. Illustrative rendering; not a production or test record.

PCIe AC Coupling Capacitor Placement

Start with the platform’s channel drawing, not a rule such as “always next to the transmitter.” The transmit path tells you which lane needs coupling; physical position depends on the device and topology. Confirm which board or module provides the series parts and whether the device already integrates coupling.

Consider a hypothetical endpoint on an adapter connected to a host through a slot. Mark host transmit and endpoint transmit as separate paths. A placement decision that is correct for one direction does not automatically assign the parts in the reverse direction.

AC Coupling Capacitor for PCIe

A series coupling capacitor blocks DC while allowing the changing signal to reach the receiving path. It is not the same part as a supply bypass capacitor or a capacitor that links reference planes. On a differential lane, the approved coupling arrangement must be implemented on both conductors.

Review item	What to verify
Transmit ownership	Host and endpoint paths traced separately
Existing series parts	On-device, adapter, or host implementation
Placement	Topology-specific vendor guidance
Part geometry	Same approved launch on both conductors

Check the schematic against the actual channel and bill of materials. Do not add a second pair simply because a connector sits between boards.

PCIe AC Coupling Capacitor Value

Choose capacitance from the applicable platform or device documentation. TI’s PCIe Gen 5 layout note discusses a 75–220 nF range and describes 220 nF as typical in its context. Those values do not override requirements for a specific component, topology or implementation.

Check approved value, tolerance, package, voltage and the relevant high-frequency model together. A nominal capacitance match does not prove two components behave the same through their mounting geometry and parasitics.

AC Coupling Capacitor Size

Compare the solder land with the controlled trace before selecting a package. In TI’s illustrative Gen 5 layout, a 12 mil pad is wider than a 5–7 mil trace. At an illustrative 6 mil trace width, the pad is twice as wide. That ratio is a geometry warning, not a formula for the resulting impedance.

Placement option	Potential benefit	What to confirm
Smaller approved package	Smaller pad transition	Assembly and component limits
Existing larger footprint	Established assembly process	Modeled discontinuity is acceptable
Staggered pair	Fits a crowded area	Both paths still have comparable electrical response

Differential Pair Routing Guidelines

Make the two capacitor launches geometrically comparable. Use matching footprints, equivalent approach and exit routes, and comparable vias and reference environments. Avoid adding a jog or changing layers on one conductor just to align both components visually.

If routing forces a stagger, compare the actual two-path electrical response rather than assuming a neat centerline layout compensates for it. Keep nearby copper, neckdowns and return geometry in the model.

Parallel copper routes with corresponding SMD footprints on a test coupon — Compare the two pad transitions and their reference geometry. Illustrative rendering; not a production or test record.

Differential Pair Impedance

A wider mounting pad can create a local impedance dip. The depth of that dip depends on the dielectric, pad, neighboring conductor and reference plane. A small package or an engineered transition can reduce the discontinuity, but neither automatically proves the channel is within budget.

Model the footprint and launch together, and compare the result with the channel’s permitted impedance and loss behavior. Use the final land pattern, not only the package body dimensions or the nominal routed trace impedance.

PCB Return Path

Preserve the intended return path. Some platform notes use a localized reference-plane void under the capacitor launch to reduce excess capacitance. Treat that as a stackup-specific design choice. Do not cut a long slot beneath the pair or transfer the same void to a board with different layers without checking the effect.

Compare an intact reference and the proposed local relief in the actual stackup if the device guidance permits. Include both conductors and surrounding geometry. If local impedance improves but conversion or return-path behavior worsens, revise the transition instead of approving it on a single result.

PCIe Gen 5 Layout Guidelines

Release the design when ownership, capacitance, placement and both electrical paths have been checked against the approved platform. For the hypothetical adapter, verify both transmit directions, then compare the matched footprint against the actual connector and stackup. Save the channel model and the intended verification method with the board revision.

Use the Best Technology PCIe routing guide for the wider channel constraints. A link that trains on one bench sample is useful evidence, but it is not a substitute for the margin or compliance tests required for the product.

Frequently Asked Questions

Do PCIe coupling capacitors belong next to the transmitter?

The transmitter identifies the path that needs the approved coupling arrangement. It does not create a universal physical placement rule. Check the platform topology and device layout guidance. A chip-to-chip path and a chip-to-connector path can have different recommended locations for the same function.

What if both boards already contain series capacitors?

Trace the channel and confirm whether the parts are intended to operate together. Two series capacitors change the effective coupling behavior, so do not leave both simply because each board uses a familiar reference design. Resolve ownership against the approved host, adapter and endpoint requirements.

Can I place one capacitor farther along the pair?

Only if the resulting channel still passes the applicable electrical checks. The location difference can change how the discontinuities interact. Compare the complete launch, return environment and differential response rather than treating matched copper length or identical component values as sufficient evidence.

Is 0201 always the best package?

No. A smaller package can reduce the pad transition, but it must be available in the approved electrical value and suitable for the assembly process. Use the actual mounting land and model. A different package is acceptable only if the electrical and manufacturing requirements are met.

Does a plane void always improve the channel?

No. A controlled local void can help a particular capacitive pad transition, but a larger or poorly placed opening can disturb the return path. Follow the device guidance and compare the geometry in the actual stackup. Do not apply a blanket cutout underneath the entire lane.

Can an AC coupling capacitor repair a bad reference-plane transition?

No. The series component has a different function from managing a signal’s return path. The pad and nearby vias must still have a suitable reference environment. Check the reference-plane transition and coupling launch independently, then evaluate their combined effect in the complete channel.

What should I check after a PCIe link trains successfully?

Confirm the expected lane width and operating speed, then follow the platform’s margin and validation plan across required conditions. Keep the channel model, device settings and assembly revision with the results. One successful training event does not prove every lane and product condition has adequate margin.

What files help with a capacitor placement review?

Send the transmit ownership diagram, schematic, package and land pattern, final stackup, and both conductors around the capacitor. Include connector and via details plus any proposed plane relief. That makes it possible to compare the two launches instead of judging the placement from a cropped image.

References

Discuss Your PCB Requirements

For a Best Technology fabrication review, send the PCIe stackup, capacitor footprint and paired route geometry to sales@bestpcbs.com. Mark the connector transitions and any localized reference-plane voids.

Tags: Differential Pad Symmetry, PCIe AC Coupling Placement, PCIe Channel Verification, Series Capacitor Launch
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Serpentine PCB Trace: Check Delay, Not Just Length

November 10th, 2026

A serpentine PCB trace adds centerline length, but tightly spaced bends can change how much delay the added length produces. Start with the timing error you need to correct, make a straight-trace estimate, and then compare the actual routing shapes on the same stackup. A CAD length match is not the final pass condition.

Bare PCB coupon with a folded copper trace and a straighter reference route — A folded path adds length, but closely spaced legs can couple. Illustrative rendering; not a production or test record.

Serpentine PCB Trace

A serpentine trace folds extra conductor into a limited area. Adjacent turns can couple to each other, so the folded section may not behave like the same length of isolated straight trace. The effect depends on the geometry and signal spectrum rather than the shape name alone.

Consider a hypothetical source-synchronous interface with one signal arriving 24 ps early at the receiver. The designer can use a compact meander or route a more open detour. Both add the same CAD length on the same layer. The decision is which leaves acceptable arrival time and waveform quality.

Trace Length Matching

Use CAD length matching to screen the layout, then compare electrical arrival time at the relevant pins. Include package delay, via transitions and route layers when the interface timing model calls for them. Two equal trace lengths on different layers need not produce equal delays.

For the example, keep the vias and reference planes unchanged in both candidates. Correct only the early signal, and measure against the same reference signal and switching criterion. The Best Technology trace length matching guide covers the broader timing budget.

PCB Trace Propagation Delay

As a first estimate, multiply added length by the straight-trace propagation delay per unit length for the actual layer. If an illustrative straight route has 6 ps/mm of delay, 24 ps ÷ 6 ps/mm suggests 4.0 mm of added centerline. This calculation is a starting target, not the predicted delay of a coupled meander.

Input	Example only
Early arrival	24 ps
Straight trace estimate	6 ps/mm
First added-length target	4.0 mm
Electrical acceptance	Use the interface timing budget

Do not reuse 6 ps/mm across all stackups. Use layer-specific data or a suitable field model and keep the package and board portions of the timing budget distinct.

PCB Trace Spacing

Define spacing between adjacent serpentine legs edge to edge, and note the width and distance to the reference plane. Close parallel runs and long coupled overlap can change both the delay and the impedance behavior. There is no single spacing multiplier that proves the path meets a particular timing budget.

When room is available, compare fewer, more open bends or a gently extended route with the compact geometry. Use a continuous reference plane and avoid creating a new coupling problem with nearby traces to make room for the tune.

PCB Crosstalk Simulation

Model the tuning section with its actual neighbors and return plane, not as a straight segment with the same length. Inspect the simulated transfer response or time-domain arrival, impedance discontinuities and relevant crosstalk. Coupling within one folded signal is a separate concern from coupling to an adjacent aggressor; both can matter.

Candidate	Why try it	What can disqualify it
Tight meander	Fits a narrow corridor	Delay gain or impedance margin is poor
Open meander	Separates neighboring legs	Uses space needed by another route
Longer detour	Avoids tightly packed folds	Adds vias or changes reference path

Compare candidates at the same electrical reference points. An apparently faster waveform caused by unequal fixture or launch models is not evidence about meander spacing.

PCB test structures with tightly and loosely folded copper routes — Compare tuning shapes at the same electrical reference points. Illustrative rendering; not a production or test record.

Differential Pair Skew Compensation

In a differential pair, determine whether the problem is skew within the pair or delay between pairs. Adjusting one conductor can correct intra-pair skew, but a wide detour may also disturb pair coupling and create mode conversion. Routing both conductors together changes pair delay while preserving symmetry better, but does not selectively correct one conductor’s lead.

Keep the interface-specific limits and validate the differential waveform and mode conversion where they matter. Do not transfer a tuning prescription from a single-ended bus directly to a tightly coupled differential pair.

Serpentine Routing Guidelines

Compare both candidate routes against a straight reference and change one tuning variable at a time. Suppose a hypothetical controlled simulation predicts 18 ps added delay for a tight shape and 23 ps for an open shape, each with 4.0 mm added CAD length. The remaining error would be 6 ps or 1 ps, respectively. These values are illustrative, not measured or expected values for any design.

If both pass timing and signal quality, choose the geometry that fits without disturbing adjacent routes. If neither passes, reconsider the placement or route and rerun the analysis. Do not add another fold solely to remove a visual mismatch in CAD.

Time Domain Reflectometry PCB

Use time-domain reflectometry to check impedance changes through the tuning section. A reflection trace is not a direct one-way delay comparison between two receivers. For arrival time, use a suitable through measurement, a correctly referenced transmission model or a calibrated system measurement, depending on the design.

Release when the timing result, discontinuity limits and relevant neighboring-net or differential checks all pass. Keep the route, stackup, reference planes and model or test conditions linked to the verified revision so the result survives the next design change.

Frequently Asked Questions

Does a serpentine always add the expected delay per millimeter?

No. The straight-line estimate is useful for sizing the first candidate, but close folds can change effective delay. Simulate or measure the actual routed section and compare it with the same reference path. Keep the signal bandwidth and the reference planes consistent across candidates.

Is a larger gap always the best solution?

A larger gap can reduce interaction between adjacent legs, but it costs routing area and may push the route toward other signals or a broken reference. Compare the actual alternatives against timing and signal-quality limits. Prefer the one that passes without creating a new layout problem.

Can I tune two traces by matching their length on different layers?

Not without checking layer-specific delay. Different reference spacing and dielectric construction can change propagation, and vias add transitions. Use a timing model that includes those paths. A length report from the layout tool is a geometry check, not proof that the two signals arrive together.

Should I put the whole tune near the receiver?

There is no universal location. For a differential pair, think about where skew is introduced and how much unbalanced routing the correction creates. For a single-ended group, check neighboring signals and the return path. Compare the actual proposed positions in the model rather than relying on a default location.

Can a tightly folded trace be acceptable on a slow signal?

It can be acceptable if the actual edge, timing and noise limits are met. Repetition rate alone does not describe signal bandwidth; a low-rate interface can still use fast edges. Use the driver transition and interface constraints to decide how much validation the geometry needs.

What if the timing model and bench test disagree?

Check the reference planes, launch geometry, stackup and measurement thresholds before blaming the routing. Compare the same edge and operating condition, and account for fixture effects where necessary. Retain both records and resolve the difference before using the model to justify a marginal result.

Is the CAD tool’s differential tuning score enough for release?

No. The tool can show length and rule compliance, but the electrical result depends on stackup, coupling, transitions and the interface budget. Verify the actual differential response and skew where required. A clean length report does not certify that the tuned geometry preserves signal quality.

What files help with a serpentine routing review?

Send the routed section and neighboring nets, stackup and reference layers, trace dimensions, spacing, via details and the timing target. If possible, include both the compact and open alternatives. This gives the reviewer enough information to compare the real geometry rather than just the CAD length.

References

Discuss Your PCB Requirements

For a Best Technology fabrication review, send the stackup, routed tuning geometry and impedance requirements to sales@bestpcbs.com. Include both candidate layouts if you need to compare how the fabrication rules affect them.

Tags: Electrical Length Matching, PCB Meander Spacing, Serpentine Trace Delay, Trace Self Coupling
Posted in bestpcb | No Comments »

Thermal Via Spacing: When a Denser Array Helps

November 10th, 2026

Closer thermal via spacing helps only if the via barrels are a meaningful part of the heat path. Before packing more vias under a QFN pad, compare the two arrays on the same copper and stackup, check that the solder joint still forms correctly, and repeat the temperature test at the same power and airflow.

Regular via array in a bare QFN exposed-pad land — Compare actual via lands and paste windows, not just the centers. Illustrative rendering; not a production or test record.

Thermal Via Spacing

Thermal via spacing is the center-to-center distance between vias that transfer heat through the board. It does not determine temperature on its own. The pad size, via diameter and plating, copper planes, and the path from the board to air or a heatsink all matter.

Consider a hypothetical power QFN with a 3 × 3 via array. The board runs hotter than expected at a steady load. The designer wants to change only the via count. Compare that option with improving copper spreading or the board-to-heatsink interface before assuming pitch is the limiting variable.

Thermal Via Array

Compare arrays that fit in the same usable pad region. In this example, a 3 × 3 array at 1.00 mm pitch and a 4 × 4 array at about 0.667 mm pitch each span 2.00 mm between outer via centers. Neither value includes the via land radii, required edge margin or paste pattern.

Parameter	Array A	Array B
Via count	9	16
Center pitch	1.00 mm	About 0.667 mm
Outer-center span	2.00 mm	2.00 mm
Via barrel and stack	Same assumed geometry	Same assumed geometry

Overlay the copper, drill and stencil data. An array that fits by center points alone may not leave enough room for the actual lands, mask or paste windows.

Thermal Via Diameter

Distinguish the finished hole diameter from the drilled hole and pad diameter. For a simplified barrel with 0.25 mm inner diameter and 0.025 mm wall thickness, the outer barrel diameter is 0.30 mm. The land can be wider. A larger land does not add the same axial copper area as a thicker barrel.

Ask for the approved drill, plating and via construction. Via fill and surface finish also affect the assembly decision. Use the package supplier’s land and stencil guidance for the actual component instead of borrowing a via diameter from a different exposed pad.

Thermal Resistance of PCB Vias

The barrel conducts heat along its copper wall. The cross-sectional area is π ÷ 4 × (outer diameter² − inner diameter²). In the illustrative geometry it is about 0.0216 mm². Do not count the air in an open hole as solid copper.

Assume uniform copper, equal temperature at all top via ends and equal temperature at all bottom ends. This idealization lets the barrel conductances add in parallel. It does not account for how heat spreads across the pad or through the receiving plane.

Thermal Resistance Formula Conduction

For one uniform conduction path, thermal resistance is length divided by conductivity times cross-sectional area: R = L ÷ (k × A). At 1.60 mm length, an illustrative copper conductivity of 390 W/(m·K), and 0.0216 mm² of wall area, one barrel is about 190 K/W. Convert mm and mm² to meters and square meters first.

Under the equal-end-temperature assumption, nine barrels give about 21.1 K/W and sixteen give about 11.9 K/W. This is a barrel-only estimate, not a junction-to-ambient rating. If both arrays connect into a poorly spreading region, the assembled temperature difference may be much smaller.

Thermal Via Solder Wicking

Check the solderable pad before approving a denser pattern. Open holes can draw solder away from the joint. More vias can change available paste area and the joint’s void pattern. Review the package recommendation, assembly process and available via treatments together.

See the Best Technology guide to solder wicking through thermal vias for the joint-side checks. Use the agreed inspection method and joint acceptance criteria; a lower board temperature does not excuse a failed solder joint.

PCB Thermal Resistance

Interpret the temperature result as a system measurement. Hold the copper layout outside the test pad, component, board stackup, heatsink contact, airflow, ambient and actual dissipated power as constant as practical. Measure at the same defined point and after a comparable steady-state condition.

Observation	Decision
Denser array lowers temperature repeatably	Verify joint quality and final conditions
Both arrays run similarly	Investigate spreading, interface and airflow
Denser array harms the joint	Change via treatment or paste plan before release
Power or airflow changed	Repeat the controlled comparison

If the product limit is junction temperature, use an appropriate package method for estimating or measuring it. A board thermocouple at an arbitrary spot is not a direct junction measurement.

PCB mounted on a heat spreader with a temperature sensor — Fix the sensor position and thermal setup for the comparison. Illustrative rendering; not a production or test record.

Thermal Via Design Guidelines

Approve the densest pattern only if it earns its manufacturing cost and passes the real requirements. Check DFM, repeat temperature measurements at the agreed operating conditions, and verify the assembly evidence. If the gain is within measurement scatter, investigate a different bottleneck rather than declaring the denser pitch a fix.

Record via count, construction, dimensions and the validated setup. If the copper stack, heatsink interface or stencil changes later, revisit the result rather than assuming the same spacing still works.

Frequently Asked Questions

Is there one recommended spacing for thermal vias?

No universal pitch fits every package or process. Use the exact component’s land-pattern guidance, the fabricator’s approved drill and copper rules, and the assembler’s paste requirements. Check the outer via margins and then compare temperature on representative hardware before approving a denser array.

Why is the calculated resistance of one via so high?

A plated barrel has a thin conducting wall. Even though copper conducts heat well, the wall area is small relative to the length of a through-board path. Several barrels can reduce that segment’s resistance in parallel, but they do not remove the other limits in the system.

Can I use the pad diameter to calculate barrel area?

No. The pad diameter describes the copper land at a layer, not the cross section of the barrel conducting through the board. Use the wall geometry and the appropriate conductive length for that model. Model any approved conductive fill separately rather than counting the whole pad as axial copper.

Can a solid fill always be treated as copper?

No. Fill materials can have different conductivities, and some fill is used for planarization rather than as a high-conductivity path. Ask for the qualified material and construction. Use its relevant properties in the model, and keep the solderable surface requirement separate from the thermal calculation.

Should every thermal via connect to a ground plane?

Only if the package electrical requirements and board design allow that connection. The exposed pad may have a specified potential. Verify the datasheet and intended planes before adding vias. A good heat path is not acceptable if it shorts nodes or violates the component’s electrical layout rules.

What if a denser array changes the temperature only slightly?

Repeat at the same power and ambient with the same sensor placement. If the change is within normal measurement scatter, do not credit the array. Check the receiving copper, thermal interface and airflow before spending more on via count, fill or additional fabrication operations.

Can I compare an infrared reading with a thermocouple reading?

Only after accounting for what and where each instrument measures. Infrared readings depend on emissivity and spot size; a contact sensor depends on placement and attachment. Define a repeatable point and method for the comparison. Do not combine unrelated readings as if they measured the same temperature.

What should be included in a thermal via fabrication review?

Send the package land pattern, stackup, drill and finished-hole data, plating requirements, pad and stencil layout, and the planned temperature test. Identify the operating power and limit you must meet. That gives the reviewer enough context to compare array geometry with fabrication and assembly constraints.

References

Discuss Your PCB Requirements

For a Best Technology fabrication review, send the component pad drawing, candidate arrays and layer stack to sales@bestpcbs.com. Include the proposed via treatment and the temperature test conditions so the drawing review addresses the actual build.

Tags: PCB Temperature Testing, QFN Via Array, Thermal Via Spacing, Via Barrel Resistance
Posted in bestpcb | No Comments »

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