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LED MCPCB Solder-Point Temperature: Use the Right Reference

November 6th, 2026

An LED’s solder-point or sensor-pad temperature is only useful for estimating junction temperature if it is measured at the location associated with the published thermal resistance. A nearby metal-base reading is not a substitute. Match the LED part, the reference location and the supplier’s power convention before calculating the junction estimate.

Thermocouple bead near an LED reference pad
Thermocouple bead near an LED reference pad. AI-generated illustration, not a measurement or production record.

Identify the temperature reference on the drawing

Manufacturers may define a solder point, case reference, or dedicated sensor pad. Locate it in the application documentation for the exact package. Lumileds’ measurement white paper explains why the solder reference and case reference are not necessarily the same.

Record the parameters before powering the test

A measurement sheet should make the estimate repeatable.

Parameter Record Example only
LED Exact part and revision Package-specific
Reference temperature °C and sensor coordinates 68
Junction-to-reference resistance °C/W, matching definition 6
Power W on the specified basis 2
Assembly state Sink, interface and airflow Intended enclosure condition

Estimate junction temperature from the example

For the illustrative compatible values, add the product of 6 °C/W and 2 W to 68 °C. The estimate is 80 °C. The example is not a component rating, and the power term must follow the manufacturer’s convention for the published resistance.

Compare solder point, metal base and ambient

These temperatures describe different parts of the assembly.

Location Useful for Cannot replace
Specified solder or sensor point Junction estimate with matching resistance Direct junction measurement
Metal base or heat sink Comparing assembly heat paths Package-specific sensor reference
Ambient Defining external operating condition Board or package temperature

Use the supplier’s power convention

Some manufacturer methods pair their published resistance with electrical input power. Others distinguish thermal power and emitted optical power. Do not independently subtract optical power or use electrical power by default; use the convention that accompanies the exact resistance value.

Place the sensor without changing the feature

Follow the supplier’s approved sensing location and attachment method. A bead on solder mask or an adjacent pad may not read the intended reference. Keep the sensor and leads from altering electrical clearance, thermal contact or the optical path.

LED metal-core board on a heat sink at a thermal test bench
LED metal-core board on a heat sink at a thermal test bench. AI-generated illustration, not a measurement or production record.

Check how the sensor affects the reading

Lead routing, attachment and sensor contact can influence the measurement. Document placement with a photo and check repeatability across equivalent samples. If the method requires a special test board or mounting procedure, reproduce that condition instead of improvising.

Measure in the relevant assembly state

Use the specified drive, airflow, mounting and interface condition. An LED on an open bench can run at a different temperature from the installed module. Record stabilization or the required timing so short transients are not mistaken for steady operation.

Keep board comparisons on the same reference

When comparing two MCPCBs, preserve the LED package, drive and sensor location. If the mount or heat sink also changes, the result compares two complete assemblies. Use the BestPCBs MCPCB stackup guide for the separate heat-path selection question.

Interpret uncertainty before claiming margin

A small apparent temperature advantage can be less than placement or measurement variation. Repeat the test and document the resistance tolerance or typical-value limitation. Avoid reporting an estimated junction temperature with more precision than its inputs support.

Know when the estimate does not apply

Do not use a steady-state resistance calculation to interpret an arbitrary short pulse. Follow the component documentation for transient operation. If the package reference or power basis cannot be matched, report the measured temperature and the unresolved limitation separately.

Hand off the evidence with the thermal review

Keep the LED part, reference drawing, sensor photo, drive power, stabilization record and mounting details together. Send the stackup and verification requirements to Best Technology at sales@bestpcbs.com for a manufacturing review.

FAQ

Can I measure the aluminum back and call it solder-point temperature?

No. The metal back is a different location, separated by part of the heat path. Use it to evaluate the assembly or compare mounts, but apply a junction-to-solder resistance only to its specified reference. Record both temperatures separately if both are useful.

Does an infrared image replace the thermocouple method?

Not automatically. Surface emissivity, reflections and spatial resolution can influence the camera result. Use the approved method for the defined point. An image can help locate gradients but cannot be assumed to reproduce a package-specific reference reading under all surface conditions.

Can I use a resistance value from another LED in the same footprint?

Do not assume it transfers. Package internals, thermal path and reference definitions can differ even with the same footprint. Use the correct part documentation and verify any supplier-approved alternative. A similar board land pattern does not establish the same temperature estimate.

Is the calculated result an exact junction measurement?

No. It is an estimate built from the reference temperature, resistance and power convention. Its accuracy depends on the applicability of the resistance and on how the measurement was taken. Keep uncertainty and any typical-value assumptions with the reported result for review.

Should I use the maximum junction rating as the design target?

An absolute limit is not automatically an operating target. Use the device and system requirements for the expected lifetime and conditions. Compare your estimate and its uncertainty with the approved design margin rather than aiming to operate exactly at the published maximum.

Can I take a reading immediately after switch-on?

Only if the test specifically calls for that transient condition and uses the corresponding method. A steady-state estimate needs a relevant stabilized reading. Record the drive duration and response so a cold-start value is not compared with a settled installed condition.

Does a colder metal base always mean a colder junction?

Not necessarily. The difference between the junction and the base depends on the package, board and interfaces. A cooler base is useful information but does not prove the junction changed by the same amount. Compare the specified reference under matched operating conditions.

What if I cannot access the specified pad?

Document the restriction and ask for an approved alternate method or a representative test coupon. Do not silently substitute a nearby surface and keep the original resistance value. A result with an unverified reference should be labeled as such rather than used for release.

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PCB TDR Fault Distance: Convert Round-Trip Time

November 6th, 2026

On a PCB TDR reflection trace, the pulse travels to a discontinuity and back. For a uniform section, one-way distance equals propagation velocity times round-trip time divided by two. Check whether the instrument already displays one-way distance before applying the conversion, then map the result to the actual route rather than measuring across the board.

PCB transmission-line coupon connected to a test instrument
PCB transmission-line coupon connected to a test instrument. AI-generated illustration, not a measurement or production record.

Why the reflection takes a round trip

Time-domain reflectometry launches a fast change and observes the return at the measurement side. A mismatch can reflect part of that signal. The time difference from a defined reference to the reflection includes travel in both directions.

What to record with a marker

A distance is only as useful as its reference and velocity model.

Field Unit or definition Example only
Time interval ns, measured as round trip 0.80
Propagation velocity mm/ns 160
Reference plane Physical boundary Coupon input launch
Computed one-way distance mm 64
Instrument axis Time or configured distance Confirm before converting

Convert the sample reflection time

Multiply 0.80 ns by 160 mm/ns and divide by two to get 64 mm. Without the divisor you would look near 128 mm. Keysight’s TDR concepts describe round-trip reflection timing and calibration with a known line.

TDR time vs displayed distance vs TDT

First identify what the instrument marker actually reports.

Reading Meaning Conversion
Raw reflection interval Outbound and return time Multiply by velocity and divide by two
Configured TDR distance Instrument-scaled distance Verify settings; do not halve again
Through transmission delay One-way delay for a defined transmission measurement Do not use the reflection divisor

Calibrate velocity on a known route

Use a known physical length with the same relevant transmission geometry when practical. If a 40 mm reference span corresponds to 0.50 ns round trip, its inferred velocity is 160 mm/ns. Use the same reference convention when applying that value to the unknown feature.

Set the reference before interpreting the event

Decide whether your origin is the instrument port, the connector plane or the PCB trace start. The cable and launch contribute delay if they remain in the measurement. Record the calibration or fixture treatment rather than quietly assuming time zero is at the board.

PCB test coupon with a coax launch and a trace transition
PCB test coupon with a coax launch and a trace transition. AI-generated illustration, not a measurement or production record.

Map distance along the route

Use cumulative distance along the traced conductor. A via or a bend can make straight-line separation misleading. Note which layer and routing segment the candidate feature occupies and check the positions of known launch or termination events.

Use separate delays for mixed structures

A cable, microstrip and stripline need not share one velocity. Account for their segment delays or use a suitable calibrated reference. Applying a single factor to an entire mixed route may move the apparent feature even when the reflection time is correct.

Know how close two events can be

Finite effective rise time and bandwidth can make neighboring reflections overlap. An apparent peak may represent more than one feature. Do not infer a precise physical location from a cursor whose resolution exceeds the information in the measurement.

Check alternatives before naming the fault

An impedance change, connector transition, stub or termination can all create a reflection. Compare a good unit or controlled fixture and use the layout to narrow possibilities. The marker alone does not tell you whether the feature is an open, a defect or a normal transition.

Keep impedance and location separate

The reflection magnitude and inferred impedance describe the event under the test conditions. Its delay estimates where to look. Compare with the BestPCBs signal transmission guide for other channel verification tasks.

Save the setup with the result

Preserve raw data, axis settings, velocity basis, reference plane, route coordinates and candidate features. For a stackup or test coupon manufacturing review, share the files with Best Technology at sales@bestpcbs.com.

FAQ

Why is my calculated distance twice the expected value?

The marker may be showing round-trip time, and the calculation may have omitted the divisor of two. Confirm the axis and reference before changing the velocity setting. If the display is already calibrated in one-way distance, do not apply the divisor again.

Can I use the speed of light for a PCB trace?

Not as the actual line velocity unless the propagation medium and geometry support it. A PCB transmission line normally propagates more slowly. Use a measured or modeled velocity appropriate to the actual route, and label any screening assumption in the test record.

Can I use the same velocity factor on every layer?

Not without checking the construction. Different layers can have different dielectric materials, field distributions and reference structures. If the route crosses layers, evaluate each relevant segment or compare with a calibrated structure that represents the full path under the same conditions.

Is the distance the same as straight-line distance on the board?

No. It corresponds to travel along the electrical path. A serpentine can place a feature far along the route while it is physically close to the connector in a top view. Map against cumulative trace distance, including relevant transitions, instead of a ruler across the board.

Can a known cable remove all fixture effects?

A known cable can help establish timing, but launches and adapters can still contribute reflections or delay. Set the correct calibration reference and inspect a suitable reference fixture. Do not assume velocity calibration is equivalent to removing fixture mismatch or loss.

Why does a strong reflection not prove a broken trace?

A normal connector, impedance step or termination can also produce a strong return. Compare with the expected layout and a known good reference. Use additional evidence before assigning the reflection to a crack, open or manufacturing defect at the estimated location.

What if the instrument shows distance in free space?

Confirm whether the plotted axis already applies the medium velocity factor. A free-space-scaled distance is not the physical PCB distance. Follow the instrument documentation and verify with a known length before accepting a marker position as a measured route location.

Can I use the same formula for transmission delay?

Only after identifying the timing convention. Transmission from one end to the other is ordinarily a one-way measurement, so its distance relation lacks the reflection divisor. Keep the acquisition mode and reference planes in the report so the calculation is not misapplied.

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SCD21 on a PCB: Find Differential-to-Common Conversion

November 6th, 2026

SCD21 measures how much of a differential stimulus at logical port 1 emerges as common mode at logical port 2. On a PCB pair, skew, unequal losses or unequal transitions can contribute. First confirm the port mapping and fixture response; otherwise the test setup can look like a layout problem.

Differential PCB test coupon with coaxial launches
Differential PCB test coupon with coaxial launches. AI-generated illustration, not a measurement or production record.

How to read the letters and port numbers

The output mode comes first and the input mode second: C is common, D is differential. The 21 identifies output at logical port 2 with stimulus at logical port 1. Keysight’s balanced-measurement reference explains this convention.

What to capture with a plot

Record the data needed to repeat the comparison.

Parameter Unit or definition Check
Sweep Hz and points Same band and frequency grid
Logical port mapping Two conductors per end, with polarity Matches the physical fixture and file order
Reference impedances Ω, including normalization Same convention for compared traces
Calibration planes Physical locations Same fixture inclusion or removal
Reported response dB versus frequency Compare the correct term and direction

SCD21 vs SDD21 vs SDC21

These terms describe different input and output modes.

Term Input and output What it tells you
SCD21 Differential in, common out Forward differential-to-common conversion
SDD21 Differential in, differential out Forward differential transmission
SDC21 Common in, differential out Forward common-to-differential conversion

Use a skew example as a diagnostic clue

In an ideal equal-loss, uncoupled pair with otherwise identical matched paths, delay mismatch alone produces a converted magnitude of |sin(πfΔt)| relative to the incident normalized differential wave for lossless paths. At 5 GHz and 5 ps, this is about 0.0785, or −22.1 dB. This is a simplified example, not a channel acceptance limit or a way to infer skew from every measured trace.

Check unequal amplitude as well as delay

If the two paths deliver different amplitudes, they do not cancel perfectly in the common-mode sum even with equal delay. Compare individual path responses before adding length. Equal drawn trace length cannot fix a connector or launch that attenuates one conductor more.

Verify the physical port map first

Map the two conductors at each end to the analyzer’s logical pairs. A swapped port or polarity can alter the interpretation of a mixed-mode plot. Preserve the port map with the raw single-ended S-parameter file so the conversion can be repeated.

Network analyzer and a PCB coupon on a test bench
Network analyzer and a PCB coupon on a test bench. AI-generated illustration, not a measurement or production record.

Establish the fixture baseline

Compare a known balanced reference or verification coupon with the DUT. Verify repeatability and the calibration planes before attributing a conversion peak to the board. For related measurement boundaries, see the PCB fixture de-embedding guide.

Inspect asymmetry where the pair changes geometry

Compare both launches, vias, reference transitions and termination areas. For example, one conductor may encounter a different pad or return path near a layer change. Check the structure at the same point on both sides instead of assuming the straight runs are the only source.

Interpret broad trends and narrow peaks differently

A gradual increase can be consistent with simple delay mismatch over a limited band. A narrow peak may suggest a discontinuity, resonance or fixture effect. Neither shape alone identifies root cause. Compare changes between controlled layout or fixture variants.

Keep conversion and emissions evidence separate

Converted common mode can be relevant to emissions, but a conversion plot does not establish regulatory pass or fail. Coupling to cables, enclosure features and the operating stimulus also matter. Verify at the appropriate system level when emissions are the concern.

Use the product’s requirement, not a generic threshold

Set the allowable conversion over the specified band and reference planes using the actual system or interface requirement. Do not apply a rule from a different connector or application. Document the noise floor or repeatability limits near the acceptance boundary.

Deliver a reproducible comparison

Save the port map, stackup, fixture setup, raw data, conversion convention and limits with the plots. For a PCB or coupon manufacturing review, share those requirements with Best Technology at sales@bestpcbs.com.

FAQ

Does more-negative SCD21 usually mean less conversion?

Yes when comparing magnitude in dB under the same normalization and reference planes. A more-negative number represents a smaller converted wave relative to the input. Ensure the measured response is above the useful noise floor before drawing conclusions from small differences.

Can good insertion loss hide conversion?

A channel may have acceptable differential transmission and still generate common mode. Plot SDD21 and SCD21 as separate quantities across the same band. Check each against the appropriate requirement rather than relying on a single loss trace to characterize every response.

Can I read SCD21 from a single-ended two-port measurement?

Not from one ordinary two-port trace alone. The conversion depends on the responses of both conductors in each logical port under the applicable normalization. Use suitable multiport measurement data and record the port pairing and calculation convention used for the mixed-mode result.

Does zero skew guarantee zero mode conversion?

No. It removes one possible mechanism but does not eliminate amplitude imbalance or asymmetry in launches, return paths and terminations. Check the complete channel and fixture. Equal timing in one part of the path cannot establish balance at every discontinuity or frequency.

Can I use SCD21 to locate a fault by itself?

It can show where in frequency the conversion is observed, but not automatically where on the board it originates. Combine it with reference structures, controlled layout changes or suitable time-domain analysis. Verify the fixture before attributing the result to a specific feature.

Should I compare two plots with different reference planes?

Not as if they represent the same DUT. One may include a connector or launch that the other removes. Align the planes or explicitly describe the difference. Preserve the raw measurements so another engineer can reproduce the comparison under the intended convention.

Can a software port swap repair a real board problem?

It can correct a bookkeeping error if the measured ports were paired incorrectly, but it cannot change a real electromagnetic imbalance. Verify the physical assignment before reprocessing the data. If the conversion remains, check the fixture and compare equivalent features of both conductors.

Is there a universal pass limit for SCD21?

No. The acceptable magnitude depends on the interface, band and system requirement. Set the limit with defined reference planes and test conditions, and account for fixture repeatability. Do not transfer a limit from an unrelated assembly just because the two channels use similar impedance.

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PCB Shunt Thermal EMF: Find the Offset Before Blaming Gain

November 6th, 2026

A high-current PCB shunt can show an apparent current even when the load is off. Dissimilar metal junctions at different temperatures can generate a thermoelectric voltage that adds to the tiny shunt signal. Measure at a documented thermal state and separate offset, resistance drift and sense-layout errors before changing calibration.

Current shunt on a PCB with separate sense conductors
Current shunt on a PCB with separate sense conductors. AI-generated illustration, not a measurement or production record.

What thermal EMF means in the shunt path

Thermal electromotive force is a voltage caused by temperature differences in a circuit with dissimilar materials. At the differential input, the measured offset depends on how the junction contributions combine. A uniform warm board is not the same condition as unequal terminal temperatures. See Vishay’s technical note on thermal EMF for an example of a controlled terminal temperature imbalance.

Why small offsets matter

A low resistance minimizes voltage drop at high current. It also produces a small voltage per ampere. That makes a few microvolts meaningful, especially at light load or when checking the zero point just after a high-current event.

Parameters to record

Record both the electrical stimulus and thermal state.

Parameter Unit Example or record
Nominal shunt resistance μΩ 100, illustrative
Residual offset μV 5, illustrative
Sense terminal temperatures °C Both sides, and measurement locations
Applied current A Magnitude, polarity and timing
Acquisition Time and bandwidth Settling, instrument range and filter state

Convert microvolts to apparent current

For an illustrative 100 μΩ shunt, 5 μV divided by 100 μΩ equals 0.05 A. That is 50 mA of apparent current if the measurement treats all voltage as resistive drop. The values are an example, not a component accuracy specification.

Thermal EMF vs gain drift vs sense pickup

First determine how the error behaves when current or temperature changes.

Candidate Typical diagnostic clue Useful follow-up
Thermal EMF Offset changes with terminal temperature difference Observe zero as the board cools
Resistance drift Voltage-per-amp changes with thermal state Compare slope at controlled temperature
Pickup or shared copper drop Reading changes with switching or power routing Review Kelvin nodes and measure at the input

Check the two sense attachment points

Use the shunt supplier’s specified Kelvin points and take the sense conductors away from load current copper. See the four-terminal PCB sensing guide for the separate routing problem. Kelvin wiring reduces unwanted series voltage drop; it does not automatically cancel thermoelectric voltages.

Current-sense board and copper power terminals on a bench
Current-sense board and copper power terminals on a bench. AI-generated illustration, not a measurement or production record.

Find unequal heating around the terminals

Compare the two ends after the same operating event. A large bus connection, nearby switch, air jet or asymmetric copper area can affect one side more than the other. Record temperatures near the relevant junctions rather than using an unrelated board average.

Compare cold zero and post-load zero

Measure the zero-current output before and after an approved operating event. Confirm the load really is off, allow the input to settle electrically, and log the offset over time. A decaying offset that correlates with a thermal gradient is useful evidence, not proof that every microvolt comes from the shunt.

Use current reversal only on a suitable test setup

For an isolated resistive fixture where safe equal positive and negative currents are authorized, keep voltage lead orientation fixed. If offset is stable, half the difference of the signed readings estimates the resistive voltage, and half their sum estimates the offset. Do not reverse a live product or a unidirectional power stage to try this.

Know when reversal does not cancel the error

The calculation assumes the offset stays effectively constant between measurements. If the sample warms, cools or settles differently during the two readings, residual error remains. Check repeatability in the approved lab setup; do not claim the result cancels all errors.

Choose a corrective action from the evidence

If the offset follows temperature imbalance, examine junction symmetry, nearby heat sources and attachment geometry. If the problem instead follows current, confirm the resistance and placement of sense points. Test one change at a time so you can identify what improved the result.

Record the condition for the next revision

Save the stackup, shunt part, sense coordinates, load history, terminal temperatures and raw signed readings. For PCB manufacturing review, send the layout and test requirements to Best Technology at sales@bestpcbs.com.

FAQ

Does zero-current offset prove a thermoelectric problem?

No. The amplifier, ADC, wiring and external instruments can also contribute offset. Check the actual input with a suitable measurement, compare cold and warm conditions, and isolate candidate sources before assigning the entire error to a temperature difference at the shunt.

Will four-wire sensing eliminate thermal EMF?

No. Four-wire sensing separates the voltage measurement from the power leads, reducing shared resistance errors. Thermoelectric voltages along the actual sense circuit can still appear at the input. Layout and temperature symmetry remain useful even when the Kelvin connection is correct.

Can I subtract a single offset in firmware?

Only if the calibration procedure shows that the offset remains within budget across the intended thermal and operating conditions. A cold zero correction may not compensate a gradient that develops after loading. Check repeatability and temperature dependence before making a fixed correction.

How is thermal EMF different from TCR?

Thermal EMF is an additive voltage. Temperature coefficient of resistance describes how the resistance itself changes with temperature, affecting the slope of voltage versus current. Both can occur together, so compare both offset and gain under controlled conditions when diagnosing error.

Does averaging readings automatically solve this?

Ordinary averaging can reduce some noise, but it cannot remove a stable additive offset. A specific compensated procedure can help only if its assumptions hold. Save the raw readings and record the method so another engineer can verify the improvement.

Is a lower-resistance shunt always more accurate?

No. It reduces power loss for a given current but also reduces signal per ampere. The same voltage offset then represents more current error. Balance thermal limits, resolution and the low-current error budget against the full range required by the product.

Can I infer the offset from a thermal camera alone?

No. A thermal image helps locate uneven heating, but it does not measure the net thermoelectric voltage. Use the image to choose temperature and voltage measurement points, then correlate the electrical data with time and the actual thermal conditions observed.

What should I do on a system that cannot reverse current?

Do not force a reverse condition. If the approved test plan allows it, compare offset during a verified zero-current interval or use an isolated coupon and a suitable lab method. Document which contribution remains unresolved when the operating setup limits the test.

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RF PCB Phase Matching: Turn Degrees Into a Delay Budget

November 6th, 2026

Two RF paths are phase-matched when their relative phase at defined reference planes stays within a specified limit over the relevant frequency band. Start by converting the phase limit to delay at each frequency, then include routing, launches and component tolerances. Equal drawn lengths alone do not guarantee equal phase.

RF evaluation board with separate trace paths
RF evaluation board with separate trace paths. AI-generated illustration, not a measurement or production record.

What phase matching means on a PCB

Phase is position within a signal cycle, expressed in degrees. For two paths carrying the same tone, compare their phases at the chosen output references after accounting for their inputs. The requirement can be equal phase or a defined offset.

What to put in the requirement

Specify the two paths, the measurement planes and the intended frequency band before setting a length tolerance.

Field Unit or definition Example only
Test frequency GHz 6.0
Allowed relative phase error Degrees ±3
Target relative phase Degrees 0
Effective permittivity Dimensionless 3.0 for an illustrative uniform line
Reference planes Defined interfaces Input and output launch boundaries
Test state Condition and setup Same temperature and matched ports

Convert a phase limit to time

For a pure delay difference, phase magnitude in degrees is 360 times frequency in hertz times delay in seconds. At 6 GHz, 3 degrees corresponds to about 1.39 ps. This budget is for the total path difference at that frequency, not the portion reserved for PCB routing.

Estimate the corresponding routing mismatch

For an illustrative uniform line with effective permittivity 3.0, phase velocity is about 173 mm/ns. Multiplying by 0.00139 ns gives about 0.24 mm. Use that as a screening estimate only; different layers, dispersive structures or launches need a better model.

Physical length vs phase delay vs group delay

These quantities answer different questions.

Quantity What it describes What can change it
Physical length Drawn or manufactured conductor distance Routing geometry
Phase at a tone Relative angular shift at one frequency Electrical length and discontinuities
Group delay Negative slope of unwrapped phase with angular frequency Frequency-dependent behavior across the band

Why equal lengths can still differ

Different layers and reference geometries can change propagation. Different via transitions, launches or component footprints can add phase error even when the planar routes measure the same. Compare both complete signal paths, not only the longest straight traces.

Vector network analyzer beside an RF fixture
Vector network analyzer beside an RF fixture. AI-generated illustration, not a measurement or production record.

What changes across a frequency band

Pure delay produces phase error proportional to frequency. Real paths may also show phase curvature because their behavior varies with frequency. A single point inside the limit does not establish a wideband match; sweep the full requirement and use consistent phase unwrapping.

How to allocate the total budget

Keep separate allowances for the PCB routing, launches, connector or component variation and measurement uncertainty. In a worst-case budget the signed contributions can add unfavorably. Use a statistical combination only if the assumptions and evidence support it.

What the reference planes should include

A system specification may include connector phase, while a board coupon test may remove the fixture. Choose the boundary before comparing results. Keysight’s guide to network analyzer delay functions distinguishes group delay, electrical delay and port extension; record which function was used so the results are reproducible.

How to measure a path pair

Measure each path under the same calibrated setup, with stable cables and corresponding port terminations. Compare unwrapped transmission phase across the band and report the difference with the target offset. Repeat connections where fixture repeatability could consume the allowance.

What to check before adding a meander

Verify which section causes the phase difference. Adding length may help a delay mismatch, but it will not necessarily correct a frequency-dependent launch issue. Tight tuning segments can change coupling, so validate the actual routed geometry rather than adding a generic serpentine.

What to release with the PCB files

Include the frequency band, phase target and allowable error, exact layer stack, reference-plane definitions and test conditions. For context see the PCB trace length matching guide. Send fabrication and coupon requirements to Best Technology at sales@bestpcbs.com.

FAQ

Is a ±3-degree limit always equal to ±1.39 ps?

No. That conversion applies to a pure delay error at 6 GHz. At other frequencies the same phase angle corresponds to a different delay. If the limit applies across a band, perform the conversion at the relevant frequencies and check the measured response.

Do two 50-ohm traces necessarily have the same phase?

No. Impedance and propagation delay are different characteristics. Two structures may have the same nominal impedance while using different dielectric geometries or materials. Compare electrical length and the complete path response rather than treating the impedance callout as a phase requirement.

Can I use the laminate’s bulk dielectric constant directly?

Not for every line structure. A surface trace can have fields in both substrate and surrounding media. Use an effective propagation value appropriate to the line geometry and band, or a validated field solution. Label any assumed value in the calculation.

What is phase wrapping?

An instrument can display phase within a fixed angular interval, making a continuous trace jump by 360 degrees at the boundary. Apply a consistent unwrapping and reference convention before interpreting delay or comparing trends. Retain the original data for review.

Does matching at center frequency prove broadband matching?

No. Two paths can cross at one frequency and differ on either side. Compare the full specified band and inspect phase slope or ripple when needed. In a broadband design, the useful evidence is the response under the actual test conditions.

Why do repeated measurements sometimes disagree?

Cable motion, connector torque, calibration drift and fixture repeatability can change phase. Repeat the measurement with stable setup conditions and record any reconnection. If measurement variation is comparable to the allowance, improve the setup before drawing a design conclusion or changing the routing.

Can unequal line lengths produce a desired phase offset?

Yes, over a defined design range, but verify the frequency dependence. A fixed additional delay does not generally produce a constant nonzero phase across a broad band. Define whether the specification is an angle at a tone or a delay or response across a band.

Should I put the entire phase allowance into trace length?

No. The complete paths can include launches, transitions and parts, and the verification itself has uncertainty. Allocate an explicit portion to routing, then check the complete path against the requirement. Reserve margin for manufacturing and test variability supported by evidence.

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PCB Plane Cavity Resonance: Estimate the First Mode

November 6th, 2026

A power plane and its neighboring ground plane can behave like a resonant cavity. For a uniform rectangular overlap, a first screening estimate uses the electrical length of that overlap: a larger plane or higher dielectric constant moves the first mode lower. Use the estimate to identify a frequency band to investigate, not to predict the exact impedance or emissions of the assembled board.

PCB test coupon beside a vector network analyzer
PCB test coupon beside a vector network analyzer. AI-generated illustration, not a measurement or production record.

What resonates between the planes

A changing current can launch electromagnetic energy between two copper planes separated by dielectric. At certain frequencies the fields can form standing-wave patterns. A mode is one such pattern; it is not the same as saying that every point on the board has a large voltage at that frequency.

Which rectangle to measure

Use the overlap of the two planes involved, not automatically the finished board outline. A rail that occupies one portion of a larger ground plane has a smaller relevant outline. A narrow neck, cutout or divided rail can invalidate the simple rectangular approximation.

Parameters for a first estimate

Use consistent units and document what each dimension represents.

Input Example only How to use it
Overlap length a 100 mm Longer in-plane dimension
Overlap width b 60 mm Shorter in-plane dimension
Relative permittivity 4.0 Illustrative uniform value for the plane dielectric
Plane spacing Record actual spacing in mm Influences impedance and coupling; not a term in this simple in-plane frequency estimate
Mode indices m and n (1,0), (0,1) Number of half-wave variations along each axis under the model

How to calculate the first two modes

For the idealized rectangular cavity, use f(m,n) ≈ c divided by twice the square root of relative permittivity, multiplied by the square root of [(m/a)² + (n/b)²]. Use meters and c ≈ 3 × 10⁸ m/s. With the sample geometry, (1,0) is about 0.75 GHz and (0,1) about 1.25 GHz. The first nonzero estimate is lower along the longer direction. Mattey, Edwards and Hood’s cavity study compares cavity estimates with field simulation; their refined estimate includes a small fringing correction omitted in this screening calculation.

Cavity modes vs capacitor antiresonance vs fixture effects

A peak is a clue, not a diagnosis. Compare what changes the peak before changing the board.

Candidate What it follows Useful check
Plane cavity mode Overlap geometry, dielectric and position Compare predicted bands and probe at multiple locations
PDN antiresonance Interaction between capacitance and inductance in the mounted network Compare with a validated model or controlled population change
Fixture artifact Launch, cable, calibration or probe geometry Repeat with stable connections and inspect the fixture response

Why plane spacing still matters

Moving planes closer changes their distributed capacitance and impedance even when the idealized first-mode frequency expression does not contain their separation. Do not conclude that spacing is unimportant. Real dielectric structures, losses and boundary conditions can change how a resonance appears.

PCB test coupon with coaxial measurement launches
PCB test coupon with coaxial measurement launches. AI-generated illustration, not a measurement or production record.

Why the probe location changes what you see

A mode can be weak at one location and strong at another. If the predicted band appears quiet at a single port, try a second point chosen to couple to a different part of the field pattern. Document the port locations so the comparison can be repeated.

When the simple estimate stops being useful

Treat irregular shapes, multiple return planes, heavy segmentation and connected cavities as cases for a model of the actual layout. A rectangle can still identify an order of magnitude, but a precise numerical result would imply geometry the model does not contain.

How to compare an unpopulated and assembled board

Keep the same reference points and fixture when practical. The unpopulated coupon can help isolate geometry; the populated board adds decoupling, package and regulator interactions. A difference between the traces can be meaningful only when the changed conditions are recorded.

How to decide whether the mode matters

Compare the observed response with the frequency content of the excitation and with the requirements at the affected ports. A mode that is not strongly excited may be less significant than a lower-frequency impedance problem. Do not equate a simulated mode with a measured compliance failure.

What to change after identifying the mechanism

If the evidence points to the plane geometry, consider a stackup, shape or damping change supported by modeling and measurement. If the peak instead follows capacitor population or fixture changes, address that mechanism first. Review any layout change for return-path and current-delivery consequences.

What to record for the next design revision

Save the overlap geometry, dielectric assumptions, estimated mode band, port locations, raw data, populated state and the acceptance requirement. Use this with the broader PCB power-integrity workflow. For a stackup or test-coupon manufacturing review, contact Best Technology at sales@bestpcbs.com.

FAQ

Can I use the longest edge of the entire board?

Only if that dimension represents the active rectangular overlap in the model. A power island can be smaller than the overall board, and nearby splits or necks can make even its bounding rectangle misleading. Identify the two conductors and their overlap first.

Which dielectric constant should I use?

Use a documented value appropriate to the actual plane dielectric and the band of interest. For a quick calculation, label an assumed value as such. When several materials or uncertain geometry are involved, compare a bounded range or use an appropriate field model.

Is a frequency estimate enough to choose decoupling capacitors?

No. The calculation estimates where an idealized mode can occur. It does not predict the impedance at a particular device port or the effect of capacitor mounting inductance. Evaluate the actual PDN and verify the relevant band before changing the population.

Why might I see a different peak on a second port?

Different locations can couple differently to the same standing-wave pattern, and the two launches may not be identical. Compare the expected mode shapes, port definitions and fixture behavior before concluding that every observed peak represents a different physical resonance in the PCB.

Can power planes resonate when their DC voltage looks stable?

Yes. A DC reading shows the average or slow behavior at the instrument’s measurement point. A resonant response is frequency-dependent and may only be visible with suitable bandwidth and a defined excitation or measurement configuration. Record both when they answer different questions.

Does a larger board always have a lower cavity mode?

Not necessarily. The relevant dimension is the electrical length of the participating plane overlap, not simply the product outline. The dielectric and boundaries also matter. Compare like geometry and material assumptions before interpreting the direction of any frequency change between designs.

Can I identify a cavity mode from emissions alone?

An emissions peak can indicate a band worth investigating, but it does not isolate the source. Compare near-field or port evidence with geometry and known excitation, and check cables, enclosure and test fixtures before assigning the peak to the plane pair.

Is the calculated frequency a compliance limit?

No. It is a screening estimate for a simplified geometry. Compliance criteria depend on the applicable test and product requirements. Use the estimate to choose what to simulate or measure, and keep the resulting evidence separate from the calculation in the qualification report.

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DBC Copper Edge Relief: How to Check Thermal-Cycle Risk

November 6th, 2026

Copper edge relief is a local reduction of copper near a pad perimeter on a direct-bonded copper (DBC) ceramic substrate. It can reduce stress near the copper edge during temperature cycling, but it is not a universal pattern or a guaranteed life extension. Compare a relieved layout with an unrelieved control, and check that the remaining copper still meets the electrical, thermal and assembly requirements.

Patterned copper on a white ceramic substrate
Patterned copper on a white ceramic substrate. AI-generated illustration, not a measurement or production record.

Why cracks can start beside a copper pad

Copper and ceramic expand by different amounts when the temperature changes. Because they are bonded, each constrains the other, and stress can concentrate near a copper island’s perimeter. Rogers’ reliability discussion describes this mechanism in metallized ceramic substrates. It does not imply that every crack in that region has the same cause.

What edge relief changes

A relief feature changes the copper section near an edge rather than changing the whole ceramic. One supplier implementation uses shallow copper dimples near pad edges. A supplier drawing should distinguish a recess in copper from a through-hole or a gap in the electrical pattern. For the underlying construction, see this overview of DBC ceramic substrates.

Which dimensions to include in the comparison

Record the full stack and the remaining copper where the relief is deepest. There is no universal dimple size or pitch suitable for every design.

Field Unit or basis What to compare
Ceramic and thickness Grade and mm Same grade and thickness in the control and relief variant
Front and back copper Finished thickness in mm Both faces, not just the component side
Relief geometry Width, spacing and distance from edge in mm Features aligned to a documented datum
Residual copper Minimum remaining thickness in mm Section where current or spreading heat could be constrained
Temperature cycle Low and high setpoints in °C; dwell and ramp Same defined test profile for both variants
Failure criterion Agreed inspection and functional limits Same initial baseline and end criterion

Relief vs copper balance vs changing the substrate

Start with the change that addresses the observed mechanism and is feasible for the application.

Option What it changes What else to verify
Local copper edge relief Copper section near selected perimeter zones Remaining current path, inspectability and usable attach area
Copper distribution adjustment Front-to-back pattern balance Flatness, insulation spacing and whether the change alters other copper features
Different ceramic or bonding system Material and interface behavior Thermal performance, electrical isolation, supply and qualification
Unrelieved control Retains the original edge and stack Baseline against which proposed improvements are measured

How to keep relief away from the current path

Check the narrowest conducting section, not just the nominal copper thickness in the order. Imagine a power terminal feeding a copper island along one edge. Relief along the opposite unused perimeter may have a different impact from relief under the terminal feed. If the pattern intrudes into a high-current neck, check the actual remaining section before approving it. In a purely illustrative stack with 0.30 mm finished copper and a 0.08 mm recess, the nominal copper remaining at the recess bottom is 0.22 mm. Those figures are not a recommendation or a current rating; check the toleranced section and the actual current path.

How to protect the die-attach area

Keep the proposed relief separate from the die footprint and required attach land unless the assembly has been designed and qualified for that geometry. Check where heat enters the substrate and where the copper spreads it. A mechanically helpful detail can still be unacceptable if it reduces the attachment area or changes the thermal path.

Shallow recesses near the edge of a copper pattern
Shallow recesses near the edge of a copper pattern. AI-generated illustration, not a measurement or production record.

Why the back copper belongs in the drawing

Record both faces because the stress depends on the whole cross-section and pattern. A nearly solid back face and a heavily segmented front face are not equivalent to two matching patterns. Review the copper-free perimeter, alignment and flatness along with the relief itself.

How to make a meaningful test coupon

Build a control and a relief variant that differ only in the intended feature where practical. Use the same ceramic, copper construction, layout at the area of interest and relevant assembly conditions. If a supplier also changes the ceramic, the test compares two systems rather than isolating the effect of relief.

Which temperature-cycle details belong in the report

Record setpoints, dwell, ramp or transfer conditions, fixture configuration and inspection intervals. Two tests with the same cycle count can impose different stress histories. An accelerated result ranks specimens under those conditions; it does not directly predict service life.

How to tell whether an indication matters

Locate the indication relative to the die, contact pads, copper edge and insulation boundary. A scanning acoustic microscopy image can help locate internal indications on a suitable sample, but interpret it with the baseline and geometry. When the heat path is at issue, correlate the inspection result with a relevant thermal measurement.

What to review if the modified pad still cracks

Compare the failure sites across control and variant. If cracks shift rather than disappear, review ceramic edges, copper pattern balance and local geometry. If both variants fail at a similar location, check specimen preparation, attachment conditions and the proposed failure mechanism before adding more relief.

What to send for a substrate review

Provide both copper layouts, the substrate grade, nominal and minimum dimensions, attach locations, operating temperature profile and qualification criteria. For manufacturing review, send the package to Best Technology at sales@bestpcbs.com and identify the required evidence rather than requesting a generic dimple pattern.

FAQ

Does every DBC substrate need dimples?

No. The decision depends on the construction and the failure mechanism in the intended use. A supplier may use a different geometry or material strategy. Compare against a control under the same conditions rather than treating the feature as mandatory.

Are dimples the same as copper vias?

No. In this context a dimple refers to a localized recess in the copper intended to change the edge geometry. It is not a plated interconnect. Confirm the depth and residual thickness in a section drawing rather than inferring the structure from a top-view photo.

Can thermal cycling tell me how long the product will last?

Not on its own. The test compares specimens under a defined temperature history. Service conditions also involve the operating profile and the assembled module. A lifetime claim needs a justified relationship between those conditions and the observed mechanism, supported by suitable validation.

Can I transfer the same geometry from alumina DBC to another ceramic?

Do not assume it transfers unchanged. Ceramic properties, copper thickness, joining system and geometry all affect stress. Treat a substrate change as a new design input and confirm the geometry and qualification plan for that particular construction. Keep the original test result tied to its original stack.

Is a visible ceramic crack always caused by copper expansion?

No. The position can suggest a mechanism, but handling, machining, assembly and pre-existing defects also need consideration. Use baseline inspection, test history and failure analysis to separate a cycling-related change from an indication that was already present. Compare equivalent locations across samples.

Will thicker copper always be worse?

No universal rule covers every geometry and stack. Extra copper can support current and heat spreading while increasing stress in some constructions. Compare the full system under the agreed electrical, thermal and mechanical conditions rather than ranking it by one thickness.

Should I compare copper relief on both faces at the same time?

If you want to isolate the effect of relief on one face, keep the other face unchanged in the control. If both faces must change in production, a separate matched test can evaluate the combined configuration. Label the two comparisons separately in the report.

Can I approve the design using an acoustic image alone?

Use the agreed acceptance criteria. An image can locate an indication but may not quantify its electrical or thermal consequence. Keep the baseline images and correlate them with relevant measurements if the indication lies near a critical function. Record the inspection resolution and interpretation limits.

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Differential Via Antipads: Shared Oval or Separate?

November 6th, 2026

A shared oval antipad can reduce local capacitance in a differential via transition, but it also removes plane copper. Compare it with two separate openings in the actual stackup. Keep the signal pair, return vias and fabrication clearances in the model rather than enlarging the cutout by itself.

What an Antipad Does

An antipad is a clearance in copper around a feature that must not connect to that copper. At a signal via, it also changes the electrical coupling between the via and the reference plane. Texas Instruments’ differential via article discusses those effects and a shared oval example.

High-speed PCB with closely spaced via features
AI-generated illustration, not a view of a hidden antipad.

Why Two Openings Are Not the Same as One

Two separate clearances can leave a copper bridge between them. A shared opening removes that bridge and changes the field around both vias. Neither arrangement is universally better; compare the transition and surrounding reference structure.

Detailed Model Inputs

Input Unit or record Purpose
Via pitch mm Sets pair spacing
Pad and barrel Finished geometry Defines the conductor
Opening by layer Shape and dimensions Describes plane clearance
Return vias Position and reference net Represents the return path
Stub and layer pair Length and layer IDs Describes the transition

Shared Oval vs Separate Antipads

Feature Separate openings Shared opening
Plane between the vias May retain copper Removed in the shared region
Electrical review Coupling with retained bridge Coupling with common opening
Fabrication review Width and stability of copper web Clearance to nearby features

Worked Example: Check Whether a Web Remains

For two aligned circular openings of 0.45 mm diameter with centres 0.55 mm apart, their nominal edge separation is 0.10 mm. That is only the artwork value for this hypothetical case. Verify the intended finished web and tolerance or compare a shared opening instead.

Keep Both Sides of the Pair Comparable

Review symmetry around each via, the nearby reference connections and any asymmetry introduced by other routing. An electrically asymmetric environment can affect the differential transition. Do not judge the pair only by whether its two hole sizes match.

Do Not Remove Return Copper Without Checking the Path

A larger opening can clear copper around the signal vias but also reshape the nearby reference region. Review where return current can transfer between planes. If a neighbouring path becomes narrow or interrupted, assess that change as part of the same comparison.

Model the Stub and Pads With the Opening

The pad, barrel, stub and antipad contribute to one transition. A short local impedance change is not automatically attributable to the opening. Keep the geometry consistent between alternatives and use an appropriate model when the bandwidth or loss budget makes the distinction important.

Review Layer-Specific Clearance

The same opening is not necessarily appropriate on every layer. Check plane assignments, copper features and any controlled-depth operation. For the broader treatment of unused barrel, see the BestPCBs via stub guide.

Compare an Actual Test Structure

For a sensitive link, use a structure that reproduces the layer change, openings, nearby grounds and routing. A straight impedance coupon alone cannot demonstrate the transition. Agree on the test objective and how fixture effects will be interpreted.

PCB coupons near coaxial fixtures on a lab bench
AI-generated illustration of test context, not measured evidence.

Keep the Fabricator’s Clearance Rules Separate

The model answers an electrical question; the fabricator confirms which openings and copper features can be built. Check the artwork, layer-by-layer clearances and applicable tolerances. If the final geometry changes, rerun the relevant comparison before accepting the build.

Record the Selected Geometry and Evidence

Keep the via dimensions, opening shape, layer map, return arrangement and verification result together. Record why the selected option met the actual requirements. If the stackup changes, revisit the transition instead of assuming an old clearance is still appropriate.

Discuss a High-Speed Stackup

Share the layer pair and via geometry with Best Technology.

FAQ

Is a shared oval antipad always better?

No. A shared opening changes capacitance and also removes plane copper between the vias. The right choice depends on the stackup, return paths, dimensions and electrical target. Compare both options and verify the fabrication constraints instead of adopting the oval solely because a reference design used it.

What if two separate openings overlap?

Then they no longer preserve a complete web between them in the overlapping area. Review the actual resulting shape rather than treating the artwork as two independent circles. Confirm the intended clearance with the fabricator and use the correct merged geometry in any electrical model.

Is the antipad the same as the via pad?

No. The via pad is a conductor intended to connect at an applicable layer. The antipad is an opening in surrounding copper where a connection is not intended. Identify both on the relevant layer so their sizes and purposes are not accidentally swapped.

Can I enlarge the antipad to fix any impedance dip?

Not reliably. A dip can involve multiple parts of the transition, and changing the opening may affect return geometry or nearby features. Compare the suspected mechanism with a suitable model or measurement before changing the layout, and check the impact on the rest of the path.

Do return vias still matter for a differential pair?

Yes, evaluate them as part of the actual reference transition. Differential signals interact with nearby copper, and asymmetry or a reference change can matter. Confirm where the references connect and model the geometry that will be built rather than assuming the pair needs no return review.

Will a standard impedance coupon show the effect?

Only if the coupon includes a representative transition and the method can resolve it. A straight uniform trace checks a different structure. If the antipad decision is important, specify the relevant layer change and geometry and agree how the result will be interpreted.

Can different layers use different antipad shapes?

They can be designed differently when the electrical and manufacturing requirements support it. Check the relevant plane, clearance and nearby geometry on each layer. Document the actual shapes for the model and fabrication release rather than relying on a single label for the entire via.

What should I send for a transition review?

Send the stackup, via pitch, pad and barrel dimensions, layer-specific openings, return-via positions and stub details. Include the interface requirements and intended measurement or simulation scope. Those inputs let the reviewer assess the transition without guessing what the clearance drawing means.

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Metal Core PCB Isolation: Breakdown vs Hipot vs Working Voltage

November 6th, 2026

A metal core PCB can have a dielectric breakdown figure, a finished-board withstand test result and an equipment working-voltage requirement. These are not interchangeable. A report that a sample survived a specified test does not set a continuous operating rating for the assembled product.

Which Electrical Path Is Being Discussed?

On a single-sided insulated metal substrate, dielectric separates the circuit copper from the metal base. Copper-to-base isolation is different from spacing between two top-layer nets. Thermagon’s insulated metal substrate guide discusses dielectric isolation in different constructions.

Aluminum-backed board with an exposed metal edge
AI-generated illustration of construction, not an isolation-tested sample.

What Breakdown Evidence Means

A material breakdown test characterizes failure under a defined test configuration. The number depends on the specimen and method. Check whether the report measured actual breakdown or instead stopped at a leakage threshold; those observations should not be treated as identical.

Detailed Parameters to Request

Field What to record Purpose
Sample identity Material coupon or finished board Defines evidence scope
Electrode or circuit path Copper to base or another path Defines what was tested
Test type AC or DC, as specified Keeps results comparable
Condition Duration, criteria and conditioning Defines the reported outcome
Working requirement System specification Separate design input

Breakdown vs Withstand vs Working Voltage

Term What it describes What it does not prove
Breakdown Failure under the stated test Continuous use rating
Dielectric withstand Result against a specified test Long-term performance by itself
Working voltage Voltage in the intended application Which production screen applies

Example: Read a Report Without Promoting It to a Rating

Imagine a report records that a bare board passed its specified copper-to-base withstand test. That supports the sampled board or lot only as defined by the test plan. It does not establish the permissible continuous voltage after the board is mounted, wired and enclosed.

Check Whether the Material Report Matches the Build

Ask for the dielectric grade, thickness, foil construction and specimen conditions. A material coupon with generous margins can differ from a finished PCB with cutouts, edges and plated features. Keep material selection evidence separate from production acceptance evidence.

Include the Metal Base in the System Review

The equipment design determines whether the base is bonded, exposed, floating or tied to another conductive part. Identify that arrangement in the design record. Do not assume a thermal interface or mounting screw has no electrical significance.

Inspect the Edge and Mounting Geometry

The shortest relevant path may involve a board edge, fastener, cutout or exposed conductor. Ask the responsible safety engineer to evaluate the assembled geometry and applicable requirements. A laminate coupon does not represent every mechanical interface in a finished enclosure.

Keep AC and DC Results Under Their Own Methods

Different waveforms and test setups can produce different observations. Do not apply an informal conversion to replace an approved requirement. Ask for the applicable method and the actual recorded conditions rather than comparing only the largest number in volts.

Insulated metal substrate in a closed test fixture
AI-generated illustration of testing context, not a procedure or result.

Separate Thermal and Isolation Decisions

A thinner dielectric can change the thermal path, but selection still needs electrical and manufacturing verification. Compare the intended material and construction on both requirements. The BestPCBs metal core PCB resources provide a material-test example, not a working-voltage approval.

Identify Who Owns Each Acceptance Decision

The supplier can report material or board test evidence. The equipment team determines the applicable system requirements and verifies the complete build. Keep those records linked, and have qualified personnel conduct any specified high-voltage testing in an approved setup.

Record What Would Trigger a New Review

A change to the dielectric, mounting, edge clearance or electrical connection can alter what the previous evidence represents. Keep the approved construction and report together. Check whether the existing result still applies rather than inheriting it by board name.

Request a Construction Review

Share the stackup, isolation path and applicable test requirements with Best Technology.

FAQ

Can I use a breakdown figure as the working voltage?

No. Breakdown characterizes a test specimen under particular conditions. Working voltage belongs to the system design and its applicable requirements, including the assembled construction and environment. Have the responsible engineer verify the equipment instead of deriving a continuous rating from a single material number.

Does a passed hipot test show that breakdown was measured?

Not necessarily. A withstand test checks performance against a specified condition and can finish without breakdown. Read the endpoint and criteria on the report. A pass is meaningful for that test, but it is not automatically a measurement of the voltage at which failure occurs.

Is copper-to-base isolation the same as trace-to-trace spacing?

No. The first concerns the path between circuitry and the metal base; the second concerns conductors on the circuit side or elsewhere in the assembly. State the path explicitly and evaluate both where relevant. A report for one path does not establish the other.

Can I compare AC and DC figures directly?

Not without the applicable specification and method. Waveform, leakage criteria, duration and specimen arrangement affect interpretation. Keep the results identified by their original test conditions and ask the responsible engineer which evidence satisfies the requirement. Do not substitute an informal conversion for a defined test.

Does the metal base always need to be grounded?

That is a system design question, not a universal board rule. The required arrangement depends on the equipment architecture and applicable safety requirements. Record how the base is mounted or connected, and have the complete assembly reviewed instead of assuming a generic grounding scheme.

What if the coupon passes but the assembled board fails?

Check whether the two tests cover the same electrical path and geometry. The assembly can add fasteners, edges, interfaces or connections absent from a coupon. Preserve the reports and have qualified personnel investigate the difference under the approved procedure rather than repeating tests without a plan.

Does higher thermal conductivity mean better electrical isolation?

No. Thermal conductivity and isolation are separate properties, and the finished construction affects both. Compare the actual material and thickness against the thermal and electrical requirements. Do not infer a voltage rating from a thermal property or accept a thermal result as electrical evidence.

What should a supplier report identify?

Ask for the construction, sample or lot identity, test path, method, conditions, criteria and outcome. Clarify whether the evidence is from raw material, a qualification specimen or production boards. Keep it tied to the drawing and do not use it outside the scope it represents.

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Offset Stripline: Why Both Plane Spacings Matter

November 6th, 2026

An offset stripline sits closer to one reference plane than the other. Do not put the average spacing into a symmetric formula and assume the result is correct. Model both distances and verify the actual stackup and coupon before freezing the trace width.

What Makes a Stripline Offset

A stripline is a conductor embedded between two reference planes. In a symmetric geometry the trace has equal dielectric spacing to those planes; in an offset geometry it does not. Analog Devices’ layout guide explains why the dielectric dimensions matter to stripline impedance.

Multilayer PCB coupon showing copper and dielectric bands
AI-generated cutaway concept; geometry is not to scale.

Why the Total Gap Does Not Describe the Geometry

Adding the upper and lower clearances hides where the trace sits. Moving the same trace toward one plane changes the field distribution and coupling. Preserve both individual dimensions in the impedance model rather than using their sum as the only spacing input.

Detailed Stackup Inputs to Collect

Item Unit or record Purpose
Upper dielectric Finished distance in mm Describes the upper field region
Lower dielectric Finished distance in mm Describes the lower field region
Trace width and thickness Finished geometry in mm Sets conductor cross-section
Dielectric properties Model value and frequency Represents each dielectric region
Reference layers Layer IDs and net Establishes the physical structure

Symmetric vs Offset Stripline

Input Symmetric example Offset example
Upper clearance 0.15 mm 0.10 mm
Lower clearance 0.15 mm 0.20 mm
Sum of clearances 0.30 mm 0.30 mm
Model choice Symmetric geometry Preserve both distances

Worked Example: Same Sum, Different Input

The two examples in the table have the same total dielectric clearance, but the trace in the second sits 0.05 mm closer to the upper plane. Keep the copper thickness and material assumptions explicit. The example compares model inputs only; it does not predict an impedance value.

Know What the Published Formula Assumes

Analog Devices’ symmetric stripline handbook section describes a trace between equally spaced reference planes. Its symmetric expression is not a substitute for a model of an off-centre trace. Use the formula only within the geometry and assumptions it describes.

Account for Copper Thickness in the Datum

Confirm whether the two distances are measured from the trace faces, its centreline, or another reference. When using face-to-plane dielectric clearances, the complete plane separation also includes the conductor thickness. Do not add thickness twice when converting the drawing to solver inputs.

Check Which Materials Sit Above and Below

Even equal clearances do not make every electrical property symmetric if the dielectric constructions differ. Record the material on each side, along with relevant properties and frequency assumptions. The solver should represent the chosen construction rather than assuming one material throughout.

Recalculate When the Fabricator Proposes a New Stackup

A proposed replacement can keep overall board thickness while changing one of the local distances. Ask for the approved finished dimensions, re-evaluate trace width or pair spacing if needed, and check whether the existing routing still fits the required clearances.

Use a Coupon That Represents the Offset Layer

Match the routed layer, upper and lower references and relevant conductor geometry. A coupon on another layer may answer a different question. Agree on how the result will be measured and which dimensions are checked when a result falls outside its target.

PCB test coupons with visible surface routing and coaxial fixtures
AI-generated illustration of a test bench; the visible surface routing is not the buried stripline discussed here.

Check Transitions Separately

A uniform stripline model does not describe every connector or via transition. Review how reference current transfers where the route changes layers. The BestPCBs impedance control guide covers the wider stackup and test handoff.

Document Both Clearances Before Release

Record the layer pair, two dielectric distances, conductor dimensions, model assumptions and acceptance evidence. Keep the coupon associated with that revision. If the two distances are not known, leave the impedance estimate provisional rather than converting an assumed stackup into an approved requirement.

Discuss an Impedance Stackup

Send the layer map and controlled geometries to Best Technology.

FAQ

Can I use the average of the two clearances?

Not as a final model for an offset stripline. Averaging discards the location of the trace between the planes. Use the actual upper and lower distances and an appropriate model, then compare the result with representative evidence if the design requires a controlled impedance.

Does equal plane spacing guarantee equal impedance?

No. Trace position, dimensions and dielectric properties matter even when the total distance between planes is the same. Keep the individual distances in the input record. Compare complete geometries rather than using a matching total as proof that two fabricated builds are electrically equivalent.

Can the two sides use different dielectric constructions?

A stackup may have different constructions on either side, but the model and fabrication review must account for them. Record both materials and their relevant properties. Do not use a single bulk dielectric input unless that approximation is justified for the electrical requirement and confirmed where necessary.

Is offset stripline necessarily worse than symmetric stripline?

No. It is a different geometry with different constraints and can be intentional. Compare impedance, available routing and reference continuity for the actual design. A symmetric structure may simplify the initial calculation, but suitability still depends on the requirements and on what can be built consistently.

Can I keep the same trace width after a stackup change?

Only after verifying that the new geometry meets the required impedance and layout constraints. A change in either dielectric distance can matter. Recheck the model and approved construction first, and decide whether the fabrication data or artwork needs updating before placing a production order.

Does an impedance coupon verify every transition?

No. A coupon for a uniform trace does not necessarily include the vias, launches or reference changes in the actual channel. Define which structures the coupon represents and decide whether the transitions need a separate model, test structure or assembled board measurement for the application.

Do I measure spacing from the trace centre or its face?

Use the convention required by the solver or drawing and convert dimensions consistently. A face-to-plane dielectric gap is not the same as a centreline-to-plane dimension. State the convention in the handoff and account for copper thickness exactly once when combining the measurements.

What should I ask the fabricator to confirm?

Ask for the finished upper and lower spacing, copper geometry, applicable material inputs and coupon layer. Include the target impedance and tolerance. Confirm the agreed measurement method and keep the answer linked to the actual artwork and stackup revision that will be released.

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