PCB Engineering Change Order for Controlled Production Updates

September 22nd, 2026

A PCB engineering change order provides a controlled way to move an approved board change into production without mixing old and new manufacturing data. A layout update may appear straightforward, but it can also affect the Gerber or ODB++ data, fabrication drawing, BOM, centroid file, assembly drawing, test instructions, and inventory already in the supply chain. If those records do not change together, a technically correct modification can still produce the wrong PCB or PCBA.

For customers, effective change control means fewer revision-related delays, less risk of unusable inventory, and clearer evidence of what was built in each production lot. EBest Circuit supports customer-approved changes through manufacturing-data review, DFM, PCB fabrication, component sourcing, assembly, inspection, and agreed testing. Product-design approval and the final decision to release a change remain with the customer.

What Is a PCB Engineering Change Order?

A PCB engineering change order, commonly called an ECO, is the authorized record used to implement a change to a released PCB or PCBA. It identifies what must change, which product or board revision is affected, when the change becomes effective, and how existing material or work in progress should be handled.

The ECO is more than a marked-up drawing. It connects the approved engineering decision with the files and production actions needed to build the correct revision. Depending on the change, it may control:

PCB layout or circuit changes;
stackup, copper weight, material, surface finish, or controlled-impedance requirements;
component, footprint, package, or approved-alternative changes;
fabrication, assembly, inspection, programming, or test instructions;
board revision markings and product traceability;
the disposition of open purchase orders, bare PCBs, components, and assembled boards.

The term ECO is also used in PCB design software for transferring differences between a schematic and a layout. That CAD function can be one step in making a design change, but it does not replace the broader approval, document control, effectivity, and production-disposition process discussed here.

How Do an Engineering Change Request, Engineering Change Order, and Engineering Change Notice Differ?

An engineering change request proposes and evaluates a possible change. An engineering change order authorizes the detailed implementation after the technical and business impacts have been reviewed. An engineering change notice communicates the approved change to the people and suppliers who must act on it.

Record	Primary purpose	Typical status
ECR	Describe a problem or proposed improvement and evaluate its impact	Under review
ECO	Define and authorize the files, revision, effectivity, and actions required	Approved for implementation
ECN	Notify affected teams or suppliers that the approved change must be applied	Released for communication

Terminology varies among companies and quality systems. Some organizations combine ECO and ECN into one controlled record, while others use ECN as the main approval document. The abbreviation matters less than a clear workflow: the manufacturer must know which change is approved, which data set is valid, and which production units are affected.

Which Files Belong in the PCB Engineering Change Order Process?

The PCB engineering change order process should include every released record whose content or revision is affected by the change. Updating only the layout file is not enough if purchasing, assembly, inspection, or testing still uses older instructions.

The controlled package commonly includes:

native design data when it forms part of the agreed handoff;
Gerber or ODB++ files, NC drill data, and IPC-356 netlist data;
the fabrication drawing and stackup specification;
the BOM with manufacturer part numbers and approved alternatives;
the centroid, pick-and-place, or CPL file;
the assembly drawing, polarity information, and special process notes;
stencil requirements where pad or package changes affect solder-paste printing;
programming files, test procedures, fixtures, and acceptance limits when applicable;
mechanical drawings or enclosure interfaces affected by board dimensions, holes, connectors, or component height;
revision history, approval record, effectivity, and disposition instructions.

Not every ECO changes every file. A silkscreen correction may affect only a few records, while a footprint or component change may affect the BOM, land pattern, centroid data, stencil, assembly drawing, inspection criteria, and test coverage. The affected-file list should follow the actual technical impact instead of a fixed document count.

How Does an ECO Keep Gerber, BOM, CPL, and Drawings on the Same Revision?

An ECO keeps manufacturing records aligned by releasing them as one identified revision package rather than as unrelated replacement files. The package should make the relationship between the board revision, document revisions, and effective production point unambiguous.

Several controls prevent mixed-revision builds:

one approved package or controlled download location for the released files;
consistent revision identifiers across the ECO and affected documents;
a change summary that identifies superseded and replacement files;
confirmation that the BOM references footprints actually present in the released PCB data;
confirmation that CPL coordinates, rotations, and reference designators match the new assembly data;
removal or quarantine of obsolete files from active production folders;
a documented release date, lot, serial number, purchase order, or other effectivity point.

File names alone are weak revision control. A folder containing names such as “final,” “latest,” and “updated-final” does not tell fabrication, purchasing, and assembly teams which combination was approved. A defined revision package reduces clarification cycles and helps ensure that the quoted, fabricated, assembled, and inspected product refers to the same design state.

How Does Engineering Change Effectivity Control Work in Progress and Existing Inventory?

Engineering change effectivity defines when the approved change begins and which units must use it. This prevents a new revision from being applied casually to some orders while older material continues through production without an agreed decision.

The correct treatment depends on the reason for the change and the condition of existing material:

Immediate implementation: Stop affected production and apply the change before more units are built. This is appropriate when the old revision presents an unacceptable functional, safety, compliance, or assembly risk.
Rework: Modify eligible bare boards or assemblies when the rework method is approved, technically reliable, traceable, and economically justified.
Use as is: Complete or ship existing units when the previous revision remains acceptable for their intended application and the customer authorizes that disposition.
Run out existing inventory: Consume approved old-revision material before switching at a defined lot, date, or order.
Scrap or segregate: Prevent obsolete or nonconforming material from entering later production when it cannot be used or reworked safely.

This decision may affect open component orders, bare PCB stock, stencils, fixtures, work instructions, partially assembled panels, finished goods, and replacement-service inventory. Recording the disposition in the ECO lets customers understand the cost and schedule impact before the production switch is made.

When Does a PCB Change Need a New Revision or Part Number?

A PCB change normally needs a new revision when the updated board must remain distinguishable from the previously released version but still represents the same basic product. A new part number is more appropriate when the change creates a different item that must be separately ordered, stocked, serviced, qualified, or used only in specific configurations.

Revision changes often cover controlled updates such as routing corrections, approved footprint changes, documentation corrections that affect manufacturing, or component changes that preserve the product identity. A new part number may be justified when interchangeability is lost, connector pinout or mechanical fit changes, electrical function changes substantially, regulatory or customer qualification must be separated, or both versions must remain active at the same time.

There is no universal rule based only on the size of a layout edit. The customer’s configuration-management system should define the decision. From the manufacturing side, the identifier must let purchasing, production, inspection, inventory, and field support distinguish the permitted versions without relying on memory or visual guesswork.

Board markings also need deliberate treatment. If the fabrication data changes but the visible revision marking does not, the new and old bare boards may become difficult to separate. If a marking changes, the fabrication drawing and released artwork must agree on its content and location.

How Does an Approved ECO Move Into PCB and PCBA Production?

An approved ECO moves into production by converting the customer’s released change package into controlled fabrication, sourcing, assembly, inspection, and test instructions. The manufacturer should not reinterpret an unapproved concept or decide which product behavior is acceptable; its role is to implement the authorized revision consistently and identify manufacturability conflicts before material is committed.

The production transition normally follows a practical sequence:

The new package is compared with the previous released data to identify affected PCB, BOM, placement, drawing, and test records.
DFM and assembly reviews determine whether the change introduces new stackup, impedance, spacing, tooling, stencil, component, or inspection requirements.
Questions and manufacturing exceptions are resolved before release. Any manufacturer-proposed adjustment returns to the customer for approval when it changes the authorized design intent.
Effectivity and material disposition are applied to quotations, purchase orders, inventory, work in progress, and production travelers.
The correct revision is fabricated and assembled under controlled instructions.
Inspection and agreed testing verify the features affected by the change, with lot and revision records retained for traceability.

The amount of validation should match the change risk. A documentation-only correction may need a focused record review, whereas a new BGA footprint, stackup, high-current path, controlled-impedance route, or critical component may justify first-article inspection, X-ray, dimensional verification, impedance testing, electrical testing, or customer-defined functional testing. This risk-based approach avoids repeating unrelated tests while still checking what the ECO actually changed.

EBest Circuit can fabricate and assemble customer-designed PCBs and PCBAs under an approved ECO, from prototypes to repeat production. If you have a revised Gerber package, BOM, drawings, and change record, send them to sales@bestpcbs.com for DFM review and quotation. A clearly released package helps us identify affected processes early, protect the approved revision during production, and reduce preventable delays caused by mixed manufacturing data.

FAQs About PCB Engineering Change Order

Can an email replace a formal PCB ECO?

An email can communicate a request, but it may not provide adequate approval, revision, effectivity, affected-file, and disposition control. For repeatable production, the final decision should be captured in the customer’s authorized change-control record or another formally approved release method.

Does every BOM substitution require a PCB engineering change order?

Not necessarily. A previously approved alternate may be used under the customer’s existing BOM and sourcing controls. An ECO may be required when a substitute changes the footprint, ratings, function, qualification status, assembly process, inspection criteria, test result, or another released requirement. The customer’s change-control rules determine the approval path.

Can an ECO be applied after PCB fabrication has started?

Yes, but the available options become narrower and may add cost or delay. The affected work can be stopped, reworked where technically acceptable, used as is with authorization, or scrapped. The decision should consider the fabrication stage, change risk, traceability, delivery requirement, and customer approval.

Is a PCB design-tool ECO the same as a manufacturing ECO?

No. A design-tool ECO synchronizes differences between design databases, such as a schematic and PCB layout. A manufacturing ECO controls the authorized revision, affected production data, effectivity, material disposition, implementation, and verification. The CAD update may support the change, but it does not provide the complete production-control record.

What should be sent to a PCB and PCBA manufacturer after an ECO is approved?

Send the complete released manufacturing package, the approved change record or clear change summary, revision and effectivity information, material-disposition instructions, and any updated inspection or test requirements. Providing one coherent package is safer than sending individual replacement files across separate email threads.

How can customers confirm that the correct ECO revision was built?

Use board revision markings where appropriate and connect the production lot to the released data, traveler, inspection results, and agreed test records. The required evidence depends on the product and quality system, but it should allow the customer and manufacturer to identify which approved revision was used without reconstructing the history from informal messages.

A well-controlled PCB engineering change order turns an approved technical decision into a traceable production update. By aligning affected files, effectivity, inventory disposition, manufacturing instructions, and verification, customers can introduce necessary changes without losing control of which PCB or PCBA revision reaches the next build. For support implementing an approved change in prototype or repeat production, contact EBest Circuit at sales@bestpcbs.com.

Tags: Engineering Change Notice, PCB Engineering Change Order, PCB Revision Control
Posted in best pcb, bestpcb, pcb manufacturing | No Comments »

How to Export Gerber Files from KiCad for PCB Manufacturing?

September 22nd, 2026

Here is how to export Gerber files from KiCad for manufacturing: create one Gerber file for each required PCB layer and separate drill files for holes and slots. Most fabricators expect both sets in one ZIP. Gerbers without drill data omit the hole pattern, while a native KiCad board file leaves the final plot choices to someone else.

The instructions match KiCad 10 and follow the files from the saved board through GerbView and into a revision-controlled ZIP. Older releases may label the menu differently, although File > Plot opens the plotting dialog in many earlier versions.

How to export Gerber files from KiCad, PCB design layers and fabrication output on an engineering workstation

What Should You Check Before Exporting Gerber Files from KiCad?

Check the KiCad source design before creating manufacturing files. The plotter reproduces the board as it exists; it does not repair an open outline, an unconnected net, an omitted layer, or an outdated copper-zone fill. Open the final production revision in PCB Editor and save it before running the checks.

Run the Design Rules Checker: Use Inspect > Design Rules Checker and review violations, unconnected items, and schematic-to-PCB differences. Resolve real problems and document any deliberate exclusions instead of assuming the fabricator will interpret them.
Validate Edge.Cuts: Confirm that the external outline is one closed, non-self-intersecting shape and that intended internal cutouts are also closed. KiCad shades a valid closed board area and reports malformed outlines through DRC.
Confirm the copper stack: Verify the enabled copper-layer count and order in Board Setup. A 4-layer board must have the correct internal layers and stack sequence before those layers are plotted.
Review mask and silkscreen: Check mask openings around pads and make sure silkscreen text and graphics do not cover exposed solderable areas. Remove information that does not belong on the manufactured board.
Inspect drilled features: Review plated through holes, non-plated holes, slots, and mounting holes. Confirm that each feature has the intended plating property and finished purpose.
Refill copper zones: Press B or use the zone-fill command, then save the board. Enabling KiCad’s plot-time zone check provides another safeguard, but the source board should already be current.

This preflight checks the editable design. It does not replace the later Gerber review, which checks the actual files that will leave your computer.

How to Export Gerber Files from KiCad Step by Step?

Use PCB Editor to export Gerber files from KiCad into a clean revision folder, then inspect what KiCad actually wrote. Each step below keeps the output tied to the same saved board revision and ends with something you can check.

How to export Gerber files from KiCad, process from PCB Editor through separate Gerber and drill output to a verified ZIP

Open the final board in PCB Editor: Confirm the project name and revision, save the .kicad_pcb file, and make sure the canvas shows the board you intend to order.
Open the Gerber dialog: Choose File > Fabrication Outputs > Gerbers (.gbr). File > Plot opens the same dialog when Gerber is selected as the plot format. The Plot window should show the board’s enabled layer list.
Choose a dedicated output folder: Use a new folder such as fabrication/rev-b/gerber. It should not contain files from an earlier revision. The output path displayed in the dialog should point to that folder.
Select the required layers: Include every copper layer used by the design, the top and bottom solder-mask layers, any silkscreen layers that contain board markings, and Edge.Cuts. Add paste layers only when the package also serves a stencil or assembly workflow.
Set the relevant plot options: Keep the drawing sheet out of the Gerbers, keep the plot at its real scale, use a consistent origin, and enable the zone-fill check. Change compatibility options only when your manufacturer provides a requirement.
Click Plot: KiCad writes one Gerber file for each selected layer. Review the Output Messages panel and open the destination folder. You should see a fresh set whose timestamps match this export.

Do not ZIP the folder yet. First confirm the layer set, generate the drill output, and inspect both together.

Which Gerber Layers Should You Export for PCB Manufacturing?

A bare PCB package normally includes every used copper layer, both solder-mask layers, the required silkscreen layers, and Edge.Cuts. The exact count changes with the board stack and whether artwork exists on the back. The table separates bare-board files from stencil or assembly outputs.

Layer	Purpose and Export Rule
F.Cu	Front copper image; always export it when the board uses front copper.
B.Cu	Back copper image; always export it for a 2-layer or multilayer board.
In1.Cu, In2.Cu, and other internal copper	Inner signal or plane layers; export every enabled internal layer in the correct stack order.
F.Mask	Front solder-mask openings; normally required.
B.Mask	Back solder-mask openings; normally required.
F.Silkscreen	Front legend and reference markings; export when used.
B.Silkscreen	Back legend and reference markings; export when used.
Edge.Cuts	External profile and internal cutouts; required for the manufactured board shape.
F.Paste and B.Paste	Solder-paste stencil apertures; use for stencil or assembly preparation, not normally for bare-board fabrication.
F.Fab and B.Fab	Assembly and fabrication drawing detail; send separately when requested and never substitute it for copper or Edge.Cuts.

For a typical 2-layer bare board, the practical minimum is F.Cu, B.Cu, F.Mask, B.Mask, Edge.Cuts, the silkscreen layers that contain artwork, and the drill file or files. For a multilayer design, add every internal copper layer and provide the intended stackup separately so the manufacturer can map the layer order without guessing.

Which KiCad Gerber Plot Settings Matter for PCB Manufacturing?

Keep the defaults that preserve 1:1 geometry, then change only options that affect file interpretation or compatibility. KiCad exposes many plot controls because the same dialog can also create PDF, SVG, DXF, and other outputs. A Gerber handoff uses a smaller, more focused subset.

Plot drawing sheet: off: The page border and title block are document furniture, not the PCB profile. Edge.Cuts should carry the board shape.
Check zone fills before plotting: on: KiCad warns that plot output can be wrong when outdated zones are not checked and refilled.
Plot on all layers: normally empty: This feature overlays selected items onto every base layer. Use it only for a deliberate documentation requirement, not to place Edge.Cuts or silkscreen into every Gerber by habit.
Gerber X2: use when accepted: X2 adds file-function, net, and other attributes that can help CAM interpretation. Turn it off only when a manufacturer reports that its older CAM system cannot process X2.
Protel filename extensions: optional: This changes names such as .gbr to familiar extensions such as .GTL and .GBL; it does not change the board geometry. Follow the recipient’s naming preference.
Gerber job file: useful but not a replacement: A .gbrjob file can carry stackup, material, and finish metadata. Keep the ordinary layer files and fabrication notes because not every CAM flow relies on the job file.
Coordinate format: manufacturer-bound: Use the fabricator’s recommendation when one is published. Do not change precision merely because an older tutorial shows a different KiCad release.
Origin: keep it consistent: Absolute origin is a common default when the manufacturer does not specify otherwise. If you use a drill/place origin, apply the same origin to the Gerber and drill outputs.

The current option definitions and compatibility notes are documented in the KiCad 10 PCB Editor manual. A manufacturer’s written CAM requirement takes precedence over a generic screenshot.

How Do You Generate Drill Files in KiCad?

Generate the drill data separately after plotting the Gerber layers. From the Plot dialog, click Generate Drill Files, or use File > Fabrication Outputs > Drill Files (.drl). Point the drill dialog to the same revision-specific output folder and keep its origin consistent with the Gerbers.

Choose Excellon for broad compatibility: KiCad states that most PCB manufacturers require Excellon. Use Gerber X2 drill output only when the recipient explicitly accepts it.
Leave Mirror Y axis off: KiCad advises against mirroring when a third party manufactures the PCB.
Leave Minimal header off: Enable it only when the manufacturer asks for a reduced header.
Keep PTH and NPTH separate by default: KiCad normally writes plated and non-plated holes to separate Excellon files. Merge them only when the manufacturer requests a single drill file.
Keep alternate oval-hole mode off: The normal route-command representation suits most manufacturers. Use the alternate mode only for a stated CAM requirement.
Generate and inspect the output: Click Generate, confirm that the messages contain no unresolved errors, and verify that the expected .drl file or files appear with the new Gerbers.

A drill map can help a human review the hole pattern, but it does not replace the machine-readable drill file. If blind, buried, or laser-drilled vias are involved, also send the stackup and via-span requirements because a flat file list does not fully describe the fabrication sequence.

How Do You Verify KiCad Gerber and Drill Files Before Manufacturing?

Load the exported Gerber files and Excellon drill files together in GerbView and inspect the manufacturing data, not the original PCB canvas. KiCad’s Gerber Viewer lets you switch layers on and off, compare their alignment, and view drill data over the copper and outline.

How to export Gerber files from KiCad, Gerber outline copper layers and drill hits checked together before manufacturing

Load the complete export: Open all Gerber layers, then load every Excellon drill file. The correct result is one entry for every expected copper, mask, silkscreen, profile, and drill output, with no file from an older revision.
Check the board outline: Edge.Cuts should show one continuous external profile plus only the intended internal cutouts. The displayed dimensions should match the source design, without a page border or unexpected outer rectangle.
Inspect copper in stack order: Toggle each copper layer and check that its routing, pads, planes, and board position belong to that layer. A multilayer set should contain every intended copper layer once, in the expected order.
Compare mask with pads: Solder-mask openings should align with exposed pads, test points, and other intended copper. Unexpected solid mask over a pad is a reason to return to the source board.
Review silkscreen clearance: Text should remain readable, appear on the intended side, and stay off exposed pads. In the finished-board view, bottom-side text should have the expected orientation rather than looking accidentally mirrored.
Overlay drill hits: Plated holes should sit inside their pads, while non-plated mounting holes and slots should align with the outline and mechanical features. A consistent offset across the board points to mismatched origins.
Check high-risk details: Zoom into fine-pitch footprints, connector rows, mounting holes, slots, board-edge features, and dense via fields. The correct export should preserve the same clearances and feature positions you approved in the source board.

A successful Plot message proves that KiCad wrote files; it does not prove that you selected every required layer or that the output represents the intended revision. When anything looks wrong, repair the source board, delete the affected export set, regenerate Gerbers and drills together, and repeat the viewer inspection.

What Should a Complete KiCad PCB Manufacturing Package Include?

Gerber files describe layer images and board geometry, but they do not communicate every manufacturing requirement. A complete handoff combines the exact files you inspected with the construction details that a fabricator cannot safely infer from those images.

Verified Gerber set: Include the same complete layer set that you loaded and checked in GerbView, without files from another revision.
Machine-readable drill data: Include the Excellon PTH and NPTH output generated for that Gerber set. A drill map is useful for review but is not a production drill file.
Stackup and construction details: State the layer order, material, finished thickness, copper weight, and any blind, buried, laser-drilled, filled, or capped via requirements.
Fabrication notes: Specify surface finish, controlled impedance, critical tolerances, panelization, special routing, and other order-specific requirements.
Optional Gerber job file: Include the .gbrjob file when generated and accepted, but do not use it instead of the individual Gerber, drill, and fabrication files.

If the same project also includes assembly, the assembler may request a BOM, component placement file, assembly drawings, paste layers, programming data, and test instructions. Those are PCBA inputs and should not be confused with the bare-board Gerber and drill package.

How Should You Package and Send KiCad Gerber Files to a Manufacturer?

Create the ZIP from the exact folder you inspected, then keep that verified archive unchanged for upload. This simple rule prevents a late file replacement from breaking the relationship between the viewer check and the package that reaches the manufacturer.

Start from an empty revision folder: Remove or archive the previous output before plotting. Never mix a new copper layer with an old outline or drill file.
Generate Gerbers and drills in one session: Matching timestamps are not a substitute for revision control, but they make accidental carryover easier to spot.
Verify that exact set: Load the folder’s Gerbers and drills into GerbView. Do not inspect one folder and ZIP another.
Use a clear archive name: Include the project and revision, such as controller-rev-b-fab.zip, without spaces or ambiguous words such as final-final.
Attach the fabrication notes: State quantity, material, stackup, finished thickness, copper weight, surface finish, impedance requirements, tolerances, delivery location, and any special process requirement that is not unambiguously encoded in the image files.
Review the manufacturer’s preview: If the upload portal renders the ZIP, compare the outline, layer count, dimensions, and drill pattern with your verified GerbView result before placing the order.

A .kicad_pcb file can be useful for engineering discussion, but it is not a universal substitute for fabrication output. Send it only when the manufacturer accepts native KiCad data and you are comfortable sharing the editable design. Keep the approved Gerber and drill archive as the order’s controlled manufacturing package.

Which KiCad Gerber Export Mistakes Cause Manufacturing Problems?

The most consequential errors are missing outline or drill data, wrong layer selection, mixed revisions, and inconsistent origins. The first symptom usually points to a narrow check, so correct the source or export decision instead of changing unrelated settings.

Issue	Impact and First Fix
Edge.Cuts missing or open	The board outline cannot be interpreted correctly. Close the outline and re-export Edge.Cuts.
Drill files omitted	Holes and vias are missing. Generate and include the Excellon drill files.
NPTH file omitted	Mounting or tooling holes may be missing. Include the separate NPTH drill file.
Inner layer missing	Multilayer connectivity may be incorrect. Check the stackup and re-export all copper layers.
Gerber and drill origins differ	Drill hits are shifted from pads. Use the same origin for both outputs.
Mixed revisions	Layers and holes may not align. Clear the output folder and export one revision.
Wrong extra layers included	The manufacturing package becomes ambiguous. Remove unrelated paste or fabrication outputs.
Files not inspected	Missing or shifted output may go unnoticed. Verify the exported files in GerbView.

Silkscreen over exposed pads is another frequent review finding, but it is not solved by selecting more files. Correct the source artwork or use the approved silkscreen-to-mask handling, then regenerate and inspect the affected silkscreen and mask layers.

FAQs About KiCad Gerber Export

Q1: Does the .gbrjob file include the drill data?

A1: No, the .gbrjob file does not include drill data. KiCad creates it as part of the Gerber export, while hole data is generated separately. Include the Excellon .drl files even when a .gbrjob file is present.

Q2: Can a drill map replace the .drl file?

A2: A drill map cannot replace the .drl file. It is a visual aid for reviewing hole locations and tool sizes. The manufacturer still needs the machine-readable drill file, normally in Excellon format.

Q3: How should slots and internal cutouts be included?

A3: Put board cutouts on Edge.Cuts and configure slots through their pad or drill properties. Use closed shapes for cutouts and set the correct plating property for each slot. Open the Gerbers and drill files together to confirm that every routed feature is present and aligned, and follow the manufacturer’s minimum slot and routing rules.

Q4: Why does the manufacturer’s preview show a full sheet or an oversized board?

A4: A page border or stray item is probably expanding the preview. Check that Plot drawing sheet is off, Edge.Cuts contains one valid closed outer profile, and Edge.Cuts was not added to every layer through Plot on all layers. The preview should show the board outline, not a full page or an unexpected rectangle.

Q5: Can KiCad open or edit the Gerber files after export?

A5: Use GerbView to inspect Gerbers, not as a substitute for the KiCad source design. GerbView can export limited geometry to PCB Editor, but that conversion does not recreate the original netlist, footprints, constraints, or full design intent. Make changes in the .kicad_pcb source, then export a new manufacturing set.

Q6: Do Gerber files include the BOM and component placement data?

A6: Gerber files do not include the BOM or component placement data. They describe the board’s fabricated layer images. Automated assembly normally requires a BOM and a component placement or centroid file in addition to the PCB manufacturing package.

Q7: Should I use different KiCad settings for JLCPCB or another manufacturer?

A7: Follow the manufacturer’s current requirements when they differ from KiCad’s general defaults. The essential checks stay the same: export every required layer, generate the drill files separately, keep the origins consistent, and inspect the exact upload package. A board-house profile does not replace GerbView inspection or the portal preview.

A reliable KiCad handoff comes from four controls: a checked source board, a complete layer and drill export, a viewer inspection of the actual files, and separate notes for requirements that images cannot fully express. That sequence is more dependable than copying a settings screenshot from a different KiCad release or manufacturer.

Once your KiCad Gerber and drill files have been verified, send the ZIP together with your stackup, material, copper weight, surface finish, impedance requirements, quantity, and delivery requirements to sales@bestpcbs.com. EBest Circuit can review the manufacturing package before PCB fabrication and provide a quotation based on the actual board requirements.

Tags: Excellon Drill Files, Gerber File Verification, KiCad Gerber Export, PCB manufacturing files
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Flexible Printed Circuit: Materials, Types and Connections

September 22nd, 2026

A flexible printed circuit (FPC) is an electrical circuit built on a thin, bendable insulating film, usually polyimide, with patterned copper conductors. It can connect boards, carry components, or follow a three-dimensional enclosure where a rigid PCB will not fit.

Flexibility does not mean unlimited bending. A circuit folded during installation and one moving inside a hinge need different constructions. The materials, bend zone and connector ends must be designed together.

Amber flexible printed circuit with copper routing, a smooth bend and gold contact fingers

How Does a Flexible Printed Circuit Work?

An FPC carries power and signals through copper tracks just as a rigid PCB does; its thin film substrate lets those tracks follow a controlled bend. The copper is patterned into separate conductors, while insulating layers prevent contact between adjacent circuits.

A flexible printed circuit board can include pads, vias and mounted components, not just parallel wires. In a camera module, for example, one custom-shaped flex can route signals from the sensor board around a mechanical obstruction to the main board. Component locations remain supported while the connecting section bends.

What Are the Main Types of Flex Circuits?

The main constructions are single-sided, double-sided and multilayer flex; rigid-flex combines flexible interconnect sections with integrated rigid circuit sections.

Construction	Copper structure	Typical reason to choose it
Single-sided flex	One conductive layer	Simple routing with a thin bend region
Double-sided flex	Two conductive layers, usually joined by plated holes	More routing paths or a reference layer
Multilayer flex	Three or more conductive layers	Dense routing where a thicker stack is acceptable
Rigid-flex	Rigid circuit sections integrated with flex layers	Rigid component areas connected without separate cable connectors

Adding layers increases routing space but also changes bending stiffness. A multilayer design that fits a stationary enclosure is not automatically suitable for repeated movement.

Which Flexible Printed Circuit Board Material Should You Choose?

Polyimide with copper foil is a common choice for soldered FPC assemblies; the copper type, adhesive system and protective coverlay must then match the temperature and bending requirements.

Base film: polyimide provides electrical insulation and tolerates the thermal processing used for many assembled flex circuits. Polyester is an alternative for suitable lower-temperature constructions, not an automatic replacement in a reflow-soldered design.
Copper: rolled-annealed copper is commonly evaluated for repeated flexing. Electrodeposited copper is also used, but foil grade and fatigue performance matter more than the abbreviation alone.
Laminate: adhesive-based constructions bond copper to film with an adhesive layer. Adhesiveless laminates remove that separate bonding layer from the copper-to-polyimide interface, helping reduce stack thickness.
Coverlay: a protective film and adhesive cover the tracks, with openings at solder pads and contacts.

For a concrete coverlay example, DuPont Pyralux LF7001 combines 13 µm adhesive with 13 µm polyimide, while LF0110 lists 25 µm for each. These are individual coverlay constructions, not finished FPC thicknesses.

Exploded single-sided flex stack showing coverlay, coverlay adhesive, patterned copper and polyimide base

How Is an FPC Different from an FFC or a Rigid PCB?

An FPC has a custom circuit pattern, an FFC typically has parallel flat conductors, and a rigid PCB uses a substrate intended to stay rigid.

Feature	FPC	FFC	Rigid PCB
Routing	Custom tracks, branches and pads	Usually parallel conductors	Custom tracks, planes and vias
Form	Custom outline with designed bend zones	Usually a flat ribbon	Fixed board shape
Component mounting	Possible on supported areas	Usually used as an interconnect cable	Standard component platform

An FFC can be the simpler option for a straight connection between compatible sockets. Choose FPC when the circuit needs branching, an unusual outline, components or controlled routing. A flex board with a bonded stiffener is still not the same as an electrically integrated rigid-flex board.

How Do Static and Dynamic Bending Change the Design?

Static, or flex-to-install, circuits are bent into position and normally remain there; dynamic circuits must survive repeated movement without conductor fatigue.

For installation-only routing, define the formed shape, bend radius and assembly sequence. For dynamic routing, also specify the travel, cycle requirement, speed and operating environment. A hinge that passes one assembly bend has not demonstrated its service life.

Keep components, solder joints and plated holes outside the working bend zone.
Route conductors across the bend line rather than along it, and avoid abrupt changes in width.
Use smooth curves instead of creases; keep the moving section clear of sharp enclosure edges.
Evaluate the thinnest practical stack and suitable copper foil before adding layers or shielding.

Comparison of a fixed installation bend and a rolling flex loop for repeated motion

How Is the Minimum Bend Radius Determined?

The minimum bend radius comes from the complete flex stack and required bend life, not from the polyimide thickness alone. Copper, adhesive and coverlay all contribute to the thickness and strain of the bend region.

For example, our rigid-flex DFM guide gives 6× composite thickness for single- and double-sided flex sections and 12× for sections with three or more copper layers. Under that guide’s construction assumptions, a 0.10 mm section at 6× gives a 0.60 mm radius. These are design guidelines, not a guarantee for every FPC or dynamic application.

Record the approved radius on the drawing and validate the actual construction at the required motion and temperature. Changing the copper thickness, shielding or coverlay after approval can invalidate the earlier bend assessment.

How Do You Match a Flexible Printed Circuit Connector?

Match the connector’s pitch, position count, contact side and specified FPC mating thickness before finalizing the tail drawing. Matching the number of contacts alone is not enough.

For example, Hirose FH12 is an FPC/FFC connector family offering 0.5 mm and 1 mm pitches. The exact part drawing determines the contact orientation and acceptable tail dimensions; the family name is not a complete interface specification.

Contact geometry: confirm finger width, pitch, exposed length and edge-to-contact dimensions.
Mating thickness: include the circuit, bonded stiffener and adhesive at the insertion area.
Contact side: verify whether the socket contacts the upper or lower face of the inserted tail.
Retention: allow access to the latch and keep cable pull or bending loads away from the connection.

A local PCB stiffener can support the tail and establish its mating thickness. Its edge should not force bending directly beside exposed contacts or solder joints.

FPC tail, local stiffener and open ZIF connector with total mating thickness indicated

Flexible Printed Circuit Manufacturing Process

The flexible printed circuit manufacturing process patterns copper on a flexible laminate, forms any required interlayer connections, adds insulation and reinforcement, and tests the finished circuit.

Prepare the laminate: select the specified copper-clad film and prepare the panel for imaging.
Form the circuit: image and etch the copper tracks; drill and plate interconnections where the construction requires them.
Protect the conductors: align and laminate coverlay with openings for pads and contacts.
Complete exposed surfaces: apply the specified pad or contact finish and bond local stiffeners.
Profile and test: cut the outline, inspect dimensions and check electrical continuity and isolation.

The exact sequence changes with layer count, via structure and finish. The etched FPC process explains copper pattern formation in more detail. Coverlay registration and adhesive flow deserve particular attention because a partly covered contact may not mate or solder correctly.

What Changes When Components Are Assembled on Flex?

Flex assembly needs support beneath the circuit during printing, placement and soldering so the thin panel stays flat and the joints remain unloaded.

Carrier or fixture: support the panel without obstructing pads or distorting the intended outline.
Moisture control: follow the laminate and assembly process requirements before thermal exposure; do not apply one universal baking recipe.
Reflow profile: qualify the temperature profile against the solder paste, components and complete flex material system.
Inspection: check solder joints and pad alignment, then use electrical or functional testing appropriate to the assembly.

After soldering, handle the assembly by supported areas. Pulling a loose tail to lift the board can transfer force into small pads or joints even when the soldering itself was acceptable.

Where Are Flexible Printed Circuits Most Useful?

FPCs are useful where a circuit must fit a narrow three-dimensional space, connect moving sections or reduce separate wire connections.

Cameras and displays: connect modules arranged on different planes.
Wearable devices: follow compact enclosure shapes and connect small component islands.
Medical instruments: route signals through constrained assemblies with application-specific material and reliability requirements.
Battery monitoring: distribute sensing connections across a cell arrangement without treating thin sensing traces as the main power bus.
Moving mechanisms: use a qualified dynamic flex section where the motion profile suits the construction.

For a flat assembly with ample space and no movement, a rigid PCB may be easier and less expensive. FPC is valuable when its geometry solves a real packaging or interconnection problem.

FAQ About Flexible Printed Circuits

Can an FPC be stretched?

Not like an elastic band. Conventional polyimide-and-copper flex is designed to bend, not stretch freely. Stretchable electronics require different materials or conductor geometries.

Can a torn flex circuit be repaired?

Some accessible traces can be repaired in controlled rework, but a repair changes local stiffness and may not survive repeated bending. Replacement is usually more appropriate for damaged moving sections or contacts that must fit a socket precisely.

Can flex carry high-speed signals?

Yes, with a designed transmission-line structure. Specify the impedance target, reference conductors, dielectric thickness and connector transition; bending and any change from solid to hatched shielding should be included in the assessment.

Is every amber flex circuit made from the same material?

No. Color does not identify the laminate grade, copper type or adhesive. The material specification and stackup are the reliable references.

What makes a custom FPC expensive?

More layers, complex outlines, poor panel utilization, fine features, multiple stiffeners and special materials can add cost. Compare quotations using the same construction and test requirements rather than board area alone.

How Can EBest Circuit Support Your Flex Circuit Project?

At EBest Circuit, we support flexible PCB and rigid-flex projects from prototype fabrication through production and assembly. Our PCB and PCBA services date back to 2006, and we can review the circuit, component sourcing and assembly requirements together.

For your flexible circuit project, send the Gerber or ODB++ data, stackup, bend drawing, connector part number and quantity to sales@bestpcbs.com. If assembly is required, include the BOM and placement data. We will review the material construction, reinforcement and manufacturing requirements before confirming a quotation.

Tags: flexible printed circuit, flexible printed circuit board, flexible printed circuit board material, flexible printed circuit connector, flexible printed circuit manufacturing process
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IC Packaging: Structure, Materials and Assembly Process

September 22nd, 2026

IC packaging turns a fragile semiconductor die into a component that can be handled, electrically connected and mounted in an electronic product. The package provides external terminals, protects the die and creates paths for heat to leave it. It is the chip’s physical enclosure and interconnect structure—not its shipping tray or moisture-barrier bag.

A molded QFN, a wire-bonded BGA and a flip-chip processor package achieve these tasks differently. Understanding what is inside each structure helps explain its electrical behavior, thermal requirements and limits during PCB assembly.

At EBest Circuit, we support the board-level stage through our PCB assembly services, including component sourcing, incoming inspection, assembly and project-defined testing. Our engineering support connects package selection with PCB fabrication and assembly requirements; semiconductor die packaging is a separate manufacturing process.

IC packaging cutaway showing a silicon die, bond wires and protective mold compound

Key Takeaways

IC packaging protects a semiconductor die, provides external electrical connections and creates heat-transfer paths. It is different from a shipping tray or moisture-barrier bag.
Package names describe different structural features. BGA identifies the external ball array; flip chip identifies the internal die connection. A BGA is not necessarily flip chip.
Wire bonding uses fine wires from a face-up die; flip chip uses bumps beneath a face-down die. Connection density, parasitics and mechanical requirements influence the choice.
Common materials include copper leadframes, epoxy molding compounds and organic routing substrates. Not every package contains a multilayer substrate.
Packaging combines die attachment, electrical interconnection, protection and testing. Multi-die structures add integration density but also complicate thermal management and test access.
An exposed-pad QFN transfers heat into PCB copper through its die paddle and solder joint. The pad’s electrical assignment and board layout must follow the device documentation.
Board assembly needs package-specific footprint, stencil and inspection decisions. SPI checks printed paste, AOI checks visible features, and X-ray examines hidden solder connections; electrical testing checks operation.
Moisture handling and reflow limits are component-specific. Use the exact part’s moisture sensitivity label, package drawing and assembly instructions. EBest Circuit supports PCB fabrication and PCBA, not semiconductor die packaging.

What Is Inside an IC Package?

A typical molded IC package contains a semiconductor die, a die attachment layer, electrical interconnects, a leadframe or package substrate, and protective molding compound.

Die: the piece of semiconductor containing the active circuit.
Die attachment: an adhesive, solder or other qualified bonding material that secures the die to its support. The required electrical and thermal properties depend on the device.
Internal interconnects: wires, bumps or other structures that connect die pads to the package routing.
Support and routing: a metal leadframe or multilayer substrate carries connections toward the external terminals.
Protection: molding compound, a lid or another enclosure protects vulnerable structures.

A leadframe package does not need the same internal routing stack as a substrate-based BGA. A package substrate, in turn, is not the motherboard: it redistributes fine die connections to the package’s external connections. Our explanation of IC substrates and how they differ from PCBs covers that distinction.

IC Packaging Types

IC packaging types can be grouped by external terminal format, internal connection method or integration architecture. These classifications overlap: “BGA” describes the external ball array, while “flip chip” describes how the die connects inside the package.

Classification	Examples	What It Describes
External terminals	DIP, QFP, QFN, BGA	How the finished component connects to the board
Die connection	Wire bonding, flip chip	How die pads connect to package conductors
Integration architecture	Single-die package, SiP, stacked-die package	How multiple functions or dies are arranged

For example, a QFN commonly uses a copper leadframe with bottom-side lands and may include an exposed thermal pad. A flip-chip BGA instead connects the die through bumps to a routing substrate, with a separate ball array underneath for board attachment. For footprint and assembly comparisons, see our IC package types guide.

Which IC Packaging Materials Are Used?

Common IC packaging materials include copper alloys for leadframes, epoxy molding compounds for encapsulation, organic laminates for substrates, and metals such as copper, gold or aluminum for bond wires.

Material	Package Location	Primary Function
Copper alloy	Leadframe and die paddle	Electrical conduction and mechanical support
Filled epoxy molding compound	Molded body	Encapsulation and electrical insulation
Organic laminate and copper routing	Package substrate	Signal and power redistribution
Bond-wire metals	Die-to-terminal connections	Electrical interconnection
Underfill resin	Gap beneath a bumped die	Mechanical reinforcement of interconnects
Ceramic and metal lids	Selected cavity or hermetic packages	Structural support and environmental protection

Epoxy molding compound is a common IC packaging plastic material, but it is an engineered composite rather than ordinary unfilled plastic. Resin chemistry and fillers affect flow, expansion, moisture behavior and reliability. Sumitomo Bakelite’s EME encapsulants, for example, are specifically developed for semiconductor packaging.

Materials must work as a system. A low-expansion encapsulant alone cannot eliminate stress if its adhesion, curing behavior or compatibility with the die and substrate is unsuitable. The package manufacturer qualifies the complete material combination, not just one favorable property.

How Do Wire Bonding and Flip Chip Differ?

Wire bonding connects a face-up die to package terminals with fine wires; flip chip connects a face-down die through bumps directly to matching pads on a substrate or other receiving structure.

Wire bonding and flip chip compared by die orientation and internal connection method

Wire bonding accommodates many established analog, power-management and logic packages. Its wire loops introduce electrical parasitics, and the bond-pad arrangement and loop geometry constrain the layout. Wire material and bonding settings must be compatible with the die metallization.

Flip chip supports connections across the die surface rather than only along an accessible perimeter. Its shorter interconnects can reduce inductance and support dense signal and power connections.

The trade-off is additional control of bump formation, alignment, substrate routing and mechanical stress. Underfill is used in many flip-chip structures to reinforce the connection region; the exact material and application sequence depend on the package. Neither method is universally better for every IC.

IC Packaging Process

The IC packaging process typically prepares and separates wafer dies, attaches each die, forms electrical connections, protects the assembly, and tests the finished devices. A molded wire-bonded leadframe package follows the example below.

Four simplified IC packaging stages: die attach, wire bond, mold, and singulate and test

Prepare the dies: wafer-level inspection and electrical probing identify die performance before packaging; wafer preparation and dicing separate individual dies.
Attach the die: place it on the designated paddle or support using the qualified attachment process.
Form interconnects: bond wires between die pads and separate leadframe terminals.
Encapsulate: mold the body around the die and wires, then complete the required cure and finishing operations.
Separate and finish: singulate individual packages; terminal finishing or lead forming applies where the package design requires it.
Test and pack: electrically test, inspect, mark and prepare accepted devices for shipment.

The illustrations simplify these stages and are not tooling drawings. Flip-chip, cavity and wafer-level packages use different sequences; a ceramic cavity package, for instance, may require lid sealing rather than plastic molding. Process order is defined by the particular package flow.

Why Are Multiple Dies Combined in One Package?

Multiple dies are combined to integrate functions, shorten communication paths or place different semiconductor technologies in one component or module.

A system-in-package (SiP) may combine logic, memory, radio-frequency devices and passive components. It can use several interconnect and assembly technologies rather than a single universal construction.

Side-by-side integration: dies occupy neighboring locations on a common routing structure.
Stacked-die integration: dies sit above one another; their connections may use wires or other vertical interconnect structures.
Interposer-based integration: an additional fine-routing structure connects dies before signals reach the package substrate.

These arrangements increase the importance of thermal interaction, interconnect yield and testing access. A failed die or connection can affect the completed assembly. Our CoWoS-S packaging article examines one interposer-based architecture in more detail.

How Does Heat Leave an IC Package?

Heat leaves an IC through paths into the PCB, the package surface and any attached cooling hardware. In an exposed-pad QFN, an important path runs from the die through its attachment and paddle, through solder, and into PCB copper.

Simplified QFN thermal path from die through exposed pad and solder into PCB copper and thermal vias

The exposed pad needs the land pattern, solder connection and copper arrangement specified for that component. Thermal vias can connect the top land to additional copper layers. Their dimensions, filling or tenting treatment and stencil layout must also account for solder loss into holes and assembly quality.

Not every exposed pad is an interchangeable ground connection. Its electrical assignment comes from the device datasheet. Likewise, a thermal resistance value is meaningful only with its stated board and test conditions; it is not a fixed prediction of temperature on every PCB.

For a lidded processor package, heat transfer through a thermal interface material and heat spreader may be central to the cooling design. That is a different assembly from the QFN example and should not inherit its thermal-pad rules.

How Are IC Packages Tested?

IC packages undergo electrical testing to confirm device operation, while inspection and reliability qualification address assembly defects and resistance to specified stresses.

Electrical testing: checks functions and relevant parameters after assembly, using the device’s test program.
Visual and dimensional inspection: checks body condition, markings, terminal geometry and other specified characteristics.
Internal inspection: X-ray or acoustic methods may investigate hidden connections, voids or delamination, according to the inspection plan.
Reliability qualification: evaluates defined stresses such as temperature cycling or humidity exposure on the applicable qualification samples.

These checks answer different questions. Passing an electrical test does not prove that a package has no internal structural defect, and a clear X-ray image does not establish full device functionality. Burn-in and system-level testing are product-dependent, not mandatory stages for every IC.

What Can Damage an IC Package During PCB Assembly?

Moisture exposure followed by reflow, excessive temperature, electrostatic discharge and mechanical stress can damage an IC package or its internal connections.

Absorbed moisture is especially important for moisture-sensitive surface-mount components: rapid heating can generate internal pressure and contribute to cracking or delamination. The moisture sensitivity level, permitted floor life and peak package-body temperature must be taken from the component’s label and applicable handling instructions.

Before placement: confirm the exact ordering code, package drawing, moisture status and storage history.
During reflow: use a validated profile compatible with the component, solder paste and board; oven settings alone do not show the component’s actual temperature.
During handling and rework: control ESD, avoid excessive board bending, and follow the specified limits on heating and mechanical loading.

Baking is not a universal remedy to apply at an arbitrary temperature. Follow the approved recovery procedure when floor life or storage conditions have been exceeded.

What Should Be Checked Before Mounting an IC Package?

Check the exact package drawing, PCB land pattern, stencil apertures, orientation and inspection plan before releasing an IC for board assembly. A package-family name or pin count alone is not enough to approve the footprint.

Footprint: compare terminal pitch, pad dimensions, exposed-pad geometry and pin-1 location with the manufacturer’s drawing. A mismatch can produce open joints or incorrect connections even when the body fits.
Paste printing: evaluate stencil thickness and aperture geometry together. For a rectangular aperture, area ratio is L × W / [2t(L + W)], where t is stencil thickness. Reducing thickness increases this ratio but reduces theoretical paste volume; neither choice should be made from pitch alone.
Exposed pads: review aperture segmentation and thermal-via treatment to limit excess paste and solder loss into open vias. Do not apply one void-percentage limit to every QFN or power device.
Inspection: use SPI to evaluate paste height, area and volume before placement. After reflow, use AOI for accessible joints and orientation, and X-ray for hidden BGA or QFN connections. Follow with the agreed electrical or functional tests.

Our SMT stencil service supports the paste-printing stage. Send the package drawing with the PCB and assembly files so aperture and thickness choices can be reviewed together, rather than copied from a different component.

At EBest Circuit, our PCBA process includes SPI, AOI and X-ray inspection. The project’s component geometry and acceptance requirements determine the inspection plan; an X-ray image alone does not prove that a populated board functions correctly.

FAQ About IC Packaging

Is IC packaging the same as PCB assembly?
No. IC packaging builds the component around semiconductor dies. PCB assembly mounts packaged components and other parts onto a circuit board.

Does every IC package contain a substrate?
No. Many molded packages use a metal leadframe instead of a multilayer organic package substrate.

Are all BGA packages flip chip?
No. BGA describes the external solder-ball array. The die inside can use wire bonding, flip chip or another qualified interconnect arrangement.

Are plastic IC packages waterproof?
Ordinary molded plastic packages should not be treated as hermetic enclosures. Environmental suitability depends on the complete package qualification and the product’s protection measures.

Does a 3D package always use TSVs?
No. Dies can be stacked and connected with bond wires. Through-silicon vias are one possible vertical interconnect technology, not a requirement for every stacked-die package.

How Can EBest Circuit Support Your PCB Assembly?

A well-chosen IC package still needs a compatible footprint, soldering process and inspection plan. At EBest Circuit, we bring PCB fabrication, component sourcing and assembly support together so these requirements can be reviewed before your build.

Send your BOM with exact manufacturer part numbers, Gerber files, assembly drawings, quantities and test requirements to sales@bestpcbs.com. We can review your project’s PCB and assembly requirements, identify missing package information, and discuss the next steps for a quotation.

Tags: IC packaging, ic packaging materials, ic packaging plastic material, ic packaging process, ic packaging types
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Ethernet PCB Manufacturing and Assembly for Network Hardware

September 21st, 2026

An Ethernet PCB that links reliably on a laboratory bench can still become unstable in production if the fabricated stackup, connector assembly, or test method differs from the released design. Link speed, PHY interface, isolation magnetics, connector style, PoE requirements, and the enclosure all affect how the board must be laid out, fabricated, assembled, and verified.

EBest Circuit turns customer-approved schematics and component requirements into manufacturable layouts, controlled-impedance PCBs, and assembled network boards. With in-house PCB and PCBA production, 20 years of PCBA experience, and a supply network of more than 1,000 partners, we can coordinate fabrication, component sourcing, SMT and through-hole assembly, and agreed testing under one production route. To discuss an Ethernet hardware build, contact sales@bestpcbs.com.

How Link Speed Changes Ethernet PCB Requirements

Higher Ethernet speeds leave less margin for insertion loss, crosstalk, discontinuities, and timing variation. The target speed must therefore be fixed before the stackup, magnetics, connector, and test method are released.

Link speed	PCB impact	Build priority
10 / 100M	Two active MDI pairs	Correct pair geometry and matched interface parts
1G	Four bidirectional pairs	Four-pair consistency and 1G link testing
2.5G-10G	Tighter loss, crosstalk, and thermal limits	Material and stackup matched to the PHY budget

The cable-side MDI pairs are not the same as the MAC-to-PHY interface. MII, RMII, RGMII, SGMII, and other system-side interfaces use different electrical and timing rules. For example, RGMII timing depends on the selected MAC, PHY, and internal-delay settings; it should not receive a generic length-compensation rule copied from another design.

PoE adds another layer. The data rate may be correct while the board still has inadequate current capacity, magnetics rating, isolation, or thermal performance. PSE or PD role, PoE type, supply path, copper area, and expected temperature must be defined with the approved circuit.

Where Ethernet PCBs Are Used in Industrial and Embedded Equipment

Ethernet PCBs are used wherever equipment needs a stable wired link, but the board requirements change with the environment and the job performed by the port.

Industrial controllers and gateways: PLC interfaces, HMIs, remote I/O, and edge gateways may combine Ethernet with noisy power stages, long field cables, and metal enclosures. Grounding, isolation, surge protection, and connector retention become as important as the PHY itself.
Machine vision and IP cameras: A compact board may need high data throughput and PoE in the same interface. Connector position, heat around the PHY and power stage, and repeatable link testing are common production concerns.
Embedded computers and test equipment: These boards often combine Ethernet with processors, memory, USB, wireless modules, and sensitive analog sections. Placement and return-current planning must prevent one interface from disturbing another.
Switches, access points, and network appliances: Multiple ports increase pair density, power demand, connector alignment, and test coverage. The production fixture and test plan must reflect the actual port count and target speed.

Not every industrial Ethernet port uses an RJ45. Sealed M12 interfaces and single-pair Ethernet use different pin assignments, coupling arrangements, and mechanical constraints. Automotive 100BASE-T1 or 1000BASE-T1, for example, should not inherit a four-pair RJ45 layout merely because both are called Ethernet.

Ethernet PCB Layout Support Based on Customer-Approved Schematics

EBest Circuit can support PCB layout after the customer has approved the network architecture, schematic, PHY, magnetics, connector, and functional requirements. Our role is to translate those decisions into a board that can be fabricated and assembled consistently, not to replace the customer's circuit or system design authority.

Physical signal path: Place the PHY, discrete magnetics or magjack, protection parts, and connector so the MDI pairs remain short, balanced, and free of unnecessary stubs and vias.
Interface-specific routing: Apply the selected PHY's data sheet and reference design to the MDI path, while treating MII, RMII, RGMII, or serial MAC-side interfaces according to their own timing and impedance requirements. Detailed Ethernet PCB routing rules are reviewed against the actual device rather than copied as universal numbers.
Reference and isolation structure: Coordinate reference planes, isolation gaps, chassis or shield connections, and any keepout beneath magnetics with the approved safety and EMC concept.
Support circuitry: Keep the oscillator or crystal, bias resistor, decoupling network, termination, and ESD parts in the locations required by the selected components.
Manufacturing handoff: Align the net classes and critical geometry with a producible stackup, then return material or geometry changes for approval before CAM release.

The customer remains responsible for PHY and MAC selection, circuit function, firmware, system compliance, and final product validation. This boundary keeps layout support practical without allowing production changes to alter the approved design intent.

How Stackup, Materials, and Controlled Impedance Shape Ethernet PCB Manufacturing

Controlled impedance is a property of the finished stackup, not a trace-width value in isolation. Dielectric thickness and Dk, finished copper, line width and spacing, reference planes, solder mask, and etching compensation work together to produce the result.

For an Ethernet production build, EBest Circuit can support multilayer rigid PCB fabrication from 1 to 32 layers, controlled impedance, and standard or high-Tg FR-4 options; HDI or other special structures are evaluated against the released design. FR-4 is not automatically unsuitable for a faster link, but the selected material and geometry must satisfy the PHY's actual channel-loss budget.

The manufacturing sequence should remain controlled:

the customer defines the target impedance and tolerance for each applicable net class;
EBest Circuit proposes a manufacturable stackup and calculates the corresponding geometry;
the approved material family, dielectric, copper, line width, spacing, via structure, and reference planes are locked for production; and
an impedance coupon and TDR record can be supplied when included in the order requirements.

Our impedance control PCB process can verify representative fabricated geometry, but a coupon does not prove the performance of the complete assembled Ethernet channel. Magnetics, connector transitions, soldering, firmware, cable, and link partner still require the appropriate assembly or functional test.

Ethernet PCB Assembly for PHYs, Magnetics, and Network Connectors

Ethernet PCB assembly must hold both the electronic and mechanical interfaces to the released design. A board can have correct copper and still fail if a PHY has hidden-joint defects, a connector sits unevenly, or an unapproved magnetics substitute changes bandwidth, isolation, pinout, or PoE current capacity.

BOM and revision control: Source the exact approved PHY, oscillator, magnetics or magjack, connector, ESD device, bias and termination parts, and PoE components. Alternatives require engineering approval; matching only the package or nominal function is not enough.
Fine-pitch assembly: Use an appropriate stencil and reflow profile for QFN, BGA, LGA, or other bottom-terminated PHY packages. SPI, AOI, and X-ray are applied where they match the package and inspection plan.
Network connector assembly: RJ45, M12, and other ports may use SMT, through-hole, pin-in-paste, or mixed processes. The Ethernet connector PCB build must control seating height, board-edge position, shield tabs, through-hole fill, and the mechanical load transferred from the cable.
Integrated or discrete magnetics: A magjack already contains the magnetics, while other designs place a separate transformer between the PHY and connector. The assembly route and inspection points must follow the actual architecture rather than assume both parts are present.

A typical build route is approved BOM verification, solder-paste inspection, SMT placement and reflow, AOI or X-ray as required, through-hole connector assembly, cleaning, and customer-defined testing. PoE boards also need process control for higher-current paths, power devices, isolation areas, and local heat.

Ethernet PCB Inspection and Testing for Bare Boards and PCBAs

No single test proves that an Ethernet board is ready for the end product. Each stage answers a different question, so bare-board, assembly, and link evidence must not be treated as interchangeable.

Test process	Main fault found	Production role
Bare-board electrical test	Opens and shorts	Screens PCB connectivity before assembly
Coupon / TDR	Impedance deviation	Monitors stackup and trace geometry
SPI / AOI / X-ray	Paste, placement, and solder defects	Controls assembly workmanship
Defined link test	Power-up, negotiation, and packet faults	Exercises the agreed PCBA functions

These methods address different production layers: electrical testing and TDR cover the fabricated PCB, inspection controls assembly workmanship, and link testing exercises the agreed PCBA functions. EBest Circuit can run customer-defined link tests using approved firmware, fixtures, link partners, and pass/fail limits. Production testing does not replace EMC, safety, PoE, or IEEE compliance validation.

How EBest Circuit Supports Ethernet PCB Prototypes and Repeat Production

EBest Circuit uses prototype builds to establish a manufacturing baseline, then carries the approved data and process into repeat production.

Prototype build: DFM and CAM data, stackup, impedance classes, BOM, first-article inspection, and the test method are aligned before release.
Repeat orders: Gerber or ODB++, material, stackup, approved alternatives, placement data, firmware, and test revisions remain tied to the order.
Traceability: The digital shopfloor can locate material and product-batch records within five seconds when an engineer needs to investigate a component, revision, or lot.
In-house execution: PCB fabrication, sourcing, mixed SMT and through-hole assembly, and final inspection follow one coordinated production route. Prototype and small-batch builds are supported.
Quality systems: Company certifications include ISO 9001, ISO 13485, IATF 16949, and AS9100D for applicable regulated programs.

FAQs About Ethernet PCB

Does every Ethernet PCB use 100-ohm differential impedance?

Most cable-side copper Ethernet MDI pairs use the differential impedance specified by the PHY and magnetics interface, commonly 100 ohms. MAC-side interfaces, single-pair Ethernet, and vendor-specific structures may follow different requirements, so the selected device data and approved stackup remain the authority.

Can standard FR-4 support a Gigabit Ethernet PCB?

Yes, standard FR-4 is suitable for many 1G boards when the route length, stackup, geometry, and connector path stay within the PHY channel budget. Faster links or longer on-board channels may require tighter loss control or a lower-loss material.

Should the Ethernet magnetics be integrated into the RJ45 or placed separately?

Both architectures are valid. A magjack can shorten the interface path and reduce the part count, while discrete magnetics can provide more flexibility for connector choice, placement, isolation, and PoE implementation. The PCB and assembly route should follow the approved architecture and BOM.

Why can a PCB pass bare-board electrical testing but still fail Ethernet link testing?

Bare-board electrical testing finds opens and shorts; it does not exercise the assembled channel. Link failure can still come from impedance deviation, solder defects, an incorrect component, clock or power problems, PHY configuration, firmware, the connector, or the cable.

Can EBest Circuit perform Ethernet link testing before shipment?

Yes, when the firmware, fixture, link partner, target speed, active ports, and pass/fail limits are agreed before production. The test can cover power-up, link negotiation, and defined packet functions within the approved test scope.

When your schematic and interface architecture are approved, EBest Circuit can coordinate controlled-impedance PCB fabrication, sourcing, assembly, and the agreed link test. Send the released files, target quantity, and test requirements to sales@bestpcbs.com, or arrange an on-site factory audit before first articles or repeat production.

Tags: Ethernet PCB, Ethernet PCB Assembly, Ethernet PCB Layout
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Star Grounding in PCB Design: When to Use or Avoid It

September 21st, 2026

Star grounding is a targeted fix for shared-return noise, not a default PCB layout style. It helps when a known high-current or noisy load would otherwise share return copper with a sensitive circuit, and the two branches can meet at one short, controlled junction. Fast digital, RF, and widely distributed currents usually need a continuous ground plane instead.

A sound choice starts with the actual current loops: identify the disturbing current, the reference that must stay quiet, the fastest edge, and every path that can reconnect the grounds. Those four facts lead to a practical decision between a star, a plane, or a hybrid layout and define what must be measured on the prototype.

Star grounding topology with four PCB return branches meeting at one controlled point

What Is Star Grounding, and What Problem Does It Solve?

Star grounding gives selected circuits separate return branches that meet at one controlled junction. The aim is to stop current from one branch flowing through the reference used by another branch before both currents reach their common source.

The problem is common-impedance coupling. Copper, vias, connectors, and solder joints all have impedance. When two circuits share a return segment, the current from the first circuit creates a voltage across that segment:

Reference error = shared return current × shared-path impedance

Consider a 24 V control board with a solenoid and a sensor amplifier. If the solenoid and amplifier share return copper, each solenoid current step can shift the amplifier reference and appear as a false sensor signal. Separate branches can keep the solenoid current out of the measurement path until both returns reach the supply reference.

The topology is useful only when the designer can name both sides of that relationship: the current that causes the error and the reference it disturbs. A radial drawing without that explanation is not a design decision.

How Do Frequency and Return Paths Affect Star Grounding?

Low-frequency load currents may tolerate separate branches, while fast-edge currents need a short return close to the outgoing signal. This is why a star can reduce sensor-reference error yet make a clock, data bus, or switching node worse.

Nominal operating frequency is not enough. A slowly updated bus may still switch in nanoseconds, and a low-sample-rate converter may contain fast clocks. Long branches add inductance and loop area, which can increase ringing, crosstalk, emissions, and susceptibility even when their DC resistance looks acceptable.

Check three things for every important signal or load:

The complete loop: source, outgoing conductor, load, and return conductor.
The fastest transition: driver rise and fall time, switch-node edge, converter clock, or ESD event.
Return continuity: plane splits, narrow necks, missing return vias, and connector boundaries that force a detour.

If a proposed branch sends a fast return across the board before it can close, use a nearby plane for that loop. The same PCB can still use a dedicated branch for a compact low-frequency load return.

When Does Star Grounding Work Well?

Star grounding works well when one identifiable load threatens one identifiable reference and both branches can reach a compact junction. The following conditions should all be true:

The disturbing current is known. Typical sources include a relay, motor, solenoid, heater, lamp, or power-output stage.
The sensitive reference is known. It may belong to a sensor, precision reference, measurement shunt, low-level audio input, or feedback network.
The junction is physically close. A supply return, bulk-capacitor return, regulator return, or connector boundary can accept the branches without long radial routing.
Fast local loops stay local. Decoupling, clocks, interfaces, and switching loops still close through a nearby plane or tightly coupled conductor pair.

On the control-board example, the solenoid can return directly to the power-entry capacitor while the sensor branch reaches the same reference on separate copper. The ADC and microcontroller interface can remain over continuous ground. This is a hybrid solution driven by current paths, not by the labels “analog” and “digital.”

When Should You Avoid Star Grounding and Use a Ground Plane Instead?

Avoid a whole-board star when fast signals, RF energy, dense routing, or distributed loads need many short return paths. Start with a continuous ground plane for most multilayer digital boards, then add a controlled junction only where a specific noisy branch must be kept out of a sensitive region.

Engineering comparison of star, continuous ground plane, and hybrid PCB return topologies

Board condition	Starting topology	What to verify
One compact low-frequency load beside a sensitive reference	Star or Kelvin return	Measure reference movement during the worst load step.
Clocks, fast buses, RF traces, or rapid converter interfaces	Continuous ground plane	Keep an adjacent return path beneath the complete signal route.
Fast local interfaces beside a noisy power section	Hybrid	Keep fast returns on the plane and control where the power return joins it.
Loads spread across a large board	Plane or region-based power return	Calculate voltage differences using the actual routing length and current.
Several boards, cables, shields, or conductive mounts	System-level grounding plan	Trace every connection that can create a parallel return path.

A layout should be judged by return-current behavior rather than visual symmetry. A neat radial pattern can create a large high-frequency loop, while careful placement over a solid plane can keep a noisy load current away from a measurement circuit.

Where Should the Star Ground Point Be Placed?

Place the star point where the selected branch currents return to their shared source without crossing another branch’s reference first. That point is often near a bulk capacitor, regulator return, supply connector, or measurement shunt, not at the geometric center of the PCB.

Engineering comparison of incorrect shared return routing and a controlled star point near the supply return

Mark the sources and loads. Include connectors, regulators, bulk capacitors, switching stages, sensors, converters, and external cables.
Draw outgoing and return current together. Check steady load, the worst load step, and the fastest transition because the paths may differ.
Locate the protected reference. Identify the exact point where the sensor, amplifier, ADC reference, or feedback network measures voltage.
Join the branches after their local reference points. The noisy current should reach the shared source without using the sensitive branch’s copper.

A net tie or zero-ohm resistor can make the chosen junction visible in the schematic and testable on the board. It cannot correct long branches or poor placement. Choose the electrical location first, then use the component or copper feature to enforce it.

How Should Analog, Digital, Power, and Chassis Grounds Meet?

Connect ground regions according to the currents they carry and the reference required by signals that cross between them. The names AGND, DGND, PGND, and chassis ground describe roles; they do not automatically require separate copper planes.

Analog return: keep load and switching current away from low-level inputs, references, and feedback nodes.
Digital return: give clocks and interfaces a short path beside their signal traces, even when average current is small.
Power return: contain converter hot loops, motor current, and gate-drive current near their sources and local capacitors.
Chassis, shield, and protective earth: route ESD, common-mode, shield, and safety current at the connector or enclosure boundary without sending it through a sensitive reference.

For a mixed-signal IC, follow the device data sheet and reference layout before splitting ground. AGND and DGND pins may describe internal circuit functions rather than a requirement for two board planes. The relevant questions are where the pin currents flow and what reference the crossing signals use.

Also trace paths outside the PCB. A cable shield, metal standoff, programming lead, or oscilloscope earth connection can bypass the intended junction. A board-level star is valid only if the assembled system preserves it.

What Layout Mistakes Make Star Grounding Fail?

Star grounding fails when the copper, components, or external connections create a different current path from the one shown on the schematic. These mistakes are the first places to look when the expected noise reduction does not appear:

The junction is beyond the sensitive reference. The noisy current crosses the measurement reference before reaching the star. Move the junction or change placement.
The branches are too long. A branch with acceptable DC resistance can still have excessive inductance. Keep fast returns on a plane.
A signal crosses a split or narrow ground neck. The return detours around the gap. Reroute the signal or restore continuous ground beneath it.
A second connection bypasses the star. Noise changes when a cable, enclosure, debugger, or instrument is attached. Trace current through the complete test setup.
Decoupling current travels to a remote junction. The IC supply loop becomes larger than necessary. Close each high-frequency decoupling loop locally.
A bead or zero-ohm link replaces analysis. The fitted part adds impedance but does not define the current path. Select it only after the target current and allowed voltage difference are known.

Change one path at a time during troubleshooting. Switch the suspected load while monitoring the protected reference, then repeat with the enclosure and external cables connected. The difference separates shared-copper error from a secondary path or radiated-coupling problem.

How Can You Review and Test a Star Ground Design?

A star-ground design is ready when the current-path drawing, physical junction, and measured result agree with one defined acceptance limit. Six checks provide that evidence:

Draw the critical loops. Mark the source, outgoing path, load, return, and local decoupling loop for each noisy, fast, or sensitive circuit.
Name the coupling. Record the aggressor current, shared path, victim reference, operating condition, and maximum acceptable error.
Compare the drawing with the PCB. Check branch length, plane continuity, layer changes, connectors, shields, mounts, and the exact junction feature.
Estimate the low-frequency error. Calculate shared resistance and voltage drop at maximum load and compare the result with the allowed reference shift.
Measure the load event. Compare idle and worst-load conditions with a short-ground-spring probe or an appropriate differential probe. Save the waveform that occurs at the same time as the disturbing event.
Repeat the test on the assembled system. Add the enclosure, shields, cables, debugger, and representative external equipment so hidden return paths are included.

The result should lead to one decision. Keep the star if the protected reference stays within its limit and fast local returns remain continuous. Use a plane or hybrid if fast or distributed currents need a nearby reference. Change the architecture if the current paths or acceptance limit are still unclear.

FAQs About Star Grounding

Q1: Should each star-ground branch use a separate schematic net name?

A1: Use separate net names when they help the CAD tools enforce the intended connection. Join them with a documented net tie or approved junction footprint, then confirm that the PCB netlist and copper contain no unintended second connection.

Q2: How wide should a star-ground branch be?

A2: Size it from current, allowable voltage drop, temperature rise, and transient behavior. There is no universal width. A high-current branch may need wide copper, while a sensing branch may need a separate Kelvin path that carries almost no load current.

Q3: Can a ground pour surround star-ground branches?

A3: Yes, but the pour must not create a parallel connection between branches. Use clearances or a controlled net-tie strategy, then inspect the final Gerber data and connectivity report rather than relying on the schematic alone.

Q4: Can several regulators share one star point?

A4: They can when their return currents meet at a low-impedance source node without modulating another regulator’s reference. If one converter has large switching or load-step current, give it a local hot loop and check whether a higher-level junction is needed.

Q5: How should star-ground noise be measured with an oscilloscope?

A5: Measure between the protected reference and its source reference during the suspected load event. Use a short ground spring or a suitable differential probe; a long probe ground lead can create a loop and show noise that is not present at the circuit node.

Conclusion: Choose the Grounding Topology from the Current Loops

Choose a star only for a specific shared-impedance problem that has short branches, a clear victim reference, and one practical convergence point. Choose a continuous plane when fast or distributed currents need nearby returns. Use a hybrid when those two needs exist on the same board.

The next design review should produce two items: an annotated drawing of the critical current loops and a measurement plan for the worst load event. If both are specific, the topology choice can be checked. If either remains vague, deciding between star grounding and a ground plane is premature.

Tags: ground plane design, mixed-signal PCB, PCB grounding, PCB return current, star grounding
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CoWoS-L Explained: RDL and LSI for Larger AI Packages

September 21st, 2026

CoWoS-L combines a redistribution-layer (RDL) interposer with local silicon interconnects (LSI). The RDL spans the larger routing platform; embedded silicon bridges provide dense links at selected die interfaces. This division helps integrate more logic and high-bandwidth memory without using one continuous silicon interposer across the full area.

Conceptual CoWoS-L package with embedded local silicon interconnects

What Is CoWoS-L Packaging?

CoWoS-L packaging is TSMC’s CoWoS architecture that embeds local silicon interconnects within an RDL-based interposer for large multi-die computing packages.

A CoWoS-L cross section contains logic dies and HBM at the top, an interposer incorporating RDL and local silicon beneath them, and a separate package substrate below. RDL means redistribution layer: patterned conductors redistribute connections across the platform. LSI means local silicon interconnect: dense silicon-based routing placed where neighboring die interfaces need it.

Calling this only an “organic interposer” misses the embedded silicon and molded integration structure. It is not silicon-free, and its package substrate is not the system PCB. For the foundry context, see our introduction to TSMC’s manufacturing technologies.

How Do RDL and LSI Work Together in CoWoS-L?

LSI handles dense local die-to-die connections, while RDL distributes connections over the wider interposer footprint.

Local die-to-die signal path within the silicon bridge above wider RDL routing

Structure	Location	Interconnect role
LSI	Selected neighboring die interfaces	High-density local links using fine silicon-based wiring
RDL	Across the wider interposer	Broader redistribution and integration with the embedded structures
Package substrate	Below the interposer	Connections toward the finished component’s board interface

TSMC describes CoWoS-L LSI with multiple layers of submicron copper wiring and connections including SoC-to-SoC, SoC-to-chiplet, and SoC-to-HBM. The bridge occupies the region serving those interfaces; it is not simply a small silicon support underneath an arbitrary part of the package.

Consider two logic dies whose high-density interfaces face each other. An LSI region can connect those edges while the wider RDL carries other connections. Rotating one die may move its interface away from the intended landing region, forcing changes to bridge position and routing. Die orientation and LSI placement must therefore be co-designed.

The bridge does not generate bandwidth by itself. Link width, signaling rate, electrical characteristics, and the transmitting and receiving circuits still determine usable throughput.

Why Can CoWoS-L Support Larger Packages?

CoWoS-L extends the interposer footprint through a wider RDL platform while concentrating fine silicon routing at local interfaces, instead of enlarging one continuous silicon interposer everywhere.

TSMC’s public overview identifies a 3.5-reticle CoWoS-L generation that entered production in 2024. This is a dated technology generation, not a permanent maximum. Reticle multiples describe interposer scale relative to an exposure field; they do not specify the component’s outer dimensions, BGA pitch, or HBM count.

More placement area: the platform can accommodate additional or larger logic and memory components when supported by the package design.
Localized fine wiring: high-density silicon regions follow the die interfaces rather than covering the entire footprint.
Separate size limits: interposer area, package substrate outline, and cooling assembly envelope remain different dimensions.

Larger still means more manufacturing coordination. Mold, copper, silicon, and the organic substrate respond differently to temperature. Warpage, interconnect stress, routing yield, and cooling all require qualification. Less full-area silicon does not prove that every CoWoS-L product is cheaper than a CoWoS-S alternative.

How Is a CoWoS-L Package Manufactured?

The CoWoS-L process flow integrates local silicon interconnects into a molded RDL platform, attaches the top dies, and completes the assembly on a package substrate.

Plan the floorplan: align SoC, chiplet, and HBM interface locations with the required LSI regions and reserve power-routing space.
Integrate the embedded structures: incorporate the local silicon elements, and applicable embedded passive components, into the reconstituted interposer structure.
Form the RDL connections: create the redistribution wiring that connects the embedded regions and wider package interfaces.
Attach the top dies: TSMC describes a chip-last approach in which the interposer platform is prepared before top-chip assembly.
Complete substrate integration and verification: assemble the package substrate and thermal structure and verify links, power behavior, and reliability.

CoWoS-L functional stages from floorplan through assembly and verification

Critical controls include embedded-element position, RDL registration, surface planarity, and joint formation. A displaced bridge or a local height error can compromise the fine die interface even if the overall package outline is correct.

This sequence describes functional stages, not a proprietary process recipe. Exact mold materials, bonding temperatures, tolerances, and inspection acceptance criteria must come from the qualified package process.

How Does CoWoS-L Support Power Delivery?

CoWoS-L supports power delivery through its interconnect network and the integration of stand-alone embedded deep trench capacitors (eDTCs) beneath the SoC.

Embedded eDTC beneath the SoC within the RDL interposer above a separate package substrate

TSMC identifies this eDTC integration in its official CoWoS technology overview. Placing capacitance near the load can shorten the local current loop and reduce the inductive penalty of supplying rapid current changes. The benefit depends on the actual connection geometry, capacitor characteristics, and complete power network.

Local transient support: nearby capacitance supplies part of a fast current demand before more distant supply paths respond.
Power-path coordination: package conductors, board planes, capacitors, and voltage regulators must meet the device’s supply limits together.
Impedance control: capacitance and interconnect inductance can create resonances, so adding capacitance is not automatically an improvement at every frequency.

For an illustrative target, a permitted 30 mV voltage change during a 100 A current step gives Z = ΔV/ΔI = 0.3 mΩ. These are example inputs, not a CoWoS-L rating. A real design needs its own tolerance and frequency-dependent package, board, and regulator models.

Where Is CoWoS-L Packaging Used?

CoWoS-L is used for large AI and HPC packages that need dense local connections among logic dies, chiplets, and HBM on a larger interposer platform.

Multi-die AI accelerators: local bridges connect the compute interfaces, while the wider floorplan accommodates logic and memory integration.
HBM-based computing packages: SoC-to-HBM connections combine local routing density with space for the required memory arrangement.
Chiplet-based HPC designs: dense connections between selected chiplets support integration without making every part of the routing platform silicon.

TSMC’s disclosed SoC-to-SoC, SoC-to-chiplet, and SoC-to-HBM connection forms support these application categories. They are not a claim that every chiplet processor or AI accelerator uses CoWoS-L. Naming a particular product requires a disclosed packaging variant, not an inference from its HBM count or performance.

What PCB Assembly Checks Matter for CoWoS-L Packages?

PCB assembly checks must follow the specific finished component or module’s land pattern, handling limits, reflow instructions, warpage requirements, and thermal-mechanical design.

Board interface: confirm whether the delivered item is a directly soldered component or a module with its own board/connector interface.
Land pattern and escape routing: use the released ball map and pad geometry; LSI dimensions do not become PCB trace dimensions.
Moisture handling and reflow: use the device’s specified storage, exposure, and thermal-profile limits, not a generic “CoWoS-L temperature.”
Coplanarity and support: review the component’s allowed deformation, board support, heatsink loads, and attachment keep-outs.
Inspection and testing: agree on accessible joint-inspection methods and electrical or functional tests appropriate to the assembly. Visual inspection alone cannot verify hidden BGA joints.

Our advanced HDI PCB guide covers board-level routing options. At EBest Circuit, we review PCB fabrication and PCBA requirements against the actual design and component documentation—not the interposer’s marketing dimensions. Send your Gerber files, stackup, BOM, quantities, and component assembly specifications to sales@bestpcbs.com. This board-level support is separate from TSMC’s CoWoS-L package manufacturing.

FAQs About CoWoS-L

Does CoWoS-L eliminate silicon?

No. It retains silicon in local interconnect regions. The wider RDL platform changes where silicon is used, not whether silicon is present.

Is LSI another processor?

No. In CoWoS-L, LSI is a local silicon interconnect structure that routes signals between die interfaces; it is not an additional computing die.

Is one LSI bridge enough for every package?

Not necessarily. The number and location of bridges follow the interfaces being connected. Multiple logic dies and HBM stacks can require several local regions.

Does an embedded eDTC replace PCB decoupling?

No. Embedded capacitance supports part of the local supply network. Board capacitors and the voltage regulator must still satisfy the component’s wider power-delivery requirements.

Is 3.5 reticles the maximum CoWoS-L size?

No. It identifies a published production generation rather than a permanent ceiling. Obtain the qualified dimensions and availability for the intended design instead of treating a roadmap target as a released package.

Tags: CoWoS-L, cowos-l cross section, cowos-l lsi, cowos-l packaging, cowos-l process flow
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CoWoS-S Packaging: Silicon Interposers for AI and HPC

September 21st, 2026

CoWoS-S packaging places logic dies and high-bandwidth memory (HBM) side by side on a silicon interposer. Fine metal wiring connects the dies across that interposer, while through-silicon vias connect it vertically to a separate package substrate. This arrangement supplies the dense, short memory connections needed by AI accelerators and high-performance computing systems.

Conceptual CoWoS-S package with logic and HBM above a continuous silicon interposer

What Is CoWoS-S Packaging?

CoWoS-S is TSMC’s silicon-interposer version of Chip-on-Wafer-on-Substrate packaging: the “S” identifies the silicon interposer that carries the die-to-die wiring.

Within the CoWoS semiconductor packaging family, its distinguishing feature is a continuous silicon interposer beneath the top dies. The logic and HBM are separate components connected on this shared routing platform, rather than one monolithic chip. HBM itself contains vertically stacked memory dies, but the side-by-side arrangement of logic and memory on the interposer is commonly described as 2.5D integration.

TSMC develops the package technology; the system board sits at a different manufacturing level. Our introduction to TSMC’s manufacturing technologies explains that broader context.

What Is Inside a CoWoS-S Package?

A CoWoS-S package contains logic dies and HBM above a silicon interposer, fine die-attachment connections at their interfaces, and a package substrate beneath the interposer.

Part	Position	Function
Logic die	Above the interposer	Processes data and controls memory access
HBM stack	Beside the logic die	Provides wide-interface, high-bandwidth memory
Microbumps	Between top dies and interposer	Connect die pads to interposer wiring
Silicon interposer	Below logic and HBM	Routes dense connections between dies
Through-silicon vias (TSVs)	Through the interposer thickness	Carry connections to its underside
Package substrate	Below the interposer	Redistributes connections toward board-facing terminals

The CoWoS S silicon interposer is primarily an interconnect platform, not an additional processor. It can also incorporate passive functions such as integrated capacitance. The silicon interposer, organic package substrate, and system PCB are therefore three distinct structures—not interchangeable names for the same board.

Underfill and the thermal assembly complete important mechanical and heat-transfer functions. Their materials depend on the qualified package design; a conceptual cross section does not specify an actual lid, thermal-interface material, or assembly thickness.

How Does CoWoS-S Connect Logic Dies and HBM?

Logic-to-HBM signals travel from a die’s pads through microbumps, laterally along the interposer’s metal wiring, and through another set of microbumps into the memory interface.

Lateral logic-to-HBM routing and vertical TSV connections to the package substrate

This lateral memory path is different from the vertical path through interposer TSVs toward the package substrate. An HBM data signal does not have to travel down to the system PCB and back up to the neighboring memory stack. Keeping many connections within the package supports a wide memory interface without routing that interface across the board.

Connection density: fine interposer wiring accommodates many parallel signal connections in a small area.
Shorter paths: adjacent die placement reduces the distance compared with off-package memory routing, although actual delay and loss depend on the layout.
Matched interfaces: logic memory controllers, HBM generation, pad maps, and package routing must work together. An interposer alone does not set bandwidth.

CoWoS S bump pitch refers to center-to-center spacing at a specified bump interface. It must not be confused with TSV pitch, metal line spacing, or board-level BGA pitch. For example, a hypothetical 40 µm pitch with 20 µm-wide pads leaves a nominal 20 µm edge gap; those illustrative dimensions are not a CoWoS-S specification.

Microbump, TSV, and BGA pitches refer to different package interfaces

How Is a CoWoS-S Package Manufactured?

The CoWoS-S process flow prepares the silicon interposer, attaches the logic and memory dies to it, and integrates the resulting assembly with a package substrate.

Design the interconnect platform: coordinate die locations, HBM interfaces, routing layers, TSVs, and power connections.
Fabricate the interposer: form fine metal interconnects and the required through-silicon connections. Large designs may use lithographic stitching across exposure fields.
Prepare the backside connections: thinning and backside processing provide access to the interposer’s vertical interconnects.
Attach the top dies: align the logic and HBM interfaces with the interposer connections and form the die joints, with appropriate mechanical reinforcement.
Complete and verify the package: integrate the package substrate and thermal structure, then check electrical operation and package reliability.

These are public functional stages, not a recipe for TSMC’s proprietary production line. Bonding temperatures, process ordering, tolerances, and inspection limits require the applicable qualified process documentation.

Reliability depends on more than electrical continuity. Silicon, copper, underfill, and substrate materials expand differently during temperature changes. TSMC’s 2013 CoWoS reliability work examined underfill and lid choices, including AlSiC versus copper, in relation to interconnect fatigue. That dated study illustrates why the complete assembly must be qualified; it does not prescribe a lid material for every modern package.

What Limits CoWoS-S Interposer Scaling?

CoWoS-S interposer scaling is constrained by stitched routing, defect exposure, wafer utilization, assembly yield, and mechanical control—not by an absolute one-reticle limit.

TSMC has publicly described reticle stitching to extend silicon interposer area beyond a single exposure field. Its 2021 fifth-generation CoWoS-S publication reported an approximately 2,500 mm² interposer supporting multiple logic dies and eight HBM stacks, with five layers of submicron copper wiring and second-generation integrated capacitors. This is a specific published configuration, not a mandatory HBM count or permanent size ceiling.

Stitching: interconnects crossing exposure boundaries require controlled pattern alignment and continuity.
Yield: increasing area exposes more routing and structures to possible defects; the economics also depend on die and assembly yields.
Mechanical integration: larger assemblies require coordinated substrate, underfill, lid, and cooling design.
Usable floorplan: logic sizes, HBM placement, power regions, and keep-outs determine how much area is actually available.

Interposer area is not the package outline: the substrate and thermal assembly can extend beyond it. Nor can an area in square millimeters be converted into a package width without knowing the shape.

For larger integration footprints, CoWoS-L uses a wider RDL platform with local silicon interconnects rather than extending one continuous silicon interposer. The TSMC CoWoS overview describes these architecture options; their full comparison belongs in a separate S-versus-L discussion.

Where Is CoWoS-S Packaging Used?

CoWoS-S packaging is used in high-end computing products that need dense connections between processing dies and high-bandwidth memory, including AI acceleration and HPC.

AI accelerators: memory bandwidth helps feed compute units with model weights and intermediate data. The benefit depends on the workload, not simply the presence of HBM.
HPC processors and accelerators: simulations and other data-intensive calculations can require substantial bandwidth between compute and memory.
Multi-die computing designs: a shared interposer provides dense routing between separately fabricated logic and memory components.

TSMC’s 2022 annual report identifies CoWoS-S with high-end HPC and AI and describes HBM3-related qualification. Together with the published eight-HBM fifth-generation example, this provides concrete application context without assuming that every GPU, accelerator, or HBM product uses CoWoS-S. A named chip’s packaging variant still requires its own disclosure.

How Does a CoWoS-S Package Connect to a PCB?

A finished CoWoS-S component connects to the PCB through its package substrate and board-facing terminals, commonly a BGA interface—not through the interposer’s microbumps.

Four distinct levels: dies, interposer, package substrate, and system PCB

The component’s released land pattern, ball map, power requirements, and assembly guidance determine the board design. The PCB routes external interfaces and supplies power; it does not reproduce the fine logic-to-HBM wiring inside the package.

Layout: select escape routing and via structures from the actual BGA geometry.
Power: design planes, regulator connections, and board decoupling for the component’s current and voltage limits.
Assembly: follow the device-specific handling, reflow, warpage, and inspection requirements.
Mechanical support: coordinate heatsink attachment, board support, and package keep-outs.

Our guide to advanced HDI PCBs explains board-level routing structures. At EBest Circuit, we support PCB fabrication and PCBA projects around qualified components; we do not claim to manufacture TSMC’s interposers. Send your Gerber files, stackup, BOM, quantities, and package assembly requirements to sales@bestpcbs.com for a board-level review.

FAQs About CoWoS-S

Is CoWoS-S the same as SoIC?

No. CoWoS-S provides interposer-based integration, while SoIC addresses a different level of die stacking and bonding. These technologies can be combined in a larger integration scheme.

Are HBM TSVs and interposer TSVs the same structures?

No. HBM TSVs connect dies within the memory stack; interposer TSVs pass through the separate silicon interposer. They occupy different parts of the package.

Does every CoWoS-S package contain eight HBM stacks?

No. Eight stacks describe one published configuration. The actual count depends on the processor interfaces, memory requirements, floorplan, and qualified package design.

Does reticle stitching mean joining separate pieces of silicon?

No. It joins lithographically patterned regions across exposure fields on the interposer. It does not mean gluing individual silicon tiles together.

Can HBM be replaced like a DIMM?

No. HBM is integrated into the package assembly rather than installed in a board-level memory socket. Replacement is not equivalent to changing a server DIMM.

Tags: cowos s bump pitch, cowos s silicon interposer, cowos semiconductor, CoWoS-S, cowos-s process flow
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Bismaleimide Triazine (BT Resin): Properties, BT Epoxy & FR-4 Comparison

September 18th, 2026

Bismaleimide triazine has become an important resin system for electronic materials that need more dimensional and thermal stability than conventional PCB laminates can provide. It is particularly well known in semiconductor packaging, where thin substrates, fine interconnections, repeated reflow cycles, and moisture sensitivity place tight demands on the laminate.

However, the terminology around BT materials is often inconsistent. BT resin, BT epoxy, BT laminate, BT PCB, and BT substrate do not mean exactly the same thing. Understanding these distinctions is important before comparing material properties or releasing a PCB or substrate specification.

Bismaleimide Triazine BT resin with multilayer PCB laminate and semiconductor package applications

Key Takeaways

Bismaleimide triazine, commonly called BT resin, is a high-performance thermosetting resin system used in PCB laminates and semiconductor package substrates.
BT is a material family rather than one fixed laminate grade. Tg, Dk, Df, CTE, moisture absorption, and other properties vary with resin formulation, reinforcement, fillers, and cure system.
BT epoxy usually refers to a BT resin system modified or blended with epoxy to improve processability, adhesion, toughness, resin flow, or other manufacturing characteristics.
BT laminate, BT PCB, and BT substrate are different terms: the first describes the supplied material, while the latter two describe finished electronic structures.
Compared with standard FR-4, BT materials are commonly selected where dimensional stability, thermal performance, moisture control, and package warpage are more demanding.
BT resin is widely associated with BGA, CSP, SiP, memory, and other organic semiconductor package substrates.
BT is not automatically better than FR-4. Standard or high-Tg FR-4 remains more practical for many conventional multilayer PCBs.
Engineers should specify an exact material manufacturer and grade instead of requesting only “BT material.”

What Is Bismaleimide Triazine (BT Resin)?

Bismaleimide triazine, or BT resin, is a high-performance thermosetting resin system based primarily on bismaleimide and cyanate-ester chemistry. It is widely used in electronic laminates and organic semiconductor package substrates.

The search phrase bismaleimide triazine BT resin refers to this formulated resin family rather than one universal commercial grade.

During curing, the reactive resin components form a highly crosslinked three-dimensional network. This structure can provide a useful combination of:

High glass-transition temperature
Dimensional stability
Low moisture absorption
Thermal resistance
Electrical insulation
Controlled dielectric properties
Good compatibility with multilayer structures

BT resin is not one single chemical compound or one fixed commercial material. Different suppliers can modify the formulation with epoxy, fillers, catalysts, flame retardants, reinforcement, and other additives.

For this reason, an engineer should not assume that every BT laminate has the same Tg, Dk, Df, CTE, or processing conditions.

How Is Bismaleimide Triazine Resin Structured and Cured?

BT resin should be understood as a crosslinked resin system rather than a single molecule with one fixed structure.

A bismaleimide triazine structure is best described as a cured network whose final properties depend on formulation and processing.

Its chemistry generally combines bismaleimide functionality with cyanate-ester chemistry. During curing, cyanate groups can react to form thermally stable triazine-ring structures, while the bismaleimide portion contributes additional crosslinking and heat resistance.

A simplified reaction concept is:

Bismaleimide + Cyanate-Ester Chemistry → Thermal Cure → Crosslinked BT Resin Network

The resulting network can be further modified to balance electrical, mechanical, and processing properties.

Bismaleimide Component

The bismaleimide portion contributes thermal stability and a highly crosslinked structure. Pure BMI systems can be relatively rigid or brittle, so practical electronic formulations are often modified.

Cyanate-Ester Component

Cyanate groups form triazine-ring structures during curing. These structures are associated with high-temperature performance and useful dielectric characteristics.

Modifiers

Commercial BT systems may incorporate epoxy or other modifiers to improve flow, toughness, adhesion, cure behavior, and PCB processing.

Therefore, drawings that show one exact “BT molecule” can be misleading. The material used in an actual laminate is a formulated thermoset system.

What Is the Difference Between BT Resin, BT Epoxy, BT Laminate and BT Substrate?

These terms describe different stages or forms of the material system.

Term	Meaning
BT resin	Bismaleimide-triazine thermosetting resin chemistry
BT epoxy	BT resin system modified or blended with epoxy
BT prepreg	Reinforcement impregnated with partially cured BT-based resin
BT laminate	Cured reinforced sheet material made with a BT resin system
BT PCB	Printed circuit board fabricated using BT-based laminate
BT substrate	Finished semiconductor package substrate using BT-based material

The distinction matters during RFQ and material selection. Asking for “BT resin” does not tell a PCB manufacturer which laminate construction, copper foil, glass style, resin content, or cured thickness to use.

Similarly, a BT substrate is not merely a sheet of BT laminate. It is a finished interconnect structure that can contain fine traces, microvias, solder-mask or build-up layers, package pads, and other features.

For more detail on package construction, SAP/mSAP processing, and BT vs ABF, see our BT Substrate: Material, Process and ABF Comparison guide.

BT resin BT epoxy BT laminate and BT substrate terminology comparison

What Properties Matter in a BT Resin Laminate?

The most important BT laminate properties depend on the application. Package substrates may prioritize dimensional stability and moisture behavior, while high-speed boards may place greater emphasis on Dk and Df.

Property	Why It Matters
Tg	Dimensional and mechanical behavior through thermal cycles
Td	Thermal decomposition resistance
X/Y CTE	In-plane dimensional stability
Z-axis CTE	Via and plated-hole reliability
Dk	Impedance, propagation velocity, and trace geometry
Df	Dielectric contribution to signal loss
Moisture absorption	Package reliability and reflow behavior
Peel strength	Copper-to-laminate adhesion
Flexural/mechanical properties	Thin-substrate handling and package stability

The values cannot be generalized to every BT material. For example, AGC’s N5000 is a commercially available BT epoxy laminate and prepreg with published dielectric values around Dk 3.6 and Df 0.01 under its specified test conditions.

Those numbers should be treated as one material-grade example, not as a universal BT specification.

Research and commercial formulations can show substantially different Tg and dielectric performance because resin chemistry, fillers, glass reinforcement, resin content, and test method all influence the result.

Always compare exact material grades using the same test method and frequency.

Key BT resin laminate properties including Tg Dk Df CTE moisture and thermal resistance

Why Is BT Resin Used for BGA, CSP and IC Package Substrates?

BT resin is widely used in organic package substrates because semiconductor packaging requires more than ordinary PCB electrical insulation.

A bismaleimide triazine substrate uses this material family to support fine package interconnections and repeated thermal cycles.

A package substrate must maintain dimensional control while dealing with:

Fine-pitch package routing
Thin core and dielectric structures
Multiple lead-free reflow cycles
Silicon-to-substrate CTE mismatch
Moisture exposure
BGA or CSP warpage
Fine via and pad registration
Package assembly stress

BT-based laminates can provide a useful balance of high-temperature stability, low moisture uptake, mechanical rigidity, and electrical performance.

This is particularly important in thin BGA and CSP structures. Even small dimensional changes can affect solder-ball coplanarity, substrate warpage, trace registration, or package reliability.

BT materials are therefore commonly associated with:

BGA substrates
CSP substrates
Memory packages
SiP modules
Flip-chip package structures
RF and communication modules

The final substrate performance still depends on the exact BT grade, stackup, copper pattern, package size, substrate thickness, and manufacturing process.

Bismaleimide Triazine applications including BGA substrate CSP memory package and RF module

BT Resin vs FR-4: What Is the Difference?

FR-4 and BT resin laminates are both organic electronic materials, but they are normally selected for different performance and cost targets.

Factor	FR-4	BT Resin Laminate
Primary use	General PCB manufacturing	Package substrates and higher-reliability structures
Resin system	Primarily epoxy-based	BT or BT-epoxy-based
Tg	Wide range by grade	Often high, but grade-dependent
Dimensional stability	Suitable for conventional PCB	Better suited to demanding package control
CTE control	Depends on grade and reinforcement	Low-CTE formulations available
Moisture behavior	Grade dependent	Often selected for lower moisture sensitivity
Dielectric properties	Standard to low-loss grades available	Grade dependent; can be optimized for package/high-speed use
Thin-substrate use	Possible but not its main strength	Common in package substrate applications
Processing familiarity	Very mature	More material-specific
Material cost	Lower	Generally higher

The main difference is not simply that BT has a higher Tg. High-Tg FR-4 materials can also provide strong thermal performance.

BT becomes more attractive when several requirements appear together, such as high dimensional stability, low package warpage, moisture resistance, thin substrate construction, repeated reflow reliability, and fine-pitch interconnection.

FR-4 remains the more economical and widely available choice for most conventional PCBs.

Is BT Resin Always Better Than FR-4?

No. BT resin is not automatically a better PCB material than FR-4. It is better suited to certain applications where its material characteristics solve specific reliability or dimensional problems.

Standard or high-Tg FR-4 is usually the practical choice for:

Industrial control boards
Consumer electronics
General multilayer PCBs
Power-control boards
Cost-sensitive products
Conventional SMT assemblies
Moderate-density HDI designs

BT becomes more attractive when the product requires:

Semiconductor package substrate construction
Very thin organic substrates
Tighter dimensional stability
Lower package warpage
Fine-pitch BGA or CSP structures
Low moisture sensitivity
Higher package-level thermal reliability

Using BT where ordinary FR-4 already meets the electrical and reliability requirements can increase material cost and supply complexity without creating a meaningful product benefit.

The correct decision should come from the complete stackup, package geometry, thermal cycle, electrical requirements, warpage target, and qualification specification.

Where Is Bismaleimide Triazine Used in Electronics?

Bismaleimide triazine materials are most strongly associated with semiconductor packaging, but their use is not limited to one product type.

A bismaleimide triazine PCB may also be specified when a conventional board needs the qualified thermal or dimensional behavior of a BT laminate.

Common applications include:

BGA package substrates
CSP substrates
Memory package substrates
System-in-Package modules
RF modules
Communication modules
Selected LED package substrates
High-reliability electronic modules
Selected high-frequency PCBs
Thin multilayer interconnect structures

A BT laminate can also be used for conventional PCB structures when its thermal or dimensional characteristics provide a useful engineering advantage.

However, it should not be assumed that every high-speed PCB needs BT resin. Modern high-speed boards can use multiple material families, including low-loss FR-4 derivatives, PPE/PPO systems, PTFE-based laminates, hydrocarbon ceramics, and other specialty materials.

The application requirement should determine the laminate family, not the material’s reputation alone.

What Are the Manufacturing Challenges of BT Epoxy Laminate?

BT epoxy laminate can require tighter material and process control than a standard FR-4 production flow.

Important manufacturing factors include:

Material storage
Moisture control
Prepreg handling
Lamination temperature and pressure
Resin-flow control
Cure profile
Dimensional movement
Drilling parameters
Desmear conditions
Copper adhesion
Thin-board handling
Warpage control

Moisture Management

Low moisture absorption is an important material characteristic, but storage and handling still matter. Prepreg and thin laminate structures should follow supplier recommendations.

Lamination

BT resin flow and cure behavior differ by formulation. The press cycle should follow the actual laminate supplier’s process window rather than an FR-4 recipe being reused automatically.

Drilling and Hole Preparation

Drill parameters, smear behavior, and desmear chemistry can depend on the cured resin system and glass construction.

Dimensional Stability

Package substrates and thin BT boards may require tighter compensation because small X/Y movement can affect fine-pitch registration.

Warpage

Thin BT-based structures can still warp if copper distribution, build-up symmetry, substrate thickness, package design, or lamination stress is unbalanced. A high-performance resin does not eliminate the need for mechanical stackup control.

How Should Engineers Specify BT Material for PCB Fabrication?

A production drawing should identify the exact BT laminate requirements rather than simply stating “BT material.”

Useful information includes:

Material manufacturer
Exact material grade
Core or prepreg designation
Finished dielectric thickness
Glass style
Resin content
Copper foil type and weight
Tg and test method
Dk and Df test frequency/method
X/Y and Z-axis CTE where critical
Moisture requirement
Finished board thickness
Surface finish
Controlled impedance
Approved alternative materials

For high-frequency designs, Dk and Df values should be tied to the relevant test method and frequency. A Dk value measured by one method should not automatically replace a design Dk obtained through another method.

For thin or packaging-related structures, engineers should also specify dimensional, warpage, and registration requirements where applicable.

“Use BT material” is not enough for a controlled production release. Two BT laminates may differ significantly in processing behavior and electrical performance.

BT laminate specification guide including material grade Tg Td Dk Df glass style copper type and thickness

When Should You Choose BT Resin Instead of Another PCB Material?

Material selection should start from the product requirement rather than choosing BT first and designing around it.

Requirement	Material Direction to Consider
General multilayer PCB	Standard or high-Tg FR-4
Cost-sensitive electronics	FR-4
High-reliability conventional PCB	High-Tg / specialty FR-4
BGA/CSP organic package substrate	BT resin commonly considered
Thin warpage-sensitive package	BT or another qualified package substrate material
Very high-speed PCB	Low-loss FR-4, PPE/PPO, PTFE/hydrocarbon or other high-speed materials
Flexible circuit	Polyimide
Very high thermal conductivity	Ceramic or metal-based structures
Advanced high-density IC build-up	BT core, ABF, or other package-specific systems

BT is strongest when thermal, moisture, dimensional, and package-level requirements need to be balanced in one organic material system.

It is not necessarily the first choice for ultra-high-frequency transmission, extreme thermal conductivity, flexible construction, or every advanced IC substrate architecture.

The material decision should therefore consider the entire structure: electrical performance, package geometry, process capability, reliability, cost, supply availability, and customer qualification.

FAQ About Bismaleimide Triazine

1. What does BT stand for in PCB materials?
BT stands for Bismaleimide Triazine, a high-performance thermosetting resin system used in electronic laminates and package substrates.

2. Is BT resin the same as BT epoxy?
No. BT epoxy generally refers to a BT resin system that has been modified or blended with epoxy to adjust processing, adhesion, toughness, or other material properties.

3. Is BT resin better than FR-4?
Not for every PCB. BT is most useful when thermal stability, dimensional control, moisture behavior, package warpage, or semiconductor-substrate requirements justify the additional material cost.

4. Is BT resin used for BGA substrates?
Yes. BT resin is widely associated with BGA, CSP, memory, SiP, and other organic semiconductor package substrates.

5. Does every BT laminate have the same Tg and Dk?
No. BT is a material family. Tg, Dk, Df, CTE, moisture absorption, and other values vary by formulation, reinforcement, resin content, and test method.

6. Is a BT substrate the same as an IC substrate?
A BT substrate is one type of organic IC package substrate. Other IC substrates can use ABF and additional material systems depending on package architecture and interconnect density.

Bismaleimide triazine should therefore be specified as a material system, not as a single fixed-property laminate. Resin formulation, epoxy modification, glass reinforcement, copper construction, thickness, and processing conditions all influence how the finished PCB or substrate performs.

For a PCB project requiring BT laminate or another specialty material, EBest Circuit can review the material grade, stackup, dielectric thickness, copper construction, impedance requirements, finished thickness, and manufacturing constraints before fabrication. Send your project files to sales@bestpcbs.com for DFM review.

Tags: bismaleimide triazine, bismaleimide triazine bt resin, bismaleimide triazine pcb, bismaleimide triazine structure, bismaleimide triazine substrate
Posted in best pcb, Design Guide, PCB Material, PCB Technology | No Comments »

How Is a Vehicle Domain Controller PCBA Manufactured?

September 18th, 2026

A vehicle domain controller combines the processing, communication, and control resources that were previously distributed across several automotive ECUs. Its PCBA may carry a high-performance processor, high-speed memory, vehicle-network interfaces, power-management circuits, security devices, storage, and large harness connectors on one densely populated board. Manufacturing that assembly requires more than placing components correctly; the soldering process must accommodate fine-pitch packages, uneven thermal mass, hidden joints, and strict mechanical constraints at the same time.

EBest Circuit (Best Technology) supports customer-released domain-controller projects through an IATF 16949-certified automotive quality-management system. Our capabilities include multilayer and HDI PCB fabrication, controlled-impedance manufacturing, component sourcing, mixed SMT and through-hole assembly, AOI, X-ray inspection, programming coordination, MES-based traceability, and customer-defined testing. These controls help keep the correct hardware revision, component identity, process records, and approved manufacturing route connected as a project moves from prototypes to repeat production. To discuss a domain controller PCBA build, send the released PCB data, BOM, assembly information, quantities, and required test scope to sales@bestpcbs.com.

What Is a Vehicle Domain Controller?

A vehicle domain controller is a high-performance electronic control unit that manages several related functions within one vehicle domain. Instead of assigning every function to a separate ECU, the controller provides shared computing, communication, power-management, and software resources for a group of systems.

The “domain” describes a logical group of vehicle functions. Depending on the vehicle architecture, it may cover body and comfort systems, the digital cockpit, ADAS, propulsion, chassis, connectivity, or a combination of these areas.

A domain controller is therefore not simply a larger version of a conventional ECU. It must receive data from many sensors and network nodes, process multiple workloads, exchange information with other controllers, and maintain predictable operation when one function places a heavy demand on shared hardware.

It should also be distinguished from a zone controller. A domain controller groups functions by purpose, while a zone controller usually groups physical inputs, outputs, sensors, and actuators by their location in the vehicle. Some newer platforms use both: zone controllers collect local signals, and a domain or central computer performs higher-level processing.

How Does Automotive Domain Controller Architecture Consolidate ECUs?

Automotive domain controller architecture consolidates ECUs by moving compatible workloads onto shared processing and communication hardware. The goal is not to connect several existing ECUs inside one enclosure. It is to reduce duplicated processors, memory, power supplies, gateways, and network interfaces while coordinating the functions through a common computing platform.

For example, several cockpit functions may share an applications processor, graphics resources, memory, storage, and vehicle-network connection. An ADAS domain controller may receive camera, radar, and other sensor data through high-speed interfaces, process the information, and exchange decisions with braking, steering, or gateway controllers.

This consolidation changes the PCBA in several ways:

processor and memory density increases;
high-speed interfaces occupy more routing and connector resources;
several supply rails must start, sequence, and remain stable under changing loads;
communication traffic from CAN, CAN FD, LIN, Automotive Ethernet, or other interfaces converges on one assembly;
thermal load becomes concentrated around processors, memory, PMICs, and network devices;
a defect in one shared resource can affect several vehicle functions.

The architecture can reduce module count and wiring complexity, but it also concentrates electrical, thermal, and manufacturing risk. That is why a domain-controller PCBA cannot be treated as a generic control board with a faster processor added.

Which Functions Can an Automotive Domain Controller Combine?

An automotive domain controller combines functions that need shared computing, coordinated data, or common vehicle interfaces. The exact grouping depends on the automaker's electrical and electronic architecture; there is no universal set of functions for every controller.

Common domain groupings include:

Body domain: lighting, doors, windows, seats, mirrors, wipers, access, and comfort functions.
Cockpit domain: digital instrument clusters, infotainment, displays, audio, voice processing, and driver interaction.
ADAS domain: sensor input, image or radar processing, sensor fusion, path-related calculations, and communication with actuation controllers.
Propulsion domain: engine, transmission, inverter, motor, battery, charging, and energy-management coordination.
Connectivity domain: external wireless connectivity, gateways, secure data exchange, over-the-air service support, and communication between internal and external networks.

These categories can overlap. A cockpit controller may include connectivity functions, while a central vehicle computer may run workloads from more than one traditional domain. The released system architecture—not the marketing name—determines what the PCBA must support.

This distinction also keeps closely related modules separate. A body control module mainly controls body loads and convenience functions. A telematics control unit focuses on vehicle-to-network communication. A domain controller may coordinate either area, but its defining feature is the consolidation of multiple related workloads and interfaces.

What Hardware Is Inside a Vehicle Domain Control Unit?

The hardware inside a vehicle domain control unit reflects the functions it consolidates. A body-domain board may emphasize protected inputs and load drivers, while an ADAS or cockpit controller may emphasize computing performance, memory bandwidth, high-speed networking, and thermal management.

Typical hardware blocks include:

Hardware block	Typical devices	Manufacturing concern
Main processing	Automotive MCU, MPU, SoC, FPGA or accelerator	Fine-pitch BGA assembly, heat and lifecycle control
Memory	LPDDR, DDR, Flash, eMMC or UFS	Short high-speed connections and hidden solder joints
Vehicle networking	CAN, CAN FD, LIN, FlexRay and Automotive Ethernet devices	Controlled-impedance paths, termination and connector transitions
Power management	PMICs, DC-DC converters, LDOs, supervisors and protection devices	Multiple rails, switching heat and package-specific soldering
Storage and security	Secure elements, hardware security modules and nonvolatile storage	Programming, identification and configuration control
Sensor or display interfaces	SerDes, camera links, display interfaces and level translation	High-speed differential routing and connector integrity
Timing	Crystals, oscillators, clock generators and buffers	Placement sensitivity and contamination control
External connection	Board-to-board and harness connectors, coaxial or high-speed connectors	Mechanical load, coplanarity and through-hole soldering

The board may also include shielding frames, heatsink contact areas, thermal interface material, mounting points, test pads, and service or programming connectors. These mechanical features influence component placement and assembly sequence even though they are not active electronic functions.

Compared with a conventional electronic control unit board, a high-performance domain controller usually places greater pressure on routing density, package pitch, memory proximity, power distribution, and heat removal.

What Makes a Domain Controller PCBA Difficult to Assemble?

A domain controller PCBA is difficult to assemble because it combines components that need very different soldering conditions on the same board. A fine-pitch BGA needs controlled solder-paste deposition, board support, package alignment, and a stable reflow profile. When solder paste inspection is included in the production route, it can identify deposit-volume or alignment problems before those conditions become hidden beneath a BGA after reflow. A large connector, shield frame, inductor, or power component absorbs much more heat and may require a different assembly process.

The main difficulty is the interaction between these requirements, not any one component by itself.

Typical assembly conflicts include:

small passives and fine-pitch packages beside tall connectors or shielding structures;
high-density BGA regions with limited optical access;
large ground planes that draw heat away from selected joints;
heavy connectors that need strong solder joints without overheating nearby components;
bottom-terminated packages whose solder coverage cannot be judged by surface appearance;
components with moisture-sensitivity or storage requirements that differ from the rest of the BOM;
heatsink, shield, coating, or enclosure steps that can obstruct later inspection or rework.

Process sequencing matters. Shield frames or large connectors installed too early may block X-ray views, rework access, or test fixtures. Installed too late, they may require an additional heating process that exposes the board to more thermal stress. The assembly plan therefore has to follow the actual package mix, board construction, thermal mass, and inspection access.

That process plan also has to survive the transition from prototypes to repeat production. Recording the approved stencil, placement program, reflow profile, fixtures, inspection settings, and product revision helps prevent a later batch from being built with an outdated or incomplete process. MES-based traceability can connect those records with the applicable PCB, component lots, and programmed product identity.

Domain controllers also contain costly processors and memory devices. Soldering a visible connector correctly does not compensate for an open BGA joint beneath the main processor. Inspection and process control must therefore follow the failure modes of each package rather than rely on one final visual check.

How Are High-Pin-Count BGAs and Automotive Connectors Assembled on One PCBA?

High-pin-count BGAs and automotive connectors can share one PCBA when the assembly sequence, board support, solder volumes, and thermal profile are planned for both package types. The challenge is that they sit at opposite ends of the assembly spectrum: the BGA depends on uniform hidden joints, while the connector must withstand insertion force, harness load, and repeated temperature and vibration exposure.

For the BGA area, solder-paste printing must produce repeatable deposits on adjacent fine-pitch components. Placement accuracy and package handling are important, but the reflow profile is equally critical. The board must reach sufficient temperature for complete solder formation without creating excessive package warpage, voiding, component damage, or unnecessary thermal exposure.

Large automotive connectors may use surface-mount hold-downs, press-fit pins, through-hole solder joints, or a combination of retention features. Through-hole pins can be assembled by selective soldering, pin-in-paste, or another approved process depending on connector geometry, board thickness, nearby components, and solder-side access.

Several practical interactions must be resolved:

The connector body must not shadow nearby components during reflow or block the selective-soldering nozzle.
Through-hole copper connected to large planes may need more heat than signal pins in the same connector.
Board supports must prevent the connector's mass or insertion load from flexing the BGA region.
Pin protrusion, hole fill, solder bridging, and connector seating must all remain within the released acceptance criteria.
X-ray access to the processor, memory, and other hidden joints should remain usable after the connector and shielding hardware are installed.

The best process is not automatically “reflow everything” or “solder the connector later.” It is the sequence that creates a stable window for both the hidden BGA joints and the mechanically loaded connector joints on the actual board. EBest Circuit's mixed-assembly experience allows the BGA, surface-mount hold-downs, through-hole pins, shielding hardware, and inspection access to be reviewed as one manufacturing sequence rather than as unrelated operations.

How Do Heat and Board Warpage Affect Domain Controller Assembly?

Heat and board warpage affect domain controller assembly by changing how packages, pads, and solder joints meet during reflow. A dense processor region, thick copper planes, large connectors, and uneven component distribution can create substantial temperature differences across the PCBA. At the same time, the PCB and large packages expand at different rates.

If a BGA package or the PCB bows during reflow, corner balls may separate from their pads or touch only after part of the solder has solidified. This can create opens, head-in-pillow defects, stretched joints, or weak connections that are difficult to see from the surface. Excessive board deformation can also affect fine-pitch connectors, bottom-terminated packages, and coplanarity during later assembly steps.

Production controls should address the actual thermal and mechanical behavior:

support the panel and assembly near heavy or mechanically sensitive regions;
profile representative boards at both high-mass and low-mass locations;
keep the time and peak temperature within the limits of the PCB, packages, solder alloy, and moisture-sensitive devices;
review copper balance, board thickness, panel rails, breakaway features, and component distribution for their effect on deformation;
use package-appropriate X-ray views to assess hidden joints after soldering;
avoid fixture pressure that masks or introduces board bending during inspection and test;
control heatsink and enclosure attachment forces so that the finished board is not flexed around large BGAs.

Thermal performance in use and soldering temperature during production are related but different problems. A copper area or thermal path that helps cool the operating processor can increase local thermal mass during reflow. The assembly process must therefore be developed from the released board construction and component layout rather than from a generic oven recipe.

FAQs About the Vehicle Domain Controller

Is a vehicle domain controller the same as an ECU?

A vehicle domain controller is a type of high-performance ECU. A conventional ECU may control one function or subsystem, while a domain controller consolidates several related functions, networks, or workloads on shared hardware.

What is the difference between a domain controller and a zone controller?

A domain controller groups functions by purpose, such as cockpit, ADAS, body, or propulsion. A zone controller groups sensors, actuators, power distribution, and network connections by physical vehicle location. A vehicle architecture may use both.

Does every vehicle domain controller use an HDI PCB?

No. HDI becomes useful when processor fan-out, memory routing, package pitch, interface count, or board-size limits cannot be handled reliably with conventional through-hole vias. The released component placement, stackup, routing density, and manufacturing limits determine whether HDI is necessary.

Why are BGAs common in domain controller PCBAs?

High-performance processors, memory, FPGAs, and network devices need many power, ground, and signal connections in a compact area. BGA packages provide high connection density and short electrical paths, but their joints are hidden and require a controlled assembly and inspection process.

Can a PCBA manufacturer build the complete vehicle domain controller?

A PCBA manufacturer can fabricate the released PCB, source approved components, assemble the board, inspect hidden and visible joints, program devices, and perform agreed electrical or functional tests. The exact deliverable depends on the released product data and quotation scope.

A reliable vehicle domain controller PCBA depends on managing several difficult features together: dense processors and memory, controlled-impedance networks, multiple power rails, heavy automotive connectors, hidden solder joints, and concentrated heat. EBest Circuit combines IATF 16949 process control with multilayer and HDI fabrication, mixed assembly, AOI, X-ray inspection, MES-based traceability, programming coordination, and customer-defined testing. When required by the confirmed project scope, automotive documentation such as PPAP-related records can also be coordinated without confusing manufacturing evidence with vehicle-level validation.

For a vehicle domain controller program, this combination helps preserve the approved product revision and manufacturing process as the build moves from prototypes to repeat production. Send your released PCB data, BOM, assembly information, quantities, and required test scope to sales@bestpcbs.com for review.

Tags: Automotive Domain Controller Architecture, Domain Controller PCBA, Vehicle Domain Controller
Posted in Automotives, best pcb, bestpcb, Solutions | No Comments »

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