A PCB keepout area is a rule-controlled region that blocks selected objects, such as components, traces, vias, pads, or copper pours. It prevents electrical, assembly, enclosure, antenna, and fabrication conflicts before production.
A useful keepout identifies the restricted object, affected layer, and verification method. Verify that same restriction in DRC and the released manufacturing data.
What Is a PCB Keepout Area and What Does It Restrict?
A PCB keepout area is an exclusion rule, not a physical layer that automatically appears on the finished board. Its boundary tells the layout system which objects may not enter a defined two-dimensional or three-dimensional space.
Match the restricted objects to the risk. An antenna may prohibit copper, vias, and components on several layers, while a connector overhang may block components but allow copper underneath. Broad restrictions waste routing space and create unnecessary DRC errors.
- Component restriction: reserves placement and service access.
- Routing restriction: keeps traces out of sensitive or unsafe regions.
- Via and pad restriction: excludes drilled or plated features from hazards.
- Copper restriction: removes planes or pours while allowing selected objects.
- Height restriction: reserves Z-axis space for enclosures, heatsinks, switches, or connectors.
PCB Keepout vs. Keepin, Clearance, Courtyard and Board Outline: What Is the Difference?
These terms control different design relationships and should not be used interchangeably. Confusing them can produce false DRC results, incorrect fabrication outlines, or missing assembly space.
| Terminology | Primary Function | Controlled Relationship | Engineering Distinction |
| Keepout | Excludes selected objects from a region | Selected layout or mechanical objects | Available objects and layers depend on the EDA rule type |
| Keepin | Confines selected objects inside a region | Routing or component placement | Often used with the board boundary or functional blocks |
| Clearance | Maintains a minimum through-air distance | Spacing between conductive parts | Usually expressed as a rule value, not a drawn exclusion shape |
| Creepage | Maintains a minimum surface-path distance | Path between conductive parts along insulation | Must be calculated from the applicable safety requirements |
| Courtyard | Represents assembly and rework space around a footprint | Nearby component bodies and assembly access | It may be a reference boundary rather than an enforced rule |
| Board outline | Defines the finished board perimeter | Finished outer profile | It must not be replaced by a vague keepout boundary |
| Cutout or slot | Defines material that must be removed | Routed or drilled openings | It is a manufactured feature and requires explicit output data |
What Types of PCB Keepout Areas Are Used in Layout?
Keepout types should be selected by the object that creates the risk. The most common groups are component, route, via, copper, drill, height, and combined keepouts.
- Component keepout: prevents packages from entering connector mating zones, screw access areas, or moving switch paths.
- Route keepout: protects antenna fields, sensitive analog regions, isolation barriers, and areas exposed to mechanical damage.
- Via keepout: prevents drilled features beneath seals, press-fit hardware, contact surfaces, or restricted RF regions.
- Copper keepout: removes planes and pours around antennas, capacitive sensors, board edges, or exposed metalwork.
- Drill keepout: protects tooling, slots, cavities, controlled-depth features, and mechanically weak regions.
- Height keepout: reserves three-dimensional volume above or below the PCB.
- Combined keepout: excludes several object classes when one requirement applies to all of them.
PCB Keepout Layer vs. Signal-Layer Keepout: Which Should You Use?
Use an all-layer keepout only when the restriction must apply through the stackup; use a signal-layer keepout when the risk is local to one copper layer. This choice preserves routing freedom without weakening the intended control.
An antenna may require no copper or vias on every layer beneath its radiating element. A connector may need only a top-layer copper restriction. Check the affected layers, repour copper, and run DRC.
How Should PCB Keepout Areas Be Defined for Antennas, Mounting Holes, Connectors and Heatsinks?
Each application needs its own exclusion shape and object list. Convert the datasheet, mechanical model, assembly method, and service movement into enforceable rules.
- PCB antenna keepout: follow the antenna or wireless-module reference design. Confirm restricted copper layers, ground clearance, board-edge placement, enclosure material, and nearby metal.
- Mounting-hole keepout: include the screw head, washer, standoff, tool access, tolerance, and grounding requirement.
- Connector keepout: reserve the mating plug, cable bend, latch movement, insertion path, and service access.
- Heatsink keepout: include clips, fasteners, isolation hardware, airflow, and neighboring component height.
- Board-edge keepout: account for profile tolerance, depanelization, edge plating, bevels, rails, and component overhang.
How Should High-Voltage PCB Keepouts Be Used with Creepage and Clearance Rules?
A high-voltage keepout can enforce an approved safety distance, but it cannot determine that distance. Clearance and creepage depend on the applicable product standard, working voltage, transient conditions, pollution degree, material group, altitude, coating, and insulation strategy.
Use approved clearance rules for direct spacing and keepout geometry where copper, vias, or components are prohibited. Supply slots as routed geometry because a keepout does not remove laminate. Record the controlling safety requirement.
How Do Altium, KiCad, OrCAD and EasyEDA Represent PCB Keepout Zones?
Tool terminology differs, but the engineering decision stays the same. Confirm the prohibited objects, boundary, and affected layers in the software version being used.
- Altium Designer: places object-specific keepouts on a signal layer or the Keep-Out Layer. Signal-layer keepouts are local; the Keep-Out Layer applies across signal layers.
- KiCad: uses rule areas that can keep out tracks, vias, pads, zone fills, and footprints on selected layers.
- OrCAD X: separates route keepouts, package keepouts, and keepins into constraint subclasses. Verify the assigned subclass and DRC result.
- EasyEDA: uses Solid Region functions such as No Solid for copper exclusion and Board Cutout for a physical opening. These functions are not interchangeable; rebuild copper and inspect the Gerber preview.
After migration, review every prohibited object and rerun DRC because rule attributes may be flattened or lost.
How Do You Create and Verify a PCB Keepout Area with DRC?
A keepout is complete only after verification. Check its boundary, prohibited objects, affected layers, responsible owner, and test violation.
- Identify the functional, mechanical, RF, safety, or manufacturing reason for the exclusion.
- Obtain the controlling dimensions and tolerances from the datasheet, mechanical model, drawing, or compliance requirement.
- Select only the object classes that must be prohibited.
- Choose all layers or the specific affected layer and draw a closed, correctly sized boundary.
- Associate reusable constraints with the footprint or library item when they must follow the component.
- Repour copper, update the design database, and run the complete DRC.
- Temporarily attempt to place a prohibited object inside the region and confirm that the expected violation appears.
- Review the 3D assembly, manufacturing outputs, and final plots before release.
Record the location, reason, reviewer, and revision for each waiver; do not disable the rule globally.
Why Do PCB Keepout DRC Errors Occur and How Can They Be Fixed?
Most keepout DRC errors have three causes: incorrect restriction scope, an inherited footprint rule, or geometry on the wrong layer.
- Footprint self-conflict: a library keepout overlaps its own pads. Exclude the intended pad class, associate the region correctly, or revise the footprint rule rather than ignoring every collision.
- Wrong-layer placement: an all-layer keepout was used when only one surface required protection. Move it to the intended signal layer and rerun DRC.
- Copper-pour anomaly: the zone has not been repoured, or the restriction does not include copper fills. Update the pour and inspect the configured object list.
- Imported-rule loss: a translated design converted the keepout into ordinary graphics. Recreate enforceable rules in the destination tool.
- Board-outline confusion: profile geometry was placed on a keepout or mechanical layer with an ambiguous name. Establish one authoritative closed outline and confirm it in the fabrication viewer.
What Common PCB Keepout Mistakes Cause Fabrication or Assembly Problems?
A correct-looking boundary can still fail. The rule must control the intended objects and production data.
- Restricting everything: an unnecessary all-object keepout blocks valid routing and encourages manual rule overrides.
- Ignoring tolerance: the boundary matches nominal CAD geometry but leaves no room for board profile, component, fixture, or enclosure variation.
- Missing Z-axis space: the 2D layout passes while a heatsink, connector latch, cable, or screw collides in assembly.
- Using a keepout as a cutout: the designer expects laminate removal without providing routed geometry.
- Hiding requirements in notes: a text comment is not converted into an EDA rule, so future routing changes bypass it.
- Sending ambiguous layers: a file labeled GKO, GM1, Outline, or Mechanical is interpreted differently by the designer and fabricator.
Should PCB Keepout Areas Appear in Gerber, ODB++, IPC-2581 or Manufacturing Drawings?
Keepout rules do not normally need to become printed or etched artwork, but manufacturing-relevant constraints must be communicated unambiguously. Gerber primarily describes physical layer images; a keepout often appears only through its effect, such as missing copper or displaced features.
ODB++ and IPC-2581 can carry richer design intelligence, but CAM import may lose attributes. Physical features still need physical outputs. Place the perimeter on the agreed outline layer, supply slots and cutouts as routed geometry, and show height limits in the assembly drawing or mechanical model.
How Should PCB Keepout Requirements Be Communicated to the Fabricator and Assembler?
Communicate the required result, not merely “keepout.” State the controlling dimensions, affected operation, and source file.
- Fabrication data: provide Gerber or ODB++/IPC-2581, NC drill data, one authoritative board outline, and clearly identified slots and cutouts.
- Fabrication drawing: state board dimensions, profile tolerance, edge restrictions, special routing, bevels, castellations, and plated-edge requirements.
- Assembly drawing: identify component, connector, cable, fastener, heatsink, fixture, and Z-height exclusions.
- Mechanical model: provide STEP or an agreed ECAD/MCAD format when enclosure fit or moving parts control the space.
- README and notes: map nonstandard layer names and identify which file is authoritative when duplicate outline-like layers exist.
If a manufacturer requests a “keepout layer,” confirm whether it means the outline, copper-to-edge clearance, panel-routing clearance, or a mechanical restriction.
What PCB Keepout Checks Should Be Completed Before Design Release?
Release review must prove two things: the rule is enforced and manufacturing can interpret it correctly.
- Constraint source: every critical keepout traces to a datasheet, drawing, calculation, mechanical model, or approved requirement.
- Restriction scope: the prohibited objects and affected layers match the actual risk.
- Boundary integrity: shapes are closed, correctly dimensioned, and include tolerance.
- Library ownership: component-specific keepouts move with the footprint and do not create self-collisions.
- DRC evidence: the rule detects an intentional test violation and the final report contains no unexplained errors.
- Output review: Gerber, drill, outline, slot, copper, assembly, and mechanical data agree in independent viewers.
- Cross-discipline approval: layout, mechanical, RF, safety, test, and manufacturing owners review the constraints relevant to them.
How Can Manufacturer DFM Review Verify PCB Keepout and Mechanical Constraints?
Manufacturer DFM should verify that the released geometry can be fabricated, panelized, assembled, and inspected without violating the intended exclusions. It does not replace the designer’s functional, RF, safety, or enclosure validation.
DFM review should compare the outline, copper-to-edge distance, slots, drills, antenna regions, mounting hardware, overhang, panel tabs, tooling holes, and assembly access. Conflicting layers should be reported rather than resolved by assumption.
Send final manufacturing outputs, stackup, assembly drawing, mechanical model, panel preferences, and notes identifying critical keepouts. A PCB keepout area review is most effective before the package is frozen.
FAQs About PCB Keepout Areas
Q1: Does a keepout control the autorouter as well as manual routing?
A1: Only if the autorouter reads that rule type. Test-route through the region and confirm that the tool blocks it.
Q2: Can a PCB keepout area have an irregular or curved boundary?
A2: Yes. Use the simplest closed shape covering the restricted envelope. Extra vertices complicate editing and translation.
Q3: Do solder mask and paste layers need separate keepout rules?
A3: Usually, yes. Copper, solder mask, paste, and silkscreen are separate outputs. Define and plot each required exclusion.
Q4: How should imported vendor footprints with keepouts be checked?
A4: Compare it with the current datasheet, inspect every restricted object and layer, and trigger a test violation. Quiet DRC is not proof.
Q5: What happens to keepouts when a component is replaced?
A5: Recheck the body, mating path, thermal hardware, antenna rules, and Z-height. Pin compatibility does not prove mechanical compatibility.
Q6: Should test points have their own keepout area?
A6: Add one when a probe or fixture needs access. Cover the tool envelope and tolerance, not only the pad diameter.
Q7: How should keepouts be handled in PCB assembly variants?
A7: Keep common constraints in the base design. Document variant rules when optional hardware changes the occupied space.
Q8: Can panel rails, breakaway tabs, or V-scores violate board-level keepouts?
A8: Yes. Panelization adds temporary geometry. Check rails, tooling holes, fiducials, tabs, mouse bites, and V-scores.
Q9: Should a DNP component’s keepout be removed?
A9: Not automatically. Retain it for future population, service access, fixtures, or enclosure clearance. Remove it only through variant review.
Q10: How can ECAD and MCAD teams prevent keepout changes from being lost?
A10: Exchange revision-controlled models, assign each constraint owner, review changes, and rerun DRC plus collision checks.
If your design includes critical antenna, board-edge, mounting, connector, high-voltage, or enclosure restrictions, send the manufacturing package to EBest Circuit for DFM review. Email Gerber/ODB++, drill files, stackup, fabrication and assembly drawings, quantity, test requirements, and mechanical model to sales@bestpcbs.com for an engineering review and quotation.
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Tags: PCB Keepout Design Rules, PCB Keepout DRC, PCB Keepout Layer, PCB Keepout Manufacturing Files