{"id":39025,"date":"2026-11-14T16:12:15","date_gmt":"2026-11-14T08:12:15","guid":{"rendered":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/substrate-integrated-waveguide\/"},"modified":"2026-11-14T16:12:15","modified_gmt":"2026-11-14T08:12:15","slug":"substrate-integrated-waveguide","status":"publish","type":"post","link":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/substrate-integrated-waveguide\/","title":{"rendered":"Substrate Integrated Waveguide: Design for the Right Band"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_89 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/substrate-integrated-waveguide\/#Substrate_Integrated_Waveguide_SIW_What_the_Via_Rows_Do\" >Substrate Integrated Waveguide (SIW): What the Via Rows Do<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/substrate-integrated-waveguide\/#Substrate_Integrated_Waveguide_Design_Start_With_Four_Dimensions\" >Substrate Integrated Waveguide Design: Start With Four Dimensions<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/substrate-integrated-waveguide\/#SIW_Cutoff_Frequency_Work_Backward_From_the_Band_Edge\" >SIW Cutoff Frequency: Work Backward From the Band Edge<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/substrate-integrated-waveguide\/#Via_Fence_PCB_Geometry_Check_the_Sidewall_Before_the_Launch\" >Via Fence PCB Geometry: Check the Sidewall Before the Launch<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/substrate-integrated-waveguide\/#Waveguide_Higher_Order_Mode_Set_the_Upper_Limit_Too\" >Waveguide Higher Order Mode: Set the Upper Limit Too<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/substrate-integrated-waveguide\/#Microstrip_to_SIW_Transition_Match_the_Mode_as_Well_as_the_Feed\" >Microstrip to SIW Transition: Match the Mode as Well as the Feed<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/substrate-integrated-waveguide\/#Substrate_Integrated_Waveguide_Filter_Test_the_Bare_Guide_First\" >Substrate Integrated Waveguide Filter: Test the Bare Guide First<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/substrate-integrated-waveguide\/#Waveguide_Insertion_Loss_Read_Two_Lengths_Before_Blaming_the_Laminate\" >Waveguide Insertion Loss: Read Two Lengths Before Blaming the Laminate<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/substrate-integrated-waveguide\/#FAQ\" >FAQ<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/substrate-integrated-waveguide\/#Prepare_the_SIW_Stackup_and_Coupon_Package\" >Prepare the SIW Stackup and Coupon Package<\/a><\/li><\/ul><\/nav><\/div>\n<div class=\"yzp-no-index\"><\/div><p>Set the cutoff of a substrate integrated waveguide below your lowest operating frequency, then verify that the feed can launch the desired mode across the whole band. A guide that starts propagating at 7.8 GHz is not automatically usable just above 7.8 GHz. For an X-band design, build a plain guide with two transitions before testing the filter or antenna that uses it. That reference tells you whether a narrow usable band comes from the guide, the launches, or the device itself.<\/p>\n<figure><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/substrate-integrated-waveguide-cover.jpg\" alt=\"RF laminate coupon with two parallel rows of plated through holes\" width=\"1200\" height=\"640\" style=\"display:block;max-width:100%;height:auto\"><figcaption>Illustrative SIW test coupon. The two via rows form the side boundaries of the guide.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Substrate_Integrated_Waveguide_SIW_What_the_Via_Rows_Do\"><\/span>Substrate Integrated Waveguide (SIW): What the Via Rows Do<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>An SIW traps the field between copper planes above and below the laminate and between two rows of grounded, plated holes. Those holes approximate the solid sidewalls of a dielectric-filled rectangular waveguide. The dominant TE<sub>10<\/sub>-like mode has one electric-field maximum across the guide width. If you change the row spacing, you change the condition that allows this field pattern to propagate. The <a rel=\"nofollow\" href=\"https:\/\/pure.etsmtl.ca\/en\/publications\/accurate-modeling-wave-mechanisms-and-design-considerations-of-a-\/\">Deslandes and Wu propagation study<\/a> explains why the periodic wall, rather than just the distance between it and the trace, matters.<\/p>\n<figure class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Structure<\/strong><\/td>\n<td><strong>Choose it when<\/strong><\/td>\n<td><strong>Main trade-off<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Conventional microstrip<\/td>\n<td>You need compact planar routing or easy component access.<\/td>\n<td>The field extends outside the laminate; nearby objects and ground geometry matter.<\/td>\n<\/tr>\n<tr>\n<td>Dielectric-filled SIW<\/td>\n<td>You want a confined planar path, cavity filter or slot feed above a defined cutoff.<\/td>\n<td>The laminate and repeated holes affect loss; transitions and lateral area need a budget.<\/td>\n<\/tr>\n<tr>\n<td>Air-filled metal waveguide<\/td>\n<td>Low loss and high power justify a separate mechanical assembly.<\/td>\n<td>Flanges, alignment and enclosure volume add integration work.<\/td>\n<\/tr>\n<\/tbody>\n<\/table><figcaption>SIW vs. microstrip vs. metal waveguide: choose for field confinement and integration, not for a generic loss ranking.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Substrate_Integrated_Waveguide_Design_Start_With_Four_Dimensions\"><\/span>Substrate Integrated Waveguide Design: Start With Four Dimensions<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Define row spacing, pitch, via diameter and laminate thickness before drawing the feed. The transverse center-to-center row spacing <em>a<\/em> largely sets cutoff; the pitch <em>p<\/em> along each row and modeled via diameter <em>d<\/em> influence leakage and effective width. The thickness <em>h<\/em> affects the launch and conductor loss and belongs in the full-wave model, even though it is absent from the simple TE<sub>10<\/sub> cutoff equation.<\/p>\n<p>For a fabricated board, state what your via dimension represents and ask how it maps to drill diameter, finished bore and plated barrel geometry. Model the geometry actually being built instead of changing the drill note and leaving the simulation untouched. Record the laminate construction, design permittivity in the operating band, loss tangent, copper thickness and profile. A nominal Dk from another process or frequency is not a substitute.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"SIW_Cutoff_Frequency_Work_Backward_From_the_Band_Edge\"><\/span>SIW Cutoff Frequency: Work Backward From the Band Edge<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>For an illustrative 10\u201312 GHz guide with assumed relative permittivity 3.50, a target dominant-mode cutoff of 7.8 GHz gives an effective width of about 10.27 mm. The starting relations are <em>f<\/em><sub>c<\/sub> \u2248 <em>c<\/em>\/(2<em>a<\/em><sub>eff<\/sub>\u221a\u03b5<sub>r<\/sub>) and <em>a<\/em><sub>eff<\/sub> \u2248 <em>a<\/em> \u2212 <em>d<\/em>\u00b2\/(0.95<em>p<\/em>). Use meters with <em>c<\/em> in m\/s for frequency; the width correction works with any consistent length unit. These relations appear in the <a rel=\"nofollow\" href=\"https:\/\/www.ece.uvic.ca\/~jbornema\/Conferences\/132-11imws-tb.pdf\">published comparison of equivalent-width models<\/a>.<\/p>\n<p>With a modeled via diameter of 0.45 mm and 0.70 mm pitch, the width correction is about 0.305 mm. Set the initial row spacing near 10.58 mm, not 10.27 mm. This is a starting layout, not a board specification. Sweep the fabrication tolerances and material permittivity in a full-wave model. Do not tune directly at cutoff: propagation is dispersive there, the required match changes quickly, and a small shift can consume the band-edge margin.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Via_Fence_PCB_Geometry_Check_the_Sidewall_Before_the_Launch\"><\/span>Via Fence PCB Geometry: Check the Sidewall Before the Launch<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Tighter spacing generally makes the via wall less leaky, but spacing also has to leave the fabricator enough material between neighboring holes. The example gives <em>d\/p<\/em> \u2248 0.64 and an idealized hole-to-hole gap of 0.25 mm before tolerances. Use that gap to start the DFM conversation, not as the minimum allowable web. Confirm the relevant drill geometry, plating continuity, annular rings and registration. Inspect both fences and the plane connections; a single missing or poorly plated via near a transition can break the symmetry you modeled.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Waveguide_Higher_Order_Mode_Set_the_Upper_Limit_Too\"><\/span>Waveguide Higher Order Mode: Set the Upper Limit Too<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>The upper edge is not simply the highest frequency at which S21 looks good. In the equivalent thin rectangular guide, the TE<sub>20<\/sub> cutoff is approximately twice the TE<sub>10<\/sub> cutoff, or 15.6 GHz in the example. A symmetric launch can reduce coupling to that mode, but a bend, offset or connector asymmetry can excite modes that a symmetric simulation misses. Check the actual structure for higher-mode excitation and periodic-wall effects above the intended passband rather than assuming operation up to 15.6 GHz.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Microstrip_to_SIW_Transition_Match_the_Mode_as_Well_as_the_Feed\"><\/span>Microstrip to SIW Transition: Match the Mode as Well as the Feed<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>A 50-ohm microstrip is only the input. A taper reshapes its field to couple into the SIW mode; its width, length and position must be tuned with the guide and laminate modeled together. See the <a rel=\"nofollow\" href=\"https:\/\/espace2.etsmtl.ca\/id\/eprint\/14127\/\">Deslandes transition design paper<\/a> and the <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/microstrip-pcb\/\">microstrip PCB guide<\/a> for their distinct parts of the problem. Start with a back-to-back pair on a short straight guide. Compare it with a second board that uses the same launches and a longer guide.<\/p>\n<figure><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/substrate-integrated-waveguide-coupon.jpg\" alt=\"Planar RF guide test coupon with coaxial launches at both ends\" width=\"1200\" height=\"640\" style=\"display:block;max-width:100%;height:auto\"><figcaption>Illustrative back-to-back coupon. Match the two boards&#8217; launches and stackup before comparing guide length.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Substrate_Integrated_Waveguide_Filter_Test_the_Bare_Guide_First\"><\/span>Substrate Integrated Waveguide Filter: Test the Bare Guide First<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Do not use the complete filter as the first proof that the feed works. Inductive windows or cavities change coupling and can add passband ripple. First check the transition-only coupon; then add the filter and compare its passband, stopband and return loss. If the plain guide shows the same edge roll-off as the filter, revisit the line and feeds before changing the resonators. For antenna feeds, use the same logic: keep an un-slotted reference to distinguish unwanted line loss from deliberate radiation through a slot.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Waveguide_Insertion_Loss_Read_Two_Lengths_Before_Blaming_the_Laminate\"><\/span>Waveguide Insertion Loss: Read Two Lengths Before Blaming the Laminate<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>A single S21 trace combines guide loss, mismatch and launches. When reflections are low and the two boards share the same launch geometry, the additional loss of the longer coupon divided by the additional length estimates distributed attenuation. For a hypothetical 20 mm and 60 mm pair measured at 11 GHz, 1.2 dB and 2.0 dB of positive insertion loss give (2.0 \u2212 1.2)\/40 = 0.020 dB\/mm. It is not a measurement of laminate Df. If the traces have strong ripple, characterize or de-embed the launches instead of subtracting them as fixed losses.<\/p>\n<figure class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Observed result<\/strong><\/td>\n<td><strong>Check next<\/strong><\/td>\n<td><strong>Decision<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Both coupons roll off near the low edge.<\/td>\n<td>Mode cutoff and low-edge reflection.<\/td>\n<td>Increase cutoff margin or retune the launches based on the evidence.<\/td>\n<\/tr>\n<tr>\n<td>Extra loss increases with length and the match stays good.<\/td>\n<td>Dielectric, copper profile and sidewall leakage.<\/td>\n<td>Investigate the guide before changing the feed.<\/td>\n<\/tr>\n<tr>\n<td>Ripple changes sharply after reconnecting.<\/td>\n<td>Connector seating, calibration and calibration plane.<\/td>\n<td>Fix repeatability before judging the PCB.<\/td>\n<\/tr>\n<\/tbody>\n<\/table><figcaption>Use matched coupons to separate launch errors from distributed attenuation.<\/figcaption><\/figure>\n<p>Define limits for insertion loss, reflection and unwanted response, plus the frequency band and reference planes, before ordering the coupon. <a rel=\"nofollow\" href=\"https:\/\/www.ipc.org\/sites\/default\/files\/test_methods_docs\/2-5_2-5-5-12a.pdf\">IPC-TM-650 2.5.5.12A<\/a> is a reference for printed-board loss measurement methods, not an SIW geometry standard or a universal pass limit.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"FAQ\"><\/span>FAQ<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<h3>Can a ground via fence beside a trace act as an SIW?<\/h3>\n<p>Not by itself. A standard SIW needs two conducting planes and two sidewall rows enclosing a dielectric-filled path, with a launch that excites its guided mode.<\/p>\n<h3>Can I use FR-4 for an SIW prototype?<\/h3>\n<p>It can be useful to test topology. Use the actual laminate&#8217;s frequency-dependent properties and measure the application band before treating the prototype as a low-loss production design.<\/p>\n<h3>Is SIW cutoff the same as the filter&#8217;s lower passband edge?<\/h3>\n<p>No. The guide cutoff governs propagation; the filter edge also depends on its resonators, coupling and transitions. Test the bare guide separately.<\/p>\n<h3>Why not shrink the guide with a higher Dk laminate?<\/h3>\n<p>A higher Dk can shrink the guide for the same cutoff. Recalculate the via geometry and matching, then check loss and tolerance sensitivity rather than scaling only the width.<\/p>\n<h3>Should I model the solder mask?<\/h3>\n<p>Include it where it affects exposed microstrip or transitions, and keep the prototype and model consistent. Do not use a coating correction intended for the feed as a bulk SIW correction.<\/p>\n<h3>Can I validate the design with only a 50-ohm impedance coupon?<\/h3>\n<p>No. That coupon can check the feed&#8217;s impedance, but it does not verify mode conversion, loss or the SIW operating band.<\/p>\n<h3>Do the two guide coupons need equal connector types?<\/h3>\n<p>Yes, and match installation, feed dimensions and calibration. The length difference should be intentional; differences in connector placement or soldering undermine the comparison.<\/p>\n<h3>What should I send for a fabrication review?<\/h3>\n<p>Send the target band, stackup, modeled via geometry, actual drill and plating requirements, the two row dimensions and the drawing for each test coupon.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Prepare_the_SIW_Stackup_and_Coupon_Package\"><\/span>Prepare the SIW Stackup and Coupon Package<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>For a Best Technology fabrication discussion, email <a href=\"mailto:sales@bestpcbs.com\">sales@bestpcbs.com<\/a> with the stackup, allowed drill and layer shifts, and the frequency limits that the two coupons must verify. Identify which dimensions can move and which are fixed by your RF model.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Design a substrate integrated waveguide PCB from cutoff to via pitch, then validate the usable band with a microstrip transition and two test coupons.<\/p>\n","protected":false},"author":32827,"featured_media":39024,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_uf_show_specific_survey":0,"_uf_disable_surveys":false,"footnotes":""},"categories":[174],"tags":[9381,413,9380,9382],"class_list":["post-39025","post","type-post","status-publish","format-standard","hentry","category-bestpcb","tag-microstrip-transition","tag-rf-pcb","tag-substrate-integrated-waveguide","tag-waveguide-cutoff"],"acf":[],"aioseo_notices":[],"aioseo_head":"\n\t\t<!-- All in One SEO 5.0.4 - aioseo.com -->\n\t<meta name=\"description\" content=\"Design a substrate integrated waveguide PCB from cutoff to via pitch, then validate the usable band with a microstrip transition and two test coupons.\" \/>\n\t<meta name=\"robots\" content=\"max-image-preview:large\" \/>\n\t<meta name=\"author\" content=\"mingling, gong\"\/>\n\t<link rel=\"canonical\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/substrate-integrated-waveguide\/\" \/>\n\t\t<meta name=\"generator\" content=\"All in One SEO (AIOSEO) 5.0.4\" \/>\n\t\t<meta property=\"og:locale\" content=\"en_US\" \/>\n\t\t<meta property=\"og:site_name\" content=\"PCB &amp; MCPCB - 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