{"id":39004,"date":"2026-11-14T13:44:12","date_gmt":"2026-11-14T05:44:12","guid":{"rendered":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/mcpcb-solder-void-inspection\/"},"modified":"2026-11-14T13:44:12","modified_gmt":"2026-11-14T05:44:12","slug":"mcpcb-solder-void-inspection","status":"publish","type":"post","link":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/mcpcb-solder-void-inspection\/","title":{"rendered":"MCPCB Solder Voids: Why the Same 15% Can Differ"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_89 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/mcpcb-solder-void-inspection\/#Metal_Core_PCB_Stackup_Trace_the_Heat_Path_First\" >Metal Core PCB Stackup: Trace the Heat Path First<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/mcpcb-solder-void-inspection\/#Exposed_Pad_Soldering_Separate_the_Three_Interfaces\" >Exposed Pad Soldering: Separate the Three Interfaces<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/mcpcb-solder-void-inspection\/#Solder_Void_X_Ray_Read_the_Projection\" >Solder Void X Ray: Read the Projection<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/mcpcb-solder-void-inspection\/#Solder_Void_Percentage_Use_the_Same_Denominator\" >Solder Void Percentage: Use the Same Denominator<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/mcpcb-solder-void-inspection\/#QFN_Thermal_Pad_Voiding_Check_the_Actual_Heat-Transfer_Area\" >QFN Thermal Pad Voiding: Check the Actual Heat-Transfer Area<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/mcpcb-solder-void-inspection\/#3D_X_Ray_PCB_Inspection_Know_When_to_Escalate\" >3D X Ray PCB Inspection: Know When to Escalate<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/mcpcb-solder-void-inspection\/#Solder_Paste_Stencil_Design_Test_One_Change_at_a_Time\" >Solder Paste Stencil Design: Test One Change at a Time<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/mcpcb-solder-void-inspection\/#Thermal_Testing_Verify_the_Margin_Before_Release\" >Thermal Testing: Verify the Margin Before Release<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/mcpcb-solder-void-inspection\/#FAQ\" >FAQ<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/mcpcb-solder-void-inspection\/#Discuss_Your_MCPCB_Assembly_Review\" >Discuss Your MCPCB Assembly Review<\/a><\/li><\/ul><\/nav><\/div>\n<div class=\"yzp-no-index\"><\/div><p>Two power assemblies can both show 15% projected solder voiding and still need different decisions. A single void beneath the main heat-transfer area can interrupt a larger share of that local path than several small voids near its edges. First confirm that both images used the same pad boundary. Then compare void location and size, and verify temperature under the same operating conditions. The percentage alone does not prove a thermal pass.<\/p>\n<figure><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/mcpcb-solder-void-inspection-cover.jpg\" width=\"1200\" height=\"640\" alt=\"Surface-mounted power package on an aluminum-backed circuit board\" style=\"display:block;max-width:100%;height:auto\"><figcaption>The solder joint under the exposed package pad is hidden after assembly. Illustrative bench scene.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Metal_Core_PCB_Stackup_Trace_the_Heat_Path_First\"><\/span>Metal Core PCB Stackup: Trace the Heat Path First<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>On a typical insulated metal substrate, heat flows from the package through its exposed pad and solder, then through the upper conductor and insulating dielectric into the metal base. The base may then transfer heat into a housing through a separate interface. A direct-thermal-path design can bypass the dielectric locally, but it still depends on the solder joint where the component meets the board.<\/p>\n<p>In the motor-controller example below, assume the device is electrically and thermally connected at its exposed pad. Verify that requirement with the device drawing: depending on the part, the pad may be connected to ground, a power node or another specified potential. The metal base must not be treated as that net unless the approved construction makes the connection intentional. The <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/thermal-pad-mcpcb\/\">thermal pad MCPCB guide<\/a> explains those stackup choices.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Exposed_Pad_Soldering_Separate_the_Three_Interfaces\"><\/span>Exposed Pad Soldering: Separate the Three Interfaces<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>The exposed package pad is not a soft thermal gap pad, and the solder underneath it is not the board-to-housing interface. A hot device can result from poor solder contact, the board dielectric, or uneven enclosure contact. Changing stencil openings will not fix an uneven heatsink fit. When troubleshooting, record device power and mounting conditions before comparing X-rays from two assemblies.<\/p>\n<p>Use the exact package drawing and the supplier\u2019s attachment guidance to define the required soldered region and net connection. Board copper outside the intended joint does not belong in the void calculation. An edge fillet or a good visual inspection does not establish coverage beneath the package.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Solder_Void_X_Ray_Read_the_Projection\"><\/span>Solder Void X Ray: Read the Projection<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>A top-down 2D X-ray combines attenuation along the beam. The inspection software can outline regions with less solder within a specified joint area. The resulting image is useful for screening, but does not locate a void in depth or prove that the two solder interfaces are fully wetted. Copper, features on the opposite side, and the metal base can change contrast.<\/p>\n<p>Use the same orientation, magnification and segmentation settings when comparing units. Save the unannotated image plus the measured overlay. If bright spots track vias or repeat in features outside the pad, review the board data and image settings before counting them as voids. Document what the image could not separate rather than forcing a percentage for an unreadable region.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Solder_Void_Percentage_Use_the_Same_Denominator\"><\/span>Solder Void Percentage: Use the Same Denominator<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>If the agreed evaluation region covers 20 mm\u00b2 and the combined projected void area covers 3 mm\u00b2, the total is <strong>15%<\/strong>. Count overlapping projections only once in that total. It is an area fraction, not a volume fraction, and it cannot simply be multiplied by junction-to-ambient thermal resistance.<\/p>\n<p>For a hypothetical central region of 6 mm\u00b2, one 3 mm\u00b2 void entirely inside it would cover 50% of that region. Six voids of 0.5 mm\u00b2 outside the same region also give 15% overall but 0% inside the defined region. These assumed values show why the denominator and location matter; they are not factory data or acceptance criteria. Define a critical region using the package\u2019s actual heat path or other approved evidence, not an arbitrary center circle.<\/p>\n<table>\n<caption>Projected void percentage vs location in two example units<\/caption>\n<thead>\n<tr>\n<th scope=\"col\">Finding<\/th>\n<th scope=\"col\">Unit A<\/th>\n<th scope=\"col\">Unit B<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Total projected void area<\/td>\n<td>3 of 20 mm\u00b2 (15%)<\/td>\n<td>3 of 20 mm\u00b2 (15%)<\/td>\n<\/tr>\n<tr>\n<td>Largest single void<\/td>\n<td>3 mm\u00b2<\/td>\n<td>0.5 mm\u00b2<\/td>\n<\/tr>\n<tr>\n<td>Overlap with defined heat-transfer region<\/td>\n<td>3 of 6 mm\u00b2 (50%)<\/td>\n<td>0 of 6 mm\u00b2 (0%)<\/td>\n<\/tr>\n<tr>\n<td>Next investigation<\/td>\n<td>Verify central coverage and temperature margin.<\/td>\n<td>Check edge wetting and confirm thermal performance.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2><span class=\"ez-toc-section\" id=\"QFN_Thermal_Pad_Voiding_Check_the_Actual_Heat-Transfer_Area\"><\/span>QFN Thermal Pad Voiding: Check the Actual Heat-Transfer Area<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>A large central void may be of greater concern if heat enters the pad mainly there. But an edge void can matter if it overlaps a critical portion of the electrical termination, disrupts solder wetting, or is subject to mechanical loading. The package drawing and thermal evidence, not the image center, determine which region deserves a separate evaluation. The <a href=\"https:\/\/www.ipc.org\/system\/files\/technical_resource\/E15%26S31_02.pdf\" rel=\"nofollow\">Reliability Study of Bottom Terminated Components<\/a> examines voiding and heat transfer on specific test assemblies. Its results are not a release limit for the devices in your build.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"3D_X_Ray_PCB_Inspection_Know_When_to_Escalate\"><\/span>3D X Ray PCB Inspection: Know When to Escalate<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<figure><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/mcpcb-solder-void-inspection-scope.jpg\" width=\"1200\" height=\"640\" alt=\"Shielded electronics X-ray inspection equipment next to a sample board\" style=\"display:block;max-width:100%;height:auto\"><figcaption>Select the inspection method to resolve the uncertainty. Illustrative equipment scene, not a measured radiograph.<\/figcaption><\/figure>\n<p>Use an additional angled image if overlap obscures the pad outline or a nearby feature. If the depth of an indication changes the disposition, ask whether computed tomography can resolve it on this stackup; dense metal may limit usable contrast. A targeted destructive cross-section can verify the interface in the chosen plane, but cannot represent the entire joint on its own.<\/p>\n<table>\n<caption>2D X-ray vs CT vs cross-section<\/caption>\n<thead>\n<tr>\n<th scope=\"col\">Method<\/th>\n<th scope=\"col\">Best use<\/th>\n<th scope=\"col\">Limit<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>2D X-ray<\/td>\n<td>Compare projected area and distribution across units.<\/td>\n<td>Overlapping features can mask depth or boundaries.<\/td>\n<\/tr>\n<tr>\n<td>CT<\/td>\n<td>Separate features through depth when resolution permits.<\/td>\n<td>Metal and acquisition conditions affect visibility.<\/td>\n<\/tr>\n<tr>\n<td>Cross-section<\/td>\n<td>Inspect wetting, interfaces and thickness in a chosen slice.<\/td>\n<td>Destructive and local, not a full-pad map.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2><span class=\"ez-toc-section\" id=\"Solder_Paste_Stencil_Design_Test_One_Change_at_a_Time\"><\/span>Solder Paste Stencil Design: Test One Change at a Time<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Segmented apertures can change how paste deposits coalesce and how gases escape as solder melts. Do not infer the correct paste coverage from the final void percentage: printed paste and reflowed solder are different measurements. Start with the exact package guidance and verify the actual deposits with solder paste inspection before reflow.<\/p>\n<p>When Unit A repeatedly shows a central void, compare the baseline against one proposed aperture layout with the same paste, package lot, profile and fixture. If the void does not respond, investigate wetting or the measured reflow profile rather than reducing paste until the X-ray looks better. Confirm that the change does not create opens or insufficient attachment at other joints. <a href=\"https:\/\/www.ti.com\/lit\/an\/slua271c\/slua271c.pdf\" rel=\"nofollow\">TI SLUA271C<\/a> explains exposed-pad stencil considerations for QFN and SON.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Thermal_Testing_Verify_the_Margin_Before_Release\"><\/span>Thermal Testing: Verify the Margin Before Release<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Test representative assemblies at the specified worst-case operating point. Hold power, ambient temperature, heatsink contact, airflow and measurement method constant between samples. Use the package\u2019s characterized temperature proxy or another approved junction-temperature method; the temperature of the aluminum base alone is not a junction measurement. If Unit A shows worse margin, verify the finding across more units before assigning causality. If both pass, still apply all agreed workmanship and electrical requirements.<\/p>\n<p>A release record should include the PCB and stencil revisions, lot, pad evaluation boundary, total and largest void, location rule, image and thermal test record. <a href=\"https:\/\/www.ipc.org\/TOC\/IPC-7093A-toc.pdf\" rel=\"nofollow\">IPC-7093A<\/a> covers design and assembly considerations for bottom-termination components. Use the applicable purchase requirements and verified package guidance to define the inspection method and limits; do not adopt a blanket percentage from an unrelated package.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"FAQ\"><\/span>FAQ<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<h3>Does 15% voiding always pass?<\/h3>\n<p>No. It is an example, not a threshold. Apply the written limits and check the measurement method.<\/p>\n<h3>Does more paste always reduce voiding?<\/h3>\n<p>No. Changing deposit coverage can change gas escape, component seating and other joints. Test a controlled change.<\/p>\n<h3>Is a hot QFN proof of poor solder coverage?<\/h3>\n<p>No. Check electrical dissipation and board-to-housing contact as well as the hidden joint.<\/p>\n<h3>Can a 2D image show where a void sits through the joint thickness?<\/h3>\n<p>Not by itself. A suitable additional view, CT or a cross-section can address the specific uncertainty.<\/p>\n<h3>Can I skip paste on a difficult center pad?<\/h3>\n<p>Only if the package documentation and approved design permit a different attachment. A ground or cooling function may depend on it.<\/p>\n<h3>Can I compare images from different inspection programs?<\/h3>\n<p>Only after verifying that the boundary, calibration and segmentation are equivalent for that joint.<\/p>\n<h3>Is a central void always worse than an edge void?<\/h3>\n<p>No. Risk depends on how heat, current and stress pass through the actual joint.<\/p>\n<h3>Does passing the thermal test clear an X-ray reject?<\/h3>\n<p>No. Treat thermal performance and agreed inspection criteria as separate release gates.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Discuss_Your_MCPCB_Assembly_Review\"><\/span>Discuss Your MCPCB Assembly Review<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>For a Best Technology review, send the package drawing, MCPCB stackup, pad and stencil files, sample X-rays and test conditions to <a href=\"mailto:sales@bestpcbs.com\">sales@bestpcbs.com<\/a>. Identify the heat path and the decision the inspection needs to support.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Compare MCPCB thermal-pad voids by size and location. Learn what X-ray can prove, when to use a second view, and how to verify thermal performance.<\/p>\n","protected":false},"author":32827,"featured_media":39002,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_uf_show_specific_survey":0,"_uf_disable_surveys":false,"footnotes":""},"categories":[174],"tags":[34,9368,5195],"class_list":["post-39004","post","type-post","status-publish","format-standard","hentry","category-bestpcb","tag-mcpcb","tag-solder-voids","tag-x-ray-inspection"],"acf":[],"aioseo_notices":[],"aioseo_head":"\n\t\t<!-- All in One SEO 5.0.4 - aioseo.com -->\n\t<meta name=\"description\" content=\"Compare MCPCB thermal-pad voids by size and location. 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