{"id":38956,"date":"2026-11-13T18:08:53","date_gmt":"2026-11-13T10:08:53","guid":{"rendered":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/adc-anti-aliasing-filter\/"},"modified":"2026-11-13T18:08:53","modified_gmt":"2026-11-13T10:08:53","slug":"adc-anti-aliasing-filter","status":"publish","type":"post","link":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/adc-anti-aliasing-filter\/","title":{"rendered":"ADC Anti-Aliasing Filter Guide: From Bandwidth to Bench Test"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_89 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/adc-anti-aliasing-filter\/#Why_use_an_anti_aliasing_filter_before_ADC_sampling\" >Why use an anti aliasing filter before ADC sampling?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/adc-anti-aliasing-filter\/#How_to_use_the_aliasing_frequency_formula\" >How to use the aliasing frequency formula<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/adc-anti-aliasing-filter\/#How_to_choose_an_anti_aliasing_filter_cutoff_frequency\" >How to choose an anti aliasing filter cutoff frequency<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/adc-anti-aliasing-filter\/#Choosing_the_low_pass_filter_order\" >Choosing the low pass filter order<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/adc-anti-aliasing-filter\/#SAR_ADC_anti_aliasing_filter_Check_acquisition_settling\" >SAR ADC anti aliasing filter: Check acquisition settling<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/adc-anti-aliasing-filter\/#Sigma_delta_ADC_anti_aliasing_filter_Which_rate_matters\" >Sigma delta ADC anti aliasing filter: Which rate matters?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/adc-anti-aliasing-filter\/#Anti_aliasing_filter_example_When_a_higher_sample_rate_changes_the_choice\" >Anti aliasing filter example: When a higher sample rate changes the choice<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/adc-anti-aliasing-filter\/#How_to_verify_an_ADC_anti_aliasing_filter_design\" >How to verify an ADC anti aliasing filter design<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/adc-anti-aliasing-filter\/#FAQ\" >FAQ<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/adc-anti-aliasing-filter\/#Technical_references\" >Technical references<\/a><\/li><\/ul><\/nav><\/div>\n<div class=\"yzp-no-index\"><\/div><p>An ADC anti-aliasing filter attenuates unwanted analog frequencies <strong>before<\/strong> the analog-to-digital converter samples them. Choose it using two requirements: how much of the wanted signal must pass, and how small an unwanted signal must be after it folds into that band. Setting the cutoff below half the sampling rate is not enough by itself.<\/p>\n<p>Follow a hypothetical sensor channel that measures DC to 1 kHz at 10 kS\/s. A switching tone appears at 9.4 kHz. The challenge is to preserve the sensor signal, suppress the false reading caused by that tone, and still let the ADC input settle before each conversion.<\/p>\n<figure><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/adc-anti-aliasing-filter.jpg\" width=\"1200\" height=\"800\" style=\"max-width:100%;height:auto\" alt=\"Small data acquisition evaluation board on a laboratory bench\"><figcaption>Illustrative rendering. The analog filter and the ADC input must be designed and verified together.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Why_use_an_anti_aliasing_filter_before_ADC_sampling\"><\/span>Why use an anti aliasing filter before ADC sampling?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Once sampling folds an interfering tone onto a wanted frequency, the samples alone cannot tell which analog signal produced it. A digital filter can remove unwanted frequencies that remain outside the wanted digital band. It cannot separate two signals that now occupy the same frequency there.<\/p>\n<p>For a baseband sensor, define the highest frequency you need to keep, then identify likely interferers, including switching clocks, motor drives or nearby signals. The analog filter goes before the sampling point. For general circuit behavior and topology background, see the <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/low-pass-filter-circuit\/\">low-pass filter circuit guide<\/a>.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"How_to_use_the_aliasing_frequency_formula\"><\/span>How to use the aliasing frequency formula<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>At 10 kS\/s, a 9.4 kHz input tone appears at <strong>600 Hz<\/strong>, inside this sensor&#8217;s 0\u20131 kHz band. For a single real tone, calculate the folded frequency as |f<sub>in<\/sub> \u2212 kf<sub>s<\/sub>|, choosing the integer k that puts the result between zero and f<sub>s<\/sub>\/2. Use the same frequency units for both inputs.<\/p>\n<p>Here k = 1, so |9.4 \u2212 10| kHz = 0.6 kHz. A tone above Nyquist does not always land inside the wanted band. For example, at the same sample rate a 6 kHz tone lands at 4 kHz. A digital low-pass filter can reject that component, provided the analog input has not overloaded and no other unwanted products land in band. Check the spectrum around multiples of the actual sampling rate, not just the region immediately above Nyquist.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"How_to_choose_an_anti_aliasing_filter_cutoff_frequency\"><\/span>How to choose an anti aliasing filter cutoff frequency<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Choose the cutoff by testing both the allowed loss at the passband edge and the required attenuation at the interfering frequency. In this teaching example, the wanted signal may lose at most 0.5 dB at 1 kHz. A 100 mV RMS interferer at 9.4 kHz must be reduced to at most 1 mV RMS: the filter therefore needs at least <strong>40 dB<\/strong> of attenuation there, assuming no downstream gain change or overload.<\/p>\n<figure class=\"wp-block-table\">\n<table style=\"width:100%;table-layout:fixed;overflow-wrap:anywhere\">\n<tbody>\n<tr>\n<td><strong>Design input<\/strong><\/td>\n<td><strong>Example<\/strong><\/td>\n<td><strong>Where to confirm it<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Wanted band and allowed loss<\/td>\n<td>DC\u20131 kHz; \u22640.5 dB loss at 1 kHz<\/td>\n<td>Sensor and system accuracy budget<\/td>\n<\/tr>\n<tr>\n<td>Actual sample rate<\/td>\n<td>10 kS\/s<\/td>\n<td>Converter clock and firmware configuration<\/td>\n<\/tr>\n<tr>\n<td>Interferer and permitted residual<\/td>\n<td>100 mV RMS at 9.4 kHz; \u22641 mV RMS<\/td>\n<td>Input spectrum and allowable in-band error<\/td>\n<\/tr>\n<tr>\n<td>Acquisition window<\/td>\n<td>Device and configuration specific<\/td>\n<td>ADC timing table and input model<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<p>For a single tone, required attenuation in decibels is 20 log<sub>10<\/sub>(input amplitude \u00f7 allowed residual amplitude). Use matching units and amplitude conventions. For broadband noise, one spot-frequency check is not enough: evaluate the filtered noise that folds into the measurement band.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Choosing_the_low_pass_filter_order\"><\/span>Choosing the low pass filter order<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>In the 10 kS\/s example, a single ideal RC pole cannot meet both limits. Solving the one-pole equation for each limit gives incompatible cutoff ranges: at least 2.86 kHz to preserve the 1 kHz signal, but no more than about 94 Hz to reject the 9.4 kHz tone by 40 dB. Simply swapping the capacitor cannot fix this trade-off. At a 1.5 kHz cutoff, a single pole loses about 1.60 dB at 1 kHz and gives only 16.05 dB of attenuation at 9.4 kHz.<\/p>\n<p>An ideal third-order Butterworth response at the same 1.5 kHz cutoff gives about 0.37 dB loss at 1 kHz and 47.8 dB attenuation at 9.4 kHz. These are calculated values, not a measured circuit. For an ideal Butterworth response of order n, positive attenuation at frequency f is 10 log<sub>10<\/sub>[1 + (f\/f<sub>c<\/sub>)<sup>2n<\/sup>]. The ratios are unitless; f<sub>c<\/sub> is the \u22123 dB frequency. Three identical unbuffered RC sections do not automatically give this response.<\/p>\n<figure class=\"wp-block-table\">\n<table style=\"width:100%;table-layout:fixed;overflow-wrap:anywhere\">\n<tbody>\n<tr>\n<td><strong>Approach<\/strong><\/td>\n<td><strong>Use when<\/strong><\/td>\n<td><strong>Verify<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Single passive RC<\/td>\n<td>Measured interference and the transition band allow gentle roll-off<\/td>\n<td>Passband loss, stopband and source\/load effects<\/td>\n<\/tr>\n<tr>\n<td>Higher-order analog filter<\/td>\n<td>One pole cannot meet both limits at the available sample rate<\/td>\n<td>Component tolerances, amplifier behavior and step settling<\/td>\n<\/tr>\n<tr>\n<td>Oversample and digitally filter<\/td>\n<td>The converter and processor have throughput headroom<\/td>\n<td>Analog alias bands at the higher sample rate and rejection before decimation<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<h2><span class=\"ez-toc-section\" id=\"SAR_ADC_anti_aliasing_filter_Check_acquisition_settling\"><\/span>SAR ADC anti aliasing filter: Check acquisition settling<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>A successive approximation register (SAR) ADC often connects an internal sampling capacitor to the input during acquisition. The driver must restore the input to within the allocated error before that window closes. An RC network next to the input may reduce sampling transients, but its bandwidth can be too high to provide the required anti-alias attenuation.<\/p>\n<p>Find the acquisition time, source-drive guidance and input model in the exact ADC data sheet. Then check the driver, isolation resistor, external capacitor and sampling switch together for the largest expected step, including a channel change if the input is multiplexed. As a simple first-order screening calculation, a full-scale step settling to half an ideal LSB on a 12-bit ADC takes at least ln(8,192), or about 9.01 time constants. This calculation assumes exponential settling and gives no allowance for noise or other errors. It is not a substitute for the converter&#8217;s switched input model.<\/p>\n<figure><img decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/sar-adc-input-network.jpg\" width=\"1200\" height=\"800\" style=\"max-width:100%;height:auto\" loading=\"lazy\" alt=\"Small surface mount passives next to an integrated circuit on an evaluation board\"><figcaption>Illustrative rendering. Use the converter&#8217;s input circuit and timing table to check settling, not the appearance of the passive components.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Sigma_delta_ADC_anti_aliasing_filter_Which_rate_matters\"><\/span>Sigma delta ADC anti aliasing filter: Which rate matters?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Start with the internal modulator sampling rate and the data sheet&#8217;s combined analog and digital response, not just the output data rate. A sigma-delta converter may oversample internally and use digital filtering to reject much of the unwanted content before reducing its output rate. Interference near vulnerable analog sampling bands still needs attention.<\/p>\n<p>Read the frequency-response plot and note the selected filter mode, output data rate and any rejection holes or repeated response near the modulator rate. For multiplexed sensors, also check digital filter settling after a channel change. A mode that offers excellent steady-state rejection may take too long to settle for your channel scan.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Anti_aliasing_filter_example_When_a_higher_sample_rate_changes_the_choice\"><\/span>Anti aliasing filter example: When a higher sample rate changes the choice<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Change only one condition in the sensor example: sample at 20 kS\/s rather than 10 kS\/s. The 9.4 kHz tone now lies below the new 10 kHz Nyquist limit and remains at 9.4 kHz in the initial samples. If the ADC and analog driver tolerate it without overload or distortion, the digital filter can reject it before a lower-rate output is produced.<\/p>\n<p>That change does not make the analog filter optional. A different tone at 19.4 kHz would now fold to 600 Hz. Measure or bound interference near the new alias bands and recalculate the analog rejection requirement. If the ADC cannot support the higher sample rate with adequate acquisition time, keep the lower rate and evaluate the higher-order analog option instead.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"How_to_verify_an_ADC_anti_aliasing_filter_design\"><\/span>How to verify an ADC anti aliasing filter design<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Run two separate bench checks: one for frequency rejection, another for settling. Apply a known tone at the passband edge and then an out-of-band tone predicted to fold into the wanted band. Compare the raw ADC spectra against the loss and residual limits. In the example, the checks are 0.5 dB maximum loss at 1 kHz and no more than 1 mV RMS equivalent at 600 Hz for the specified 9.4 kHz injection.<\/p>\n<p>Next, apply the largest expected input or channel step and verify the first accepted conversion against the allocated error. Record source amplitude and impedance, sample rate, gain, test window and channel sequence. If the alias test passes but the step fails, review acquisition and driver settling rather than adding more filtering. If the step passes but a tone folds into band, inspect the source spectrum and actual analog attenuation. Repeat under the operating conditions that matter to the product.<\/p>\n<figure><img decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/adc-alias-rejection-test.jpg\" width=\"1200\" height=\"800\" style=\"max-width:100%;height:auto\" loading=\"lazy\" alt=\"Evaluation board beside signal generation and measurement equipment\"><figcaption>Illustrative rendering. Measure both out-of-band rejection and the ADC&#8217;s response after an input step.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"FAQ\"><\/span>FAQ<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<h3>Is an anti-aliasing filter the same as a noise filter?<\/h3>\n<p>Not always. A noise filter may target any unwanted band. An anti-aliasing filter specifically attenuates analog signals that would fold into a band you need to measure. One circuit can do both if its response meets both sets of requirements.<\/p>\n<h3>Is the Nyquist frequency a good cutoff setting?<\/h3>\n<p>Not by itself. At the cutoff, a standard Butterworth response attenuates the signal by only about 3 dB. Decide which interferers can fold into your measurement band and calculate the attenuation needed at their original frequencies.<\/p>\n<h3>Can I fix an aliased reading by averaging more samples?<\/h3>\n<p>Not reliably. Averaging may reduce some noise, but an interfering tone that has already folded onto a frequency you need cannot be separated from a real signal there merely by averaging.<\/p>\n<h3>Why do two RC pairs with the same cutoff behave differently?<\/h3>\n<p>The same RC product gives the same ideal unloaded pole, but different resistor and capacitor values change source loading, thermal noise, amplifier drive and sampling recovery. Check the actual connected circuit rather than assuming equal cutoff means equal performance.<\/p>\n<h3>Can a passing sine sweep prove the ADC input settles?<\/h3>\n<p>No. A frequency sweep checks a steady-state response. A large step or channel change can expose acquisition errors even when the sweep meets the passband and stopband targets.<\/p>\n<h3>Can software replace the filter before I decimate?<\/h3>\n<p>Software can reject frequencies that were captured without already folding into the wanted band. Apply the appropriate digital filter before downsampling, but first verify what aliases at the original analog sample rate.<\/p>\n<h3>Why does a suspected alias move when I change the sample rate?<\/h3>\n<p>A folded tone depends on the sampling rate as well as its original frequency. A small controlled change in sample rate can help distinguish it from a genuine baseband tone. Confirm the result by checking the analog input spectrum; a moving line alone does not identify the source.<\/p>\n<h3>What should I include in an ADC board review?<\/h3>\n<p>Include the converter and driver part numbers, schematic, actual sampling and acquisition timing, desired signal band, measured or bounded interferers, error budget and test results. Flag whether a problem is spectral rejection, step settling or both.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Technical_references\"><\/span>Technical references<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<ul>\n<li><a rel=\"nofollow\" href=\"https:\/\/www.ti.com\/lit\/an\/sbaa282b\/sbaa282b.pdf\">Texas Instruments: Fixed-cutoff anti-aliasing filter for a SAR ADC<\/a><\/li>\n<li><a rel=\"nofollow\" href=\"https:\/\/www.analog.com\/en\/resources\/analog-dialogue\/articles\/practical-filter-design-precision-adcs.html\">Analog Devices: Filter design for precision ADCs<\/a><\/li>\n<li><a rel=\"nofollow\" href=\"https:\/\/www.analog.com\/en\/resources\/analog-dialogue\/articles\/front-end-amp-and-rc-filter-design.html\">Analog Devices: SAR ADC driver and RC settling<\/a><\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>Design an ADC anti-aliasing filter by checking signal bandwidth, aliased interference, filter order and SAR input settling. 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