{"id":38922,"date":"2026-11-13T14:42:18","date_gmt":"2026-11-13T06:42:18","guid":{"rendered":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/embedded-capacitance-pcb\/"},"modified":"2026-11-13T14:42:18","modified_gmt":"2026-11-13T06:42:18","slug":"embedded-capacitance-pcb","status":"publish","type":"post","link":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/embedded-capacitance-pcb\/","title":{"rendered":"Embedded Capacitance PCB: When Plane Pairs Help Decoupling"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_89 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/embedded-capacitance-pcb\/#embedded_capacitance_pcb\" >embedded capacitance pcb<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/embedded-capacitance-pcb\/#embedded_capacitance_material\" >embedded capacitance material<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/embedded-capacitance-pcb\/#pcb_power_plane_capacitance\" >pcb power plane capacitance<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/embedded-capacitance-pcb\/#parallel_plate_capacitance_formula\" >parallel plate capacitance formula<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/embedded-capacitance-pcb\/#pcb_decoupling_capacitor\" >pcb decoupling capacitor<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/embedded-capacitance-pcb\/#pcb_decoupling_capacitor_placement\" >pcb decoupling capacitor placement<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/embedded-capacitance-pcb\/#pcb_power_distribution_network\" >pcb power distribution network<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/embedded-capacitance-pcb\/#pcb_plane_capacitance_calculator\" >pcb plane capacitance calculator<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/embedded-capacitance-pcb\/#FAQ\" >FAQ<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/embedded-capacitance-pcb\/#References\" >References<\/a><\/li><\/ul><\/nav><\/div>\n<div class=\"yzp-no-index\"><\/div><p>An embedded capacitance PCB uses overlapping conductors separated by a dielectric to provide capacitance inside the stackup. A closely spaced power and ground pair can help at high frequencies, but its available capacitance depends on overlap area and dielectric thickness. Keep discrete capacitors where the power rail needs more charge storage or frequency coverage.<\/p>\n<figure class=\"wp-block-image\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/embedded-capacitance-pcb.jpg\" width=\"1200\" height=\"800\" style=\"max-width:100%;height:auto\" alt=\"Polished multilayer PCB cross-section with adjacent copper layers\"><figcaption>Illustrative view. Validate the actual stackup and power delivery network by measurement.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"embedded_capacitance_pcb\"><\/span>embedded capacitance pcb<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Distributed plane capacitance comes from the electric field between the planes. It differs from burying a finished discrete capacitor inside the board. The first approach spreads capacitance across copper area; the second uses a component at a particular location and needs a different fabrication and verification plan.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"embedded_capacitance_material\"><\/span>embedded capacitance material<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Read the supplied material grade, dielectric thickness tolerance, effective permittivity and test conditions together. A thinner dielectric may provide more capacitance per area, but it also changes isolation, process handling and cost. Do not specify high permittivity without checking whether the proposed layer will also serve as a controlled reference for signals.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"pcb_power_plane_capacitance\"><\/span>pcb power plane capacitance<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Count the area where the intended two nets actually overlap. An unrelated copper island does not belong in the same total. Split planes and voids can cut the effective area and force a current detour. Start from the final layout rather than multiplying the entire board outline by a supplier&#8217;s capacitance density.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"parallel_plate_capacitance_formula\"><\/span>parallel plate capacitance formula<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>For an ideal approximation, C = \u03b5\u2080 \u03b5\u1d63 A\/d. With assumed \u03b5\u1d63 = 4, A = 20 cm\u00b2 and d = 25 \u00b5m, the estimate is 2.83 nF. With the same material and area at 50 \u00b5m, the estimate falls to 1.42 nF. This ignores fringing, dispersion, losses and distributed resonance. It is not a measured value or a release specification.<\/p>\n<figure class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Variable<\/strong><\/td>\n<td><strong>Example<\/strong><\/td>\n<td><strong>Use actual<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Overlap area<\/td>\n<td>20 cm\u00b2<\/td>\n<td>Released plane artwork<\/td>\n<\/tr>\n<tr>\n<td>Dielectric thickness<\/td>\n<td>25 \u00b5m<\/td>\n<td>Pressed thickness<\/td>\n<\/tr>\n<tr>\n<td>Relative permittivity<\/td>\n<td>4, assumed<\/td>\n<td>Grade and test data<\/td>\n<\/tr>\n<tr>\n<td>Ideal capacitance<\/td>\n<td>2.83 nF<\/td>\n<td>Model and verify<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<h2><span class=\"ez-toc-section\" id=\"pcb_decoupling_capacitor\"><\/span>pcb decoupling capacitor<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<h3>Embedded plane capacitance vs discrete capacitors<\/h3>\n<p>Compare each option at the load and over the relevant frequency range. A discrete ceramic capacitor can offer greater nominal capacitance, but pads, vias and placement add connection inductance. A plane pair does not eliminate the inductance between the load pins and the plane.<\/p>\n<figure class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Option<\/strong><\/td>\n<td><strong>Useful for<\/strong><\/td>\n<td><strong>Verify<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Close plane pair<\/td>\n<td>Distributed high-frequency response<\/td>\n<td>Overlap, access and modes<\/td>\n<\/tr>\n<tr>\n<td>Local ceramic capacitor<\/td>\n<td>Charge near a device<\/td>\n<td>Bias derating and mounting<\/td>\n<\/tr>\n<tr>\n<td>Bulk capacitor<\/td>\n<td>Slower load changes<\/td>\n<td>Regulator and transient response<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<figure class=\"wp-block-image\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/pcb-decoupling-capacitors.jpg\" width=\"1200\" height=\"800\" style=\"max-width:100%;height:auto\" alt=\"Ceramic capacitors mounted near a processor package\"><figcaption>Illustrative view. Validate the actual stackup and power delivery network by measurement.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"pcb_decoupling_capacitor_placement\"><\/span>pcb decoupling capacitor placement<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Start from the power pin and return pin, not from the empty area closest in the placement view. Compare the full current loop into the layer pair and into the discrete capacitor. Check via placement, shared neck-downs and the return plane. A physically close capacitor with a long return loop can deliver less useful high-frequency decoupling than expected.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"pcb_power_distribution_network\"><\/span>pcb power distribution network<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Check rail impedance and load response before removing parts. Simulate the regulator, bulk and local capacitors, connections and planes over the relevant range. Changing capacitance can move peaks as well as lower impedance in some bands. See the <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/pdn-capacitor-antiresonance\/\">PDN antiresonance guide<\/a> for interpreting an unexpected peak.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"pcb_plane_capacitance_calculator\"><\/span>pcb plane capacitance calculator<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Use the calculator for a feasibility estimate, then compare it with measurement. In the example, even doubling the estimate would not by itself justify removing a larger capacitor at a device. Test impedance at representative load access points and verify transient droop under defined load changes. Use the same observation point when comparing the baseline with the thin-plane design.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"FAQ\"><\/span>FAQ<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<h3>Does the total board area count?<\/h3>\n<p>No. Count copper overlap for the specific rail and its reference. Voids and isolated islands can substantially reduce usable overlap.<\/p>\n<h3>Can embedded capacitance replace bulk capacitors?<\/h3>\n<p>Generally not on the basis of geometry alone. Bulk capacitors serve a different charge and frequency range; verify regulator stability and measured load response before changing them.<\/p>\n<h3>Does thin dielectric guarantee lower impedance at every frequency?<\/h3>\n<p>No. Plane dimensions, access inductance and resonances can dominate certain frequencies. Measure or model the loaded network.<\/p>\n<h3>Does the formula give usable capacitance at any frequency?<\/h3>\n<p>No. It treats the geometry as an ideal lumped capacitor. Use a distributed model or appropriate measurement where propagation and resonances matter.<\/p>\n<h3>Does permittivity have to be the same for every layer?<\/h3>\n<p>No. Check the assigned material and test conditions per layer. A value from another laminate is not a substitute for the actual construction.<\/p>\n<h3>What should go into the fabrication request?<\/h3>\n<p>Include the approved material grade, thickness tolerance, layer order, reference nets and any coupons or electrical verification requirements.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"References\"><\/span>References<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><a href=\"https:\/\/www.analog.com\/en\/resources\/analog-dialogue\/studentzone\/studentzone-may-2017.html\" rel=\"nofollow\">Analog Devices: Decoupling Continued<\/a>.<\/p>\n<p>Send the proposed stackup, rail targets and routing layers to <a href=\"mailto:sales@bestpcbs.com\">Best Technology<\/a> for fabrication review.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Estimate PCB plane capacitance, compare it with discrete decoupling, and verify whether a thin dielectric helps your power delivery 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