{"id":38789,"date":"2026-11-10T20:36:23","date_gmt":"2026-11-10T12:36:23","guid":{"rendered":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/broadside-coupled-stripline-layer-offset\/"},"modified":"2026-11-10T20:40:49","modified_gmt":"2026-11-10T12:40:49","slug":"broadside-coupled-stripline-layer-offset","status":"publish","type":"post","link":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/broadside-coupled-stripline-layer-offset\/","title":{"rendered":"Broadside Coupled Stripline Guide: Check Layer Offset"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_89 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/broadside-coupled-stripline-layer-offset\/#broadside_coupled_stripline\" >broadside coupled stripline<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/broadside-coupled-stripline-layer-offset\/#edge_coupled_vs_broadside_coupled\" >edge coupled vs broadside coupled<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/broadside-coupled-stripline-layer-offset\/#broadside_coupled_stripline_calculator\" >broadside coupled stripline calculator<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/broadside-coupled-stripline-layer-offset\/#Differential_stripline_impedance_formula\" >Differential stripline impedance formula<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/broadside-coupled-stripline-layer-offset\/#pcb_layer_registration\" >pcb layer registration<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/broadside-coupled-stripline-layer-offset\/#differential_pair_skew\" >differential pair skew<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/broadside-coupled-stripline-layer-offset\/#differential_impedance_measurement\" >differential impedance measurement<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/broadside-coupled-stripline-layer-offset\/#pcb_layer_to_layer_registration_tolerance\" >pcb layer to layer registration tolerance<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/broadside-coupled-stripline-layer-offset\/#FAQ\" >FAQ<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/broadside-coupled-stripline-layer-offset\/#References\" >References<\/a><\/li><\/ul><\/nav><\/div>\n<div class=\"yzp-no-index\"><\/div><p>Use broadside coupled stripline when routing the two conductors on adjacent inner layers solves a real routing constraint, and only if the pair still meets its impedance requirement at the fabricator\u2019s expected layer offset. If side-by-side routing fits, start with edge-coupled stripline: moving both conductors onto one signal layer removes one critical dependency on alignment between two signal layers.<\/p>\n<p>Suppose a 100 \u03a9 differential link has to cross a narrow channel between connector escapes. The stacked pair fits in the layout, but the nominal impedance alone will not tell you whether it will work across production variation. Compare the two structures with the same channel requirements, then use a representative coupon and a separate launch check.<\/p>\n<figure class=\"wp-block-image\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/broadside-coupled-stripline.jpg\" alt=\"Physical-style demonstration of two internal copper strips stacked between reference planes\" width=\"1200\" height=\"600\" style=\"max-width:100%;height:auto;\"><figcaption>Illustration: The copper traces run one above the other; the artwork is not to scale and does not define a buildable stackup.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"broadside_coupled_stripline\"><\/span>broadside coupled stripline<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Broadside coupled stripline puts the pair\u2019s two conductors on separate signal layers between reference planes. Their wide faces overlap through the dielectric, the insulating material between them. The pair is still a transmission line: the reference planes, the conductors, and the dielectric together determine its electrical behavior.<\/p>\n<p>Draw the cross-section before routing. Identify both reference planes and both signal layers. If a plane sits between the two traces, it is not the intended directly coupled geometry. A pair routed in adjacent layers but far apart laterally also does not behave like an intentionally overlaid pair.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"edge_coupled_vs_broadside_coupled\"><\/span>edge coupled vs broadside coupled<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Edge coupling uses the narrow facing edges of two side-by-side tracks on the same layer; broadside coupling uses two tracks on different layers. Compare at the same target impedance, route length and channel requirements rather than comparing two unrelated calculator outputs.<\/p>\n<figure class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Decision factor<\/strong><\/td>\n<td><strong>Edge coupled<\/strong><\/td>\n<td><strong>Broadside coupled<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Routing width<\/td>\n<td>Two traces and one gap<\/td>\n<td>Can share a lateral corridor<\/td>\n<\/tr>\n<tr>\n<td>Coupling input<\/td>\n<td>Etched same-layer gap<\/td>\n<td>Interlayer spacing and overlap<\/td>\n<\/tr>\n<tr>\n<td>Entry and exit<\/td>\n<td>Both tracks share one layer<\/td>\n<td>Two depths can need different via launches<\/td>\n<\/tr>\n<tr>\n<td>Use when<\/td>\n<td>Channel fits and etch window passes<\/td>\n<td>Routing benefit remains after tolerance and launch checks<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<p>For the example link, check whether changing the escape pattern would let both traces stay on one layer. A small connector breakout redesign can be preferable to two dissimilar transitions. Keep the stacked route if the saved width matters and the expected process spread is acceptable.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"broadside_coupled_stripline_calculator\"><\/span>broadside coupled stripline calculator<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Use a model that explicitly supports broadside geometry, including lateral offset if that is part of the build tolerance. A generic stripline or edge-pair calculator is not an equivalent model. Ask the fabricator for the proposed pressed stackup and expected finished dimensions, not just the nominal prepreg designation.<\/p>\n<figure class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Input<\/strong><\/td>\n<td><strong>Unit or form<\/strong><\/td>\n<td><strong>What to vary<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Finished track widths and copper<\/td>\n<td>\u00b5m<\/td>\n<td>Both layers separately<\/td>\n<\/tr>\n<tr>\n<td>Trace-to-trace and plane spacing<\/td>\n<td>\u00b5m<\/td>\n<td>Pressed dielectric dimensions<\/td>\n<\/tr>\n<tr>\n<td>Relative layer offset<\/td>\n<td>\u00b5m transverse to route<\/td>\n<td>Nominal and both shift directions<\/td>\n<\/tr>\n<tr>\n<td>Dielectric properties<\/td>\n<td>Relative permittivity and frequency<\/td>\n<td>Approved construction and model<\/td>\n<\/tr>\n<tr>\n<td>Differential impedance<\/td>\n<td>\u03a9<\/td>\n<td>Nominal and agreed process corners<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<p>Start with the aligned geometry, sweep offset alone to understand sensitivity, and then combine relevant limits with width and dielectric changes. For a link that turns through 90 degrees, a registration shift can project differently onto the two route segments. Check both orientations if the process tolerance or routing makes that distinction relevant.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Differential_stripline_impedance_formula\"><\/span>Differential stripline impedance formula<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>For a symmetric pair with equal and opposite excitation, differential impedance equals twice the per-conductor odd-mode impedance. In this hypothetical 100 \u03a9 link, 50 \u03a9 odd-mode corresponds to 100 \u03a9 differential. That does not mean two isolated 50 \u03a9 traces will remain a 100 \u03a9 pair when brought together.<\/p>\n<p>The relation explains a solver output; it does not calculate impedance from width and spacing by itself. For unequal conductors or asymmetric placement, use a model that represents the actual cross-section, and check both differential behavior and conversion between differential and common modes. Do not reuse a symmetric calculation after making one leg materially different.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"pcb_layer_registration\"><\/span>pcb layer registration<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Registration is the alignment of one fabricated layer to another. A lateral shift can reduce copper overlap and change coupling even when both traces meet their individual width requirements. For two equal 120 \u00b5m tracks, a 30 \u00b5m transverse shift leaves 90 \u00b5m of geometrical overlap, or 75%, in a simple rectangular projection. This is a teaching example; 75% overlap does not mean a 25% impedance change.<\/p>\n<p>Ask what the quoted registration figure refers to: two layers relative to each other, a layer relative to a datum, or another inspection definition. If each layer is only specified to a common datum, get an agreed relative tolerance or justify how the limits combine. Put the layer pair and the direction of the offset in the stackup review, then use that value in the model.<\/p>\n<figure class=\"wp-block-image\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/pcb-layer-registration.jpg\" alt=\"Polished multilayer PCB microsection on a microscope stage\" width=\"1200\" height=\"600\" style=\"max-width:100%;height:auto;\"><figcaption>Illustration: A section can check local dimensions and overlap at its cut location. It is not an electrical test of the complete route.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"differential_pair_skew\"><\/span>differential pair skew<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Skew is the difference in arrival time between the pair\u2019s two conductors. Matching length in the layout editor does not by itself prove matching delay: the two vias can have different lengths, and the two tracks can have different electromagnetic environments. Look at the complete path from transmitter to receiver.<\/p>\n<p>In the connector example, both legs leave a component on the same outer layer and reach different inner layers. Model the two launches, including relevant reference transitions and via stubs, before adding a meander to correct a length number. A geometry change can improve time matching while making a discontinuity worse; check both effects.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"differential_impedance_measurement\"><\/span>differential impedance measurement<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>A matching differential time-domain reflectometry (TDR) coupon checks impedance along a representative fabricated cross-section. It should use the same signal-layer pair, reference planes, widths and spacing, and a suitable measurement launch. Agree on the trace region to evaluate so the launch and coupon termination are not averaged into the uniform segment.<\/p>\n<p>If the uniform region fails, first confirm the setup and coupon geometry, then compare measured dimensions and registration with the model. If the uniform coupon passes but the link fails, inspect the actual vias, connector and return path. Use channel measurements or an applicable eye test when system performance is the concern. A passing coupon does not certify the complete assembled channel.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"pcb_layer_to_layer_registration_tolerance\"><\/span>pcb layer to layer registration tolerance<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Release the stacked pair only when the supplier\u2019s usable registration and pressed stackup limits, the modeled process window, and the inspection plan agree. Put the target, tolerance, coupon structure and review criteria in the release package. Define which changes require a new model or approval, including substitutions that change the dielectric spacing.<\/p>\n<p>For the example, assume the project has separately defined its 100 \u03a9 tolerance and channel limits. If the agreed worst-case geometry fails or cannot be documented, choose the side-by-side routing or renegotiate the stackup before release. After a revision, rerun the same corner set, measure a representative coupon, and verify the assembled link against the project\u2019s own limits.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"FAQ\"><\/span>FAQ<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<h3>Can I stack the traces under a split in a reference plane?<\/h3>\n<p>Do not treat a plane split as equivalent to a continuous reference in the model. Review the return path and discontinuity, and reroute or model the transition if the split cannot be avoided.<\/p>\n<h3>Is nominal 100 \u03a9 enough to sign off the routing?<\/h3>\n<p>No. The nominal result leaves out process variation and the channel launches. Compare the expected range against the specified window and plan measurements for the finished construction.<\/p>\n<h3>Can a surface microstrip coupon verify the inner broadside pair?<\/h3>\n<p>No. It does not reproduce the two inner signal layers and their dielectric and plane geometry. It can help validate its own geometry, not substitute for a matched broadside coupon.<\/p>\n<h3>Does a section through one location verify alignment across a panel?<\/h3>\n<p>No. A section provides local evidence. Agree on sample locations and additional registration evidence when panel variation could affect the result.<\/p>\n<h3>Can the two tracks use different widths?<\/h3>\n<p>They can be modeled that way if necessary, but an equal-width symmetric model no longer applies. Check the finished cross-sections, impedance, delay and mode conversion before approving the change.<\/p>\n<h3>Do I need to tune both tracks if the measured issue is at the connector?<\/h3>\n<p>Not necessarily. Locate the discontinuity first. Changing the uniform trace geometry can move the coupon result without resolving a launch problem.<\/p>\n<h3>Can I use the same layer-offset value as an etch-width tolerance?<\/h3>\n<p>No. Offset moves layers relative to each other; etch tolerance changes a feature within a layer. Use separate variables and supplier data in the model.<\/p>\n<h3>Is a broadside pair always better for crosstalk?<\/h3>\n<p>No. Pair coupling is not the same as isolation from neighboring routes. Check nearby conductors, plane geometry, the coupled length and the channel\u2019s noise limits.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"References\"><\/span>References<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<ul>\n<li><a href=\"https:\/\/www.polarinstruments.com\/help\/si9000\/broadside.coupledstripline.htm\">Polar Instruments broadside-coupled stripline model<\/a><\/li>\n<li><a href=\"https:\/\/www.polarinstruments.com\/support\/cits\/AP143.html\">Polar Instruments AP143: unbalanced tracks and differential impedance<\/a><\/li>\n<li><a href=\"https:\/\/www.bestpcbs.com\/blog\/tag\/differential-pair-stripline-vs-microstrip\/\">Best Technology differential pair routing articles<\/a><\/li>\n<\/ul>\n<p>For a Best Technology manufacturing inquiry, send the proposed stackup, layer pair, finished routing geometry, impedance target and coupon requirements to <a href=\"mailto:sales@bestpcbs.com\">sales@bestpcbs.com<\/a>. Note any material or layout dimensions that cannot change.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Compare broadside and edge-coupled stripline. Learn which stackup inputs to sweep and what a matching differential impedance coupon can verify.<\/p>\n","protected":false},"author":32827,"featured_media":38787,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_uf_show_specific_survey":0,"_uf_disable_surveys":false,"footnotes":""},"categories":[174],"tags":[9302,9197,9143,9303],"class_list":["post-38789","post","type-post","status-publish","format-standard","hentry","category-bestpcb","tag-broadside-coupled-stripline","tag-differential-impedance","tag-impedance-coupon","tag-layer-registration"],"acf":[],"aioseo_notices":[],"aioseo_head":"\n\t\t<!-- All in One SEO 5.0.4 - aioseo.com -->\n\t<meta name=\"description\" content=\"Compare broadside and edge-coupled stripline. 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