{"id":38764,"date":"2026-11-10T19:09:34","date_gmt":"2026-11-10T11:09:34","guid":{"rendered":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/pcie-ac-coupling-capacitor-placement\/"},"modified":"2026-11-10T19:09:34","modified_gmt":"2026-11-10T11:09:34","slug":"pcie-ac-coupling-capacitor-placement","status":"publish","type":"post","link":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/pcie-ac-coupling-capacitor-placement\/","title":{"rendered":"PCIe AC Coupling Capacitor Placement: Check Both Paths"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_89 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/pcie-ac-coupling-capacitor-placement\/#PCIe_AC_Coupling_Capacitor_Placement\" >PCIe AC Coupling Capacitor Placement<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/pcie-ac-coupling-capacitor-placement\/#AC_Coupling_Capacitor_for_PCIe\" >AC Coupling Capacitor for PCIe<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/pcie-ac-coupling-capacitor-placement\/#PCIe_AC_Coupling_Capacitor_Value\" >PCIe AC Coupling Capacitor Value<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/pcie-ac-coupling-capacitor-placement\/#AC_Coupling_Capacitor_Size\" >AC Coupling Capacitor Size<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/pcie-ac-coupling-capacitor-placement\/#Differential_Pair_Routing_Guidelines\" >Differential Pair Routing Guidelines<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/pcie-ac-coupling-capacitor-placement\/#Differential_Pair_Impedance\" >Differential Pair Impedance<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/pcie-ac-coupling-capacitor-placement\/#PCB_Return_Path\" >PCB Return Path<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/pcie-ac-coupling-capacitor-placement\/#PCIe_Gen_5_Layout_Guidelines\" >PCIe Gen 5 Layout Guidelines<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/pcie-ac-coupling-capacitor-placement\/#Frequently_Asked_Questions\" >Frequently Asked Questions<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/pcie-ac-coupling-capacitor-placement\/#References\" >References<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-11\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/pcie-ac-coupling-capacitor-placement\/#Discuss_Your_PCB_Requirements\" >Discuss Your PCB Requirements<\/a><\/li><\/ul><\/nav><\/div>\n<div class=\"yzp-no-index\"><\/div><p>Place PCIe AC coupling capacitors only after checking which part of the link is responsible for each transmit path. Then place the two parts as a matched pair and verify their pad transitions in the actual stackup. A capacitor can be correct in the schematic and still introduce an avoidable discontinuity on the board.<\/p>\n<figure class=\"wp-block-image\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/ac-coupling-capacitor-placement.jpg\" alt=\"Pair of ceramic capacitors placed on two differential PCB traces\" width=\"1120\" height=\"630\" style=\"max-width:100%;height:auto;\"><figcaption>Check each series part and its placement in the complete lane. Illustrative rendering; not a production or test record.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"PCIe_AC_Coupling_Capacitor_Placement\"><\/span>PCIe AC Coupling Capacitor Placement<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Start with the platform\u2019s channel drawing, not a rule such as \u201calways next to the transmitter.\u201d The transmit path tells you which lane needs coupling; physical position depends on the device and topology. Confirm which board or module provides the series parts and whether the device already integrates coupling.<\/p>\n<p>Consider a hypothetical endpoint on an adapter connected to a host through a slot. Mark host transmit and endpoint transmit as separate paths. A placement decision that is correct for one direction does not automatically assign the parts in the reverse direction.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"AC_Coupling_Capacitor_for_PCIe\"><\/span>AC Coupling Capacitor for PCIe<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>A series coupling capacitor blocks DC while allowing the changing signal to reach the receiving path. It is not the same part as a supply bypass capacitor or a capacitor that links reference planes. On a differential lane, the approved coupling arrangement must be implemented on both conductors.<\/p>\n<figure class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Review item<\/strong><\/td>\n<td><strong>What to verify<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Transmit ownership<\/td>\n<td>Host and endpoint paths traced separately<\/td>\n<\/tr>\n<tr>\n<td>Existing series parts<\/td>\n<td>On-device, adapter, or host implementation<\/td>\n<\/tr>\n<tr>\n<td>Placement<\/td>\n<td>Topology-specific vendor guidance<\/td>\n<\/tr>\n<tr>\n<td>Part geometry<\/td>\n<td>Same approved launch on both conductors<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<p>Check the schematic against the actual channel and bill of materials. Do not add a second pair simply because a connector sits between boards.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"PCIe_AC_Coupling_Capacitor_Value\"><\/span>PCIe AC Coupling Capacitor Value<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Choose capacitance from the applicable platform or device documentation. TI\u2019s PCIe Gen 5 layout note discusses a 75\u2013220 nF range and describes 220 nF as typical in its context. Those values do not override requirements for a specific component, topology or implementation.<\/p>\n<p>Check approved value, tolerance, package, voltage and the relevant high-frequency model together. A nominal capacitance match does not prove two components behave the same through their mounting geometry and parasitics.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"AC_Coupling_Capacitor_Size\"><\/span>AC Coupling Capacitor Size<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Compare the solder land with the controlled trace before selecting a package. In TI\u2019s illustrative Gen 5 layout, a 12 mil pad is wider than a 5\u20137 mil trace. At an illustrative 6 mil trace width, the pad is twice as wide. That ratio is a geometry warning, not a formula for the resulting impedance.<\/p>\n<figure class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Placement option<\/strong><\/td>\n<td><strong>Potential benefit<\/strong><\/td>\n<td><strong>What to confirm<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Smaller approved package<\/td>\n<td>Smaller pad transition<\/td>\n<td>Assembly and component limits<\/td>\n<\/tr>\n<tr>\n<td>Existing larger footprint<\/td>\n<td>Established assembly process<\/td>\n<td>Modeled discontinuity is acceptable<\/td>\n<\/tr>\n<tr>\n<td>Staggered pair<\/td>\n<td>Fits a crowded area<\/td>\n<td>Both paths still have comparable electrical response<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Differential_Pair_Routing_Guidelines\"><\/span>Differential Pair Routing Guidelines<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Make the two capacitor launches geometrically comparable. Use matching footprints, equivalent approach and exit routes, and comparable vias and reference environments. Avoid adding a jog or changing layers on one conductor just to align both components visually.<\/p>\n<p>If routing forces a stagger, compare the actual two-path electrical response rather than assuming a neat centerline layout compensates for it. Keep nearby copper, neckdowns and return geometry in the model.<\/p>\n<figure class=\"wp-block-image\"><img decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/differential-pair-routing.jpg\" alt=\"Parallel copper routes with corresponding SMD footprints on a test coupon\" width=\"1120\" height=\"630\" style=\"max-width:100%;height:auto;\" loading=\"lazy\"><figcaption>Compare the two pad transitions and their reference geometry. Illustrative rendering; not a production or test record.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Differential_Pair_Impedance\"><\/span>Differential Pair Impedance<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>A wider mounting pad can create a local impedance dip. The depth of that dip depends on the dielectric, pad, neighboring conductor and reference plane. A small package or an engineered transition can reduce the discontinuity, but neither automatically proves the channel is within budget.<\/p>\n<p>Model the footprint and launch together, and compare the result with the channel\u2019s permitted impedance and loss behavior. Use the final land pattern, not only the package body dimensions or the nominal routed trace impedance.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"PCB_Return_Path\"><\/span>PCB Return Path<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Preserve the intended return path. Some platform notes use a localized reference-plane void under the capacitor launch to reduce excess capacitance. Treat that as a stackup-specific design choice. Do not cut a long slot beneath the pair or transfer the same void to a board with different layers without checking the effect.<\/p>\n<p>Compare an intact reference and the proposed local relief in the actual stackup if the device guidance permits. Include both conductors and surrounding geometry. If local impedance improves but conversion or return-path behavior worsens, revise the transition instead of approving it on a single result.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"PCIe_Gen_5_Layout_Guidelines\"><\/span>PCIe Gen 5 Layout Guidelines<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Release the design when ownership, capacitance, placement and both electrical paths have been checked against the approved platform. For the hypothetical adapter, verify both transmit directions, then compare the matched footprint against the actual connector and stackup. Save the channel model and the intended verification method with the board revision.<\/p>\n<p>Use the <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcie-routing-guidelines\/\">Best Technology PCIe routing guide<\/a> for the wider channel constraints. A link that trains on one bench sample is useful evidence, but it is not a substitute for the margin or compliance tests required for the product.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Frequently_Asked_Questions\"><\/span>Frequently Asked Questions<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<h3>Do PCIe coupling capacitors belong next to the transmitter?<\/h3>\n<p>The transmitter identifies the path that needs the approved coupling arrangement. It does not create a universal physical placement rule. Check the platform topology and device layout guidance. A chip-to-chip path and a chip-to-connector path can have different recommended locations for the same function.<\/p>\n<h3>What if both boards already contain series capacitors?<\/h3>\n<p>Trace the channel and confirm whether the parts are intended to operate together. Two series capacitors change the effective coupling behavior, so do not leave both simply because each board uses a familiar reference design. Resolve ownership against the approved host, adapter and endpoint requirements.<\/p>\n<h3>Can I place one capacitor farther along the pair?<\/h3>\n<p>Only if the resulting channel still passes the applicable electrical checks. The location difference can change how the discontinuities interact. Compare the complete launch, return environment and differential response rather than treating matched copper length or identical component values as sufficient evidence.<\/p>\n<h3>Is 0201 always the best package?<\/h3>\n<p>No. A smaller package can reduce the pad transition, but it must be available in the approved electrical value and suitable for the assembly process. Use the actual mounting land and model. A different package is acceptable only if the electrical and manufacturing requirements are met.<\/p>\n<h3>Does a plane void always improve the channel?<\/h3>\n<p>No. A controlled local void can help a particular capacitive pad transition, but a larger or poorly placed opening can disturb the return path. Follow the device guidance and compare the geometry in the actual stackup. Do not apply a blanket cutout underneath the entire lane.<\/p>\n<h3>Can an AC coupling capacitor repair a bad reference-plane transition?<\/h3>\n<p>No. The series component has a different function from managing a signal\u2019s return path. The pad and nearby vias must still have a suitable reference environment. Check the reference-plane transition and coupling launch independently, then evaluate their combined effect in the complete channel.<\/p>\n<h3>What should I check after a PCIe link trains successfully?<\/h3>\n<p>Confirm the expected lane width and operating speed, then follow the platform\u2019s margin and validation plan across required conditions. Keep the channel model, device settings and assembly revision with the results. One successful training event does not prove every lane and product condition has adequate margin.<\/p>\n<h3>What files help with a capacitor placement review?<\/h3>\n<p>Send the transmit ownership diagram, schematic, package and land pattern, final stackup, and both conductors around the capacitor. Include connector and via details plus any proposed plane relief. That makes it possible to compare the two launches instead of judging the placement from a cropped image.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"References\"><\/span>References<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<ul>\n<li><a href=\"https:\/\/www.ti.com\/lit\/an\/snla426\/snla426.pdf\">Texas Instruments: High-Speed PCB Layout for PCIe Gen 5<\/a><\/li>\n<li><a href=\"https:\/\/www.nxp.com\/docs\/en\/application-note\/AN11082.pdf\">NXP AN11082: PCB Design and Layout Guidelines<\/a><\/li>\n<\/ul>\n<h2><span class=\"ez-toc-section\" id=\"Discuss_Your_PCB_Requirements\"><\/span>Discuss Your PCB Requirements<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>For a Best Technology fabrication review, send the PCIe stackup, capacitor footprint and paired route geometry to <a href=\"mailto:sales@bestpcbs.com\">sales@bestpcbs.com<\/a>. Mark the connector transitions and any localized reference-plane voids.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Check PCIe AC coupling capacitor placement, lane ownership, pad symmetry, and return paths before releasing a high-speed PCB channel.<\/p>\n","protected":false},"author":32827,"featured_media":38762,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_uf_show_specific_survey":0,"_uf_disable_surveys":false,"footnotes":""},"categories":[174],"tags":[9287,9285,9288,9286],"class_list":["post-38764","post","type-post","status-publish","format-standard","hentry","category-bestpcb","tag-differential-pad-symmetry","tag-pcie-ac-coupling-placement","tag-pcie-channel-verification","tag-series-capacitor-launch"],"acf":[],"aioseo_notices":[],"aioseo_head":"\n\t\t<!-- All in One SEO 5.0.4 - aioseo.com -->\n\t<meta name=\"description\" content=\"Check PCIe AC coupling capacitor placement, lane ownership, pad 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