{"id":38758,"date":"2026-11-10T18:48:57","date_gmt":"2026-11-10T10:48:57","guid":{"rendered":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-spacing-array-temperature\/"},"modified":"2026-11-10T18:48:57","modified_gmt":"2026-11-10T10:48:57","slug":"thermal-via-spacing-array-temperature","status":"publish","type":"post","link":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-spacing-array-temperature\/","title":{"rendered":"Thermal Via Spacing: When a Denser Array Helps"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_89 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-spacing-array-temperature\/#Thermal_Via_Spacing\" >Thermal Via Spacing<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-spacing-array-temperature\/#Thermal_Via_Array\" >Thermal Via Array<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-spacing-array-temperature\/#Thermal_Via_Diameter\" >Thermal Via Diameter<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-spacing-array-temperature\/#Thermal_Resistance_of_PCB_Vias\" >Thermal Resistance of PCB Vias<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-spacing-array-temperature\/#Thermal_Resistance_Formula_Conduction\" >Thermal Resistance Formula Conduction<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-spacing-array-temperature\/#Thermal_Via_Solder_Wicking\" >Thermal Via Solder Wicking<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-spacing-array-temperature\/#PCB_Thermal_Resistance\" >PCB Thermal Resistance<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-spacing-array-temperature\/#Thermal_Via_Design_Guidelines\" >Thermal Via Design Guidelines<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-spacing-array-temperature\/#Frequently_Asked_Questions\" >Frequently Asked Questions<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-spacing-array-temperature\/#References\" >References<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-11\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-spacing-array-temperature\/#Discuss_Your_PCB_Requirements\" >Discuss Your PCB Requirements<\/a><\/li><\/ul><\/nav><\/div>\n<div class=\"yzp-no-index\"><\/div><p>Closer thermal via spacing helps only if the via barrels are a meaningful part of the heat path. Before packing more vias under a QFN pad, compare the two arrays on the same copper and stackup, check that the solder joint still forms correctly, and repeat the temperature test at the same power and airflow.<\/p>\n<figure class=\"wp-block-image\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/thermal-via-array.jpg\" alt=\"Regular via array in a bare QFN exposed-pad land\" width=\"1120\" height=\"630\" style=\"max-width:100%;height:auto;\"><figcaption>Compare actual via lands and paste windows, not just the centers. Illustrative rendering; not a production or test record.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Thermal_Via_Spacing\"><\/span>Thermal Via Spacing<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Thermal via spacing is the center-to-center distance between vias that transfer heat through the board. It does not determine temperature on its own. The pad size, via diameter and plating, copper planes, and the path from the board to air or a heatsink all matter.<\/p>\n<p>Consider a hypothetical power QFN with a 3 \u00d7 3 via array. The board runs hotter than expected at a steady load. The designer wants to change only the via count. Compare that option with improving copper spreading or the board-to-heatsink interface before assuming pitch is the limiting variable.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Thermal_Via_Array\"><\/span>Thermal Via Array<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Compare arrays that fit in the same usable pad region. In this example, a 3 \u00d7 3 array at 1.00 mm pitch and a 4 \u00d7 4 array at about 0.667 mm pitch each span 2.00 mm between outer via centers. Neither value includes the via land radii, required edge margin or paste pattern.<\/p>\n<figure class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Parameter<\/strong><\/td>\n<td><strong>Array A<\/strong><\/td>\n<td><strong>Array B<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Via count<\/td>\n<td>9<\/td>\n<td>16<\/td>\n<\/tr>\n<tr>\n<td>Center pitch<\/td>\n<td>1.00 mm<\/td>\n<td>About 0.667 mm<\/td>\n<\/tr>\n<tr>\n<td>Outer-center span<\/td>\n<td>2.00 mm<\/td>\n<td>2.00 mm<\/td>\n<\/tr>\n<tr>\n<td>Via barrel and stack<\/td>\n<td>Same assumed geometry<\/td>\n<td>Same assumed geometry<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<p>Overlay the copper, drill and stencil data. An array that fits by center points alone may not leave enough room for the actual lands, mask or paste windows.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Thermal_Via_Diameter\"><\/span>Thermal Via Diameter<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Distinguish the finished hole diameter from the drilled hole and pad diameter. For a simplified barrel with 0.25 mm inner diameter and 0.025 mm wall thickness, the outer barrel diameter is 0.30 mm. The land can be wider. A larger land does not add the same axial copper area as a thicker barrel.<\/p>\n<p>Ask for the approved drill, plating and via construction. Via fill and surface finish also affect the assembly decision. Use the package supplier\u2019s land and stencil guidance for the actual component instead of borrowing a via diameter from a different exposed pad.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Thermal_Resistance_of_PCB_Vias\"><\/span>Thermal Resistance of PCB Vias<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>The barrel conducts heat along its copper wall. The cross-sectional area is \u03c0 \u00f7 4 \u00d7 (outer diameter\u00b2 \u2212 inner diameter\u00b2). In the illustrative geometry it is about 0.0216 mm\u00b2. Do not count the air in an open hole as solid copper.<\/p>\n<p>Assume uniform copper, equal temperature at all top via ends and equal temperature at all bottom ends. This idealization lets the barrel conductances add in parallel. It does not account for how heat spreads across the pad or through the receiving plane.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Thermal_Resistance_Formula_Conduction\"><\/span>Thermal Resistance Formula Conduction<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>For one uniform conduction path, thermal resistance is length divided by conductivity times cross-sectional area: R = L \u00f7 (k \u00d7 A). At 1.60 mm length, an illustrative copper conductivity of 390 W\/(m\u00b7K), and 0.0216 mm\u00b2 of wall area, one barrel is about 190 K\/W. Convert mm and mm\u00b2 to meters and square meters first.<\/p>\n<p>Under the equal-end-temperature assumption, nine barrels give about 21.1 K\/W and sixteen give about 11.9 K\/W. This is a barrel-only estimate, not a junction-to-ambient rating. If both arrays connect into a poorly spreading region, the assembled temperature difference may be much smaller.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Thermal_Via_Solder_Wicking\"><\/span>Thermal Via Solder Wicking<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Check the solderable pad before approving a denser pattern. Open holes can draw solder away from the joint. More vias can change available paste area and the joint\u2019s void pattern. Review the package recommendation, assembly process and available via treatments together.<\/p>\n<p>See the <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-solder-wicking-guide\/\">Best Technology guide to solder wicking through thermal vias<\/a> for the joint-side checks. Use the agreed inspection method and joint acceptance criteria; a lower board temperature does not excuse a failed solder joint.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"PCB_Thermal_Resistance\"><\/span>PCB Thermal Resistance<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Interpret the temperature result as a system measurement. Hold the copper layout outside the test pad, component, board stackup, heatsink contact, airflow, ambient and actual dissipated power as constant as practical. Measure at the same defined point and after a comparable steady-state condition.<\/p>\n<figure class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Observation<\/strong><\/td>\n<td><strong>Decision<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Denser array lowers temperature repeatably<\/td>\n<td>Verify joint quality and final conditions<\/td>\n<\/tr>\n<tr>\n<td>Both arrays run similarly<\/td>\n<td>Investigate spreading, interface and airflow<\/td>\n<\/tr>\n<tr>\n<td>Denser array harms the joint<\/td>\n<td>Change via treatment or paste plan before release<\/td>\n<\/tr>\n<tr>\n<td>Power or airflow changed<\/td>\n<td>Repeat the controlled comparison<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<p>If the product limit is junction temperature, use an appropriate package method for estimating or measuring it. A board thermocouple at an arbitrary spot is not a direct junction measurement.<\/p>\n<figure class=\"wp-block-image\"><img decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/pcb-thermal-resistance.jpg\" alt=\"PCB mounted on a heat spreader with a temperature sensor\" width=\"1120\" height=\"630\" style=\"max-width:100%;height:auto;\" loading=\"lazy\"><figcaption>Fix the sensor position and thermal setup for the comparison. Illustrative rendering; not a production or test record.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Thermal_Via_Design_Guidelines\"><\/span>Thermal Via Design Guidelines<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Approve the densest pattern only if it earns its manufacturing cost and passes the real requirements. Check DFM, repeat temperature measurements at the agreed operating conditions, and verify the assembly evidence. If the gain is within measurement scatter, investigate a different bottleneck rather than declaring the denser pitch a fix.<\/p>\n<p>Record via count, construction, dimensions and the validated setup. If the copper stack, heatsink interface or stencil changes later, revisit the result rather than assuming the same spacing still works.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Frequently_Asked_Questions\"><\/span>Frequently Asked Questions<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<h3>Is there one recommended spacing for thermal vias?<\/h3>\n<p>No universal pitch fits every package or process. Use the exact component\u2019s land-pattern guidance, the fabricator\u2019s approved drill and copper rules, and the assembler\u2019s paste requirements. Check the outer via margins and then compare temperature on representative hardware before approving a denser array.<\/p>\n<h3>Why is the calculated resistance of one via so high?<\/h3>\n<p>A plated barrel has a thin conducting wall. Even though copper conducts heat well, the wall area is small relative to the length of a through-board path. Several barrels can reduce that segment\u2019s resistance in parallel, but they do not remove the other limits in the system.<\/p>\n<h3>Can I use the pad diameter to calculate barrel area?<\/h3>\n<p>No. The pad diameter describes the copper land at a layer, not the cross section of the barrel conducting through the board. Use the wall geometry and the appropriate conductive length for that model. Model any approved conductive fill separately rather than counting the whole pad as axial copper.<\/p>\n<h3>Can a solid fill always be treated as copper?<\/h3>\n<p>No. Fill materials can have different conductivities, and some fill is used for planarization rather than as a high-conductivity path. Ask for the qualified material and construction. Use its relevant properties in the model, and keep the solderable surface requirement separate from the thermal calculation.<\/p>\n<h3>Should every thermal via connect to a ground plane?<\/h3>\n<p>Only if the package electrical requirements and board design allow that connection. The exposed pad may have a specified potential. Verify the datasheet and intended planes before adding vias. A good heat path is not acceptable if it shorts nodes or violates the component\u2019s electrical layout rules.<\/p>\n<h3>What if a denser array changes the temperature only slightly?<\/h3>\n<p>Repeat at the same power and ambient with the same sensor placement. If the change is within normal measurement scatter, do not credit the array. Check the receiving copper, thermal interface and airflow before spending more on via count, fill or additional fabrication operations.<\/p>\n<h3>Can I compare an infrared reading with a thermocouple reading?<\/h3>\n<p>Only after accounting for what and where each instrument measures. Infrared readings depend on emissivity and spot size; a contact sensor depends on placement and attachment. Define a repeatable point and method for the comparison. Do not combine unrelated readings as if they measured the same temperature.<\/p>\n<h3>What should be included in a thermal via fabrication review?<\/h3>\n<p>Send the package land pattern, stackup, drill and finished-hole data, plating requirements, pad and stencil layout, and the planned temperature test. Identify the operating power and limit you must meet. That gives the reviewer enough context to compare array geometry with fabrication and assembly constraints.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"References\"><\/span>References<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<ul>\n<li><a href=\"https:\/\/www.ti.com\/lit\/an\/slma002h\/slma002h.pdf\">TI: PowerPAD Thermally Enhanced Package<\/a><\/li>\n<li><a href=\"https:\/\/www.ti.com\/lit\/an\/slma006\/slma006.pdf\">TI: Array QFN Application Note<\/a><\/li>\n<\/ul>\n<h2><span class=\"ez-toc-section\" id=\"Discuss_Your_PCB_Requirements\"><\/span>Discuss Your PCB Requirements<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>For a Best Technology fabrication review, send the component pad drawing, candidate arrays and layer stack to <a href=\"mailto:sales@bestpcbs.com\">sales@bestpcbs.com<\/a>. Include the proposed via treatment and the temperature test conditions so the drawing review addresses the actual build.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Compare two thermal via arrays under the same QFN pad. Estimate barrel resistance, then check whether added vias reduce temperature on the board.<\/p>\n","protected":false},"author":32827,"featured_media":38756,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_uf_show_specific_survey":0,"_uf_disable_surveys":false,"footnotes":""},"categories":[174],"tags":[9280,9278,9277,9279],"class_list":["post-38758","post","type-post","status-publish","format-standard","hentry","category-bestpcb","tag-pcb-temperature-testing","tag-qfn-via-array","tag-thermal-via-spacing","tag-via-barrel-resistance"],"acf":[],"aioseo_notices":[],"aioseo_head":"\n\t\t<!-- All in One SEO 5.0.4 - aioseo.com -->\n\t<meta name=\"description\" content=\"Compare two thermal via arrays under the same QFN pad. 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