{"id":38687,"date":"2026-11-09T17:04:41","date_gmt":"2026-11-09T09:04:41","guid":{"rendered":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-solder-wicking-guide\/"},"modified":"2026-11-09T17:04:41","modified_gmt":"2026-11-09T09:04:41","slug":"thermal-via-solder-wicking-guide","status":"publish","type":"post","link":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-solder-wicking-guide\/","title":{"rendered":"Thermal Via Solder Wicking: Protect the QFN Pad Joint"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_89 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-solder-wicking-guide\/#thermal_via_solder_wicking\" >thermal via solder wicking<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-solder-wicking-guide\/#thermal_pad_via_design\" >thermal pad via design<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-solder-wicking-guide\/#thermal_vias_size_and_spacing\" >thermal vias size and spacing<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-solder-wicking-guide\/#should_thermal_vias_be_tented\" >should thermal vias be tented<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-solder-wicking-guide\/#thermal_via_filling\" >thermal via filling<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-solder-wicking-guide\/#via_in_pad_plated_over\" >via in pad plated over<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-solder-wicking-guide\/#qfn_ground_pad_stencil_design\" >qfn ground pad stencil design<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-solder-wicking-guide\/#qfn_solder_void\" >qfn solder void<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-solder-wicking-guide\/#FAQ\" >FAQ<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/thermal-via-solder-wicking-guide\/#Discuss_Your_Project\" >Discuss Your Project<\/a><\/li><\/ul><\/nav><\/div>\n<div class=\"yzp-no-index\"><\/div><p>Thermal via solder wicking happens when molten solder enters a via opening connected to a package\u2019s exposed land. On a power QFN, that can reduce solder remaining under the package or leave solder on the opposite side. Prevent it by deciding together which vias remain open, where paste is printed and what the assembly inspection must confirm.<\/p>\n<p>Do not remove thermal vias just to make the solder process easier. Compare the via treatment and stencil pattern against the package guidance, electrical connection, thermal target and fabrication capability, then verify the assembled joint on representative hardware.<\/p>\n<figure><img fetchpriority=\"high\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/exposed-pad-thermal-via-array.jpg\" alt=\"Unpopulated PCB land with several plated via openings\" width=\"1120\" height=\"630\" style=\"max-width:100%;height:auto;\" loading=\"eager\"><figcaption>Via positions under a stencil aperture change how exposed openings interact with the paste. AI-generated illustration; not a production or test record.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"thermal_via_solder_wicking\"><\/span>thermal via solder wicking<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>An open, wettable via inside the pasted land creates a path for solder during reflow. The amount that enters depends on the opening, plating and wetting, available solder and process conditions. It is not enough to count vias or compute their empty volume. <a href=\"https:\/\/www.ti.com\/lit\/an\/slma002h\/slma002h.pdf\">TI\u2019s PowerPAD application report<\/a> discusses controlling hole size and stencil placement for the packages it covers.<\/p>\n<p>Check the actual joint for loss of solder and the reverse side for protrusion or deposits. Do not label every exposed-pad void as wicking; outgassing and paste or reflow behavior can also contribute.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"thermal_pad_via_design\"><\/span>thermal pad via design<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Design the thermal and assembly paths as one set of requirements. The exposed pad may have an electrical connection as well as a thermal role; check its required net in the device datasheet. Draw the via array, finished hole openings, paste windows and mask openings on the same coordinate basis so both suppliers can review them.<\/p>\n<figure class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Parameter<\/strong><\/td>\n<td><strong>Specify or verify<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Finished hole<\/td>\n<td>Diameter and location<\/td>\n<\/tr>\n<tr>\n<td>Via treatment<\/td>\n<td>Open, tented or capped<\/td>\n<\/tr>\n<tr>\n<td>Paste windows<\/td>\n<td>Size and alignment<\/td>\n<\/tr>\n<tr>\n<td>Thermal path<\/td>\n<td>Net, planes and copper<\/td>\n<\/tr>\n<tr>\n<td>Evidence<\/td>\n<td>X-ray and thermal check<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<h2><span class=\"ez-toc-section\" id=\"thermal_vias_size_and_spacing\"><\/span>thermal vias size and spacing<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Use the exact package recommendation and fabricator capability, not a universal hole diameter or pitch. Smaller openings may limit the solder available to flow into a barrel, but hole size, plating and pitch also affect the heat path and manufacturing yield. In a solder-risk review, ask where each opening lands relative to the stencil windows and what registration margin remains.<\/p>\n<p>The <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/thermal-vias\/\">thermal via design overview<\/a> covers the separate heat-flow and resistance question. This article focuses on deciding which openings can safely remain beneath the soldered land.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"should_thermal_vias_be_tented\"><\/span>should thermal vias be tented<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Tenting is an option only if the selected side and mask process are suitable for the package and assembly route. A mask film spanning an opening is not a metal cap. Top-side tenting can affect the wettable pad area; reverse-side tenting leaves a top-side opening unless the stack or process specifies otherwise.<\/p>\n<p>Ask whether the supplier can maintain the requested tent through fabrication and reflow at the finished hole size. Compare this with paste windows that avoid open vias, rather than treating tenting as a universal remedy.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"thermal_via_filling\"><\/span>thermal via filling<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Specify what \u201cfilled\u201d means before comparing quotes. A resin-filled via with a metal cap presents a different top surface from an open plated hole; a tented or merely plugged hole is not automatically planar or capped. A nonconductive fill does not remove the existing plated copper path, but it should not be modeled as a solid copper cylinder.<\/p>\n<figure class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Option<\/strong><\/td>\n<td><strong>Top surface<\/strong><\/td>\n<td><strong>Check before release<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Open plated via<\/td>\n<td>Opening exposed<\/td>\n<td>Paste clearance<\/td>\n<\/tr>\n<tr>\n<td>Mask tent<\/td>\n<td>Mask film, if intact<\/td>\n<td>Side and coverage<\/td>\n<\/tr>\n<tr>\n<td>Filled and capped<\/td>\n<td>Plated surface<\/td>\n<td>Flatness and cap integrity<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<figure><img decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/qfn-exposed-pad-package.jpg\" alt=\"QFN-style component underside and a power PCB sample\" width=\"1120\" height=\"630\" style=\"max-width:100%;height:auto;\" loading=\"lazy\"><figcaption>Use the exact package drawing when setting the land and stencil geometry. AI-generated illustration; not a production or test record.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"via_in_pad_plated_over\"><\/span>via in pad plated over<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Filled and plated-over via-in-pad can be useful when an uninterrupted solderable land is needed. Confirm the fill, cap plating, finished planarity and inspection evidence rather than approving a quote based only on \u201cVIPPO.\u201d See the <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/via-in-pad-plated-over\/\">via-in-pad plated-over process guide<\/a> for manufacturing details.<\/p>\n<p>Compare the extra process requirements with an open-hole approach that positions stencil windows away from the vias. Both options need assembly verification. Capping addresses the open-hole path but does not remove every possible cause of voiding.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"qfn_ground_pad_stencil_design\"><\/span>qfn ground pad stencil design<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Segmenting the paste area can help the assembler control deposit distribution and avoid some open holes. Use the package and assembly process recommendations; the stencil thickness and pattern must also suit the peripheral joints. <a href=\"https:\/\/www.ti.com\/lit\/an\/slua271c\/slua271c.pdf\">TI\u2019s QFN and SON attachment guidance<\/a> discusses exposed-pad stencil options and X-ray evaluation.<\/p>\n<p>For a drawing check only, four 1.2 mm square windows on a 3.0 mm square exposed land occupy 5.76 mm\u00b2 of the 9.00 mm\u00b2 land, or 64% area. With a 0.10 mm stencil, their theoretical aperture volume is 0.576 mm\u00b3. Neither value is a recommended target or a prediction of deposited solder; transfer efficiency and reflow change the result. Inspect the actual printed pattern before treating the layout as qualified.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"qfn_solder_void\"><\/span>qfn solder void<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Look at the void pattern, remaining joint coverage and any solder on the reverse side together. A two-dimensional X-ray can help locate voids, but it does not by itself prove how a void formed or how much solder entered a specific via. Compare the image with the via locations, stencil layout and process records.<\/p>\n<p>Before approving the design, agree the package-specific acceptance criteria with the assembly team. If the cause is still unclear, choose targeted cross-sections or another agreed inspection. Check the assembled board\u2019s temperature under representative power and ambient conditions; a neat-looking X-ray is not a thermal qualification.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"FAQ\"><\/span>FAQ<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<h3>Does every open thermal via wick solder?<\/h3>\n<p>No. The via and land must interact with molten solder under the actual process conditions. The risk depends on wetting, hole geometry, paste placement and reflow. Inspect both sides of representative assemblies and check the joint before treating a given arrangement as safe.<\/p>\n<h3>Is tenting on the bottom the same as a filled and capped via?<\/h3>\n<p>No. A mask tent can cover one opening but does not create a plated, planar top land. A filled and capped via uses a different fabrication sequence. Ask for the treatment and inspection details in the fabrication drawing instead of relying on an abbreviated label.<\/p>\n<h3>Can I simply reduce the amount of paste to stop wicking?<\/h3>\n<p>Reducing paste everywhere can leave an insufficient joint even if less solder travels down the hole. First review where paste overlaps the openings and what the package guidance calls for. Use measured paste deposits and assembled-joint evidence rather than adjusting total paste area alone.<\/p>\n<h3>Why are there solder deposits on the opposite side of the board?<\/h3>\n<p>An open via connected to the land can be a route for solder during reflow, but other solder processes can also leave deposits. Correlate their locations with the via map and record the assembly sequence. Inspect the top joint rather than assuming the reverse deposit is harmless.<\/p>\n<h3>Can a large void prove the exposed pad is not soldered?<\/h3>\n<p>A single X-ray view can show a projected void, not the full thickness or shape of a joint. Compare the image with the agreed criteria and inspect the location relative to the pad and vias. Use a suitable follow-up method if the diagnosis affects acceptance.<\/p>\n<h3>Will resin-filled vias provide the same thermal result as copper-filled vias?<\/h3>\n<p>Do not assume that they will. The barrel, fill, cap and connected planes contribute differently to heat flow. Use the actual cross-section and material properties in a thermal model, then confirm the assembled board when the temperature margin is small.<\/p>\n<h3>What must I tell the fabricator before selecting a via treatment?<\/h3>\n<p>Provide the package drawing, exposed land and via locations, finished hole sizes, affected sides and required surface condition. Also identify which features must be inspected and whether the assembler expects a flat solderable land. Get the treatment description accepted before releasing the files.<\/p>\n<h3>Should I compare a modified stencil using the same assembly process?<\/h3>\n<p>Yes, when practical. Keep the package, board, paste and reflow conditions comparable so changes are attributable to the stencil trial. Record print results, joint images and thermal checks together. If several inputs change at once, do not attribute the result to one adjustment alone.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Discuss_Your_Project\"><\/span>Discuss Your Project<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Send Best Technology the device drawing, pad and via layout, finished hole sizes and preferred treatment. Include the stencil and inspection requirements if they are already agreed. Contact <a href=\"mailto:sales@bestpcbs.com\">sales@bestpcbs.com<\/a>.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Reduce thermal via solder wicking under QFN exposed pads. Compare open, tented and capped vias, then align stencil design and X-ray inspection.<\/p>\n","protected":false},"author":32827,"featured_media":38685,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_uf_show_specific_survey":0,"_uf_disable_surveys":false,"footnotes":""},"categories":[174],"tags":[9022,7072,7354,548],"class_list":["post-38687","post","type-post","status-publish","format-standard","hentry","category-bestpcb","tag-qfn-assembly","tag-solder-wicking","tag-thermal-vias","tag-via-in-pad"],"acf":[],"aioseo_notices":[],"aioseo_head":"\n\t\t<!-- All in One SEO 5.0.4 - aioseo.com -->\n\t<meta name=\"description\" content=\"Reduce thermal via solder wicking under QFN exposed pads. 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