{"id":38527,"date":"2026-11-06T18:54:46","date_gmt":"2026-11-06T10:54:46","guid":{"rendered":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/offset-stripline-plane-spacing\/"},"modified":"2026-11-06T18:57:34","modified_gmt":"2026-11-06T10:57:34","slug":"offset-stripline-plane-spacing","status":"publish","type":"post","link":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/offset-stripline-plane-spacing\/","title":{"rendered":"Offset Stripline: Why Both Plane Spacings Matter"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_89 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/offset-stripline-plane-spacing\/#What_Makes_a_Stripline_Offset\" >What Makes a Stripline Offset<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/offset-stripline-plane-spacing\/#Why_the_Total_Gap_Does_Not_Describe_the_Geometry\" >Why the Total Gap Does Not Describe the Geometry<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/offset-stripline-plane-spacing\/#Detailed_Stackup_Inputs_to_Collect\" >Detailed Stackup Inputs to Collect<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/offset-stripline-plane-spacing\/#Symmetric_vs_Offset_Stripline\" >Symmetric vs Offset Stripline<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/offset-stripline-plane-spacing\/#Worked_Example_Same_Sum_Different_Input\" >Worked Example: Same Sum, Different Input<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/offset-stripline-plane-spacing\/#Know_What_the_Published_Formula_Assumes\" >Know What the Published Formula Assumes<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/offset-stripline-plane-spacing\/#Account_for_Copper_Thickness_in_the_Datum\" >Account for Copper Thickness in the Datum<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/offset-stripline-plane-spacing\/#Check_Which_Materials_Sit_Above_and_Below\" >Check Which Materials Sit Above and Below<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/offset-stripline-plane-spacing\/#Recalculate_When_the_Fabricator_Proposes_a_New_Stackup\" >Recalculate When the Fabricator Proposes a New Stackup<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/offset-stripline-plane-spacing\/#Use_a_Coupon_That_Represents_the_Offset_Layer\" >Use a Coupon That Represents the Offset Layer<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-11\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/offset-stripline-plane-spacing\/#Check_Transitions_Separately\" >Check Transitions Separately<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-12\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/offset-stripline-plane-spacing\/#Document_Both_Clearances_Before_Release\" >Document Both Clearances Before Release<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-13\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/offset-stripline-plane-spacing\/#Discuss_an_Impedance_Stackup\" >Discuss an Impedance Stackup<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-14\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/offset-stripline-plane-spacing\/#FAQ\" >FAQ<\/a><\/li><\/ul><\/nav><\/div>\n<div class=\"yzp-no-index\"><\/div><p>An offset stripline sits closer to one reference plane than the other. Do not put the average spacing into a symmetric formula and assume the result is correct. Model both distances and verify the actual stackup and coupon before freezing the trace width.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"What_Makes_a_Stripline_Offset\"><\/span>What Makes a Stripline Offset<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>A stripline is a conductor embedded between two reference planes. In a symmetric geometry the trace has equal dielectric spacing to those planes; in an offset geometry it does not. <a href=\"https:\/\/www.analog.com\/en\/resources\/analog-dialogue\/articles\/high-speed-printed-circuit-board-layout.html\">Analog Devices&#8217; layout guide<\/a> explains why the dielectric dimensions matter to stripline impedance.<\/p>\n<figure><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/embedded-stripline-edge.jpg\" width=\"1120\" height=\"630\" style=\"max-width:100%;height:auto\" alt=\"Multilayer PCB coupon showing copper and dielectric bands\"><figcaption>AI-generated cutaway concept; geometry is not to scale.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Why_the_Total_Gap_Does_Not_Describe_the_Geometry\"><\/span>Why the Total Gap Does Not Describe the Geometry<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Adding the upper and lower clearances hides where the trace sits. Moving the same trace toward one plane changes the field distribution and coupling. Preserve both individual dimensions in the impedance model rather than using their sum as the only spacing input.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Detailed_Stackup_Inputs_to_Collect\"><\/span>Detailed Stackup Inputs to Collect<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<figure class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Item<\/strong><\/td>\n<td><strong>Unit or record<\/strong><\/td>\n<td><strong>Purpose<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Upper dielectric<\/td>\n<td>Finished distance in mm<\/td>\n<td>Describes the upper field region<\/td>\n<\/tr>\n<tr>\n<td>Lower dielectric<\/td>\n<td>Finished distance in mm<\/td>\n<td>Describes the lower field region<\/td>\n<\/tr>\n<tr>\n<td>Trace width and thickness<\/td>\n<td>Finished geometry in mm<\/td>\n<td>Sets conductor cross-section<\/td>\n<\/tr>\n<tr>\n<td>Dielectric properties<\/td>\n<td>Model value and frequency<\/td>\n<td>Represents each dielectric region<\/td>\n<\/tr>\n<tr>\n<td>Reference layers<\/td>\n<td>Layer IDs and net<\/td>\n<td>Establishes the physical structure<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Symmetric_vs_Offset_Stripline\"><\/span>Symmetric vs Offset Stripline<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<figure class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Input<\/strong><\/td>\n<td><strong>Symmetric example<\/strong><\/td>\n<td><strong>Offset example<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Upper clearance<\/td>\n<td>0.15 mm<\/td>\n<td>0.10 mm<\/td>\n<\/tr>\n<tr>\n<td>Lower clearance<\/td>\n<td>0.15 mm<\/td>\n<td>0.20 mm<\/td>\n<\/tr>\n<tr>\n<td>Sum of clearances<\/td>\n<td>0.30 mm<\/td>\n<td>0.30 mm<\/td>\n<\/tr>\n<tr>\n<td>Model choice<\/td>\n<td>Symmetric geometry<\/td>\n<td>Preserve both distances<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Worked_Example_Same_Sum_Different_Input\"><\/span>Worked Example: Same Sum, Different Input<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>The two examples in the table have the same total dielectric clearance, but the trace in the second sits 0.05 mm closer to the upper plane. Keep the copper thickness and material assumptions explicit. The example compares model inputs only; it does not predict an impedance value.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Know_What_the_Published_Formula_Assumes\"><\/span>Know What the Published Formula Assumes<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><a href=\"https:\/\/www.analog.com\/media\/en\/training-seminars\/design-handbooks\/Basic-Linear-Design\/Chapter12.pdf\">Analog Devices&#8217; symmetric stripline handbook section<\/a> describes a trace between equally spaced reference planes. Its symmetric expression is not a substitute for a model of an off-centre trace. Use the formula only within the geometry and assumptions it describes.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Account_for_Copper_Thickness_in_the_Datum\"><\/span>Account for Copper Thickness in the Datum<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Confirm whether the two distances are measured from the trace faces, its centreline, or another reference. When using face-to-plane dielectric clearances, the complete plane separation also includes the conductor thickness. Do not add thickness twice when converting the drawing to solver inputs.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Check_Which_Materials_Sit_Above_and_Below\"><\/span>Check Which Materials Sit Above and Below<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Even equal clearances do not make every electrical property symmetric if the dielectric constructions differ. Record the material on each side, along with relevant properties and frequency assumptions. The solver should represent the chosen construction rather than assuming one material throughout.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Recalculate_When_the_Fabricator_Proposes_a_New_Stackup\"><\/span>Recalculate When the Fabricator Proposes a New Stackup<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>A proposed replacement can keep overall board thickness while changing one of the local distances. Ask for the approved finished dimensions, re-evaluate trace width or pair spacing if needed, and check whether the existing routing still fits the required clearances.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Use_a_Coupon_That_Represents_the_Offset_Layer\"><\/span>Use a Coupon That Represents the Offset Layer<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Match the routed layer, upper and lower references and relevant conductor geometry. A coupon on another layer may answer a different question. Agree on how the result will be measured and which dimensions are checked when a result falls outside its target.<\/p>\n<figure><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/stripline-coupon-bench.jpg\" width=\"1120\" height=\"630\" style=\"max-width:100%;height:auto\" alt=\"PCB test coupons with visible surface routing and coaxial fixtures\"><figcaption>AI-generated illustration of a test bench; the visible surface routing is not the buried stripline discussed here.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Check_Transitions_Separately\"><\/span>Check Transitions Separately<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>A uniform stripline model does not describe every connector or via transition. Review how reference current transfers where the route changes layers. The <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/08\/impedance-control-pcb-2\/\">BestPCBs impedance control guide<\/a> covers the wider stackup and test handoff.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Document_Both_Clearances_Before_Release\"><\/span>Document Both Clearances Before Release<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Record the layer pair, two dielectric distances, conductor dimensions, model assumptions and acceptance evidence. Keep the coupon associated with that revision. If the two distances are not known, leave the impedance estimate provisional rather than converting an assumed stackup into an approved requirement.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Discuss_an_Impedance_Stackup\"><\/span>Discuss an Impedance Stackup<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Send the layer map and controlled geometries to <a href=\"mailto:sales@bestpcbs.com\">Best Technology<\/a>.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"FAQ\"><\/span>FAQ<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<h3>Can I use the average of the two clearances?<\/h3>\n<p>Not as a final model for an offset stripline. Averaging discards the location of the trace between the planes. Use the actual upper and lower distances and an appropriate model, then compare the result with representative evidence if the design requires a controlled impedance.<\/p>\n<h3>Does equal plane spacing guarantee equal impedance?<\/h3>\n<p>No. Trace position, dimensions and dielectric properties matter even when the total distance between planes is the same. Keep the individual distances in the input record. Compare complete geometries rather than using a matching total as proof that two fabricated builds are electrically equivalent.<\/p>\n<h3>Can the two sides use different dielectric constructions?<\/h3>\n<p>A stackup may have different constructions on either side, but the model and fabrication review must account for them. Record both materials and their relevant properties. Do not use a single bulk dielectric input unless that approximation is justified for the electrical requirement and confirmed where necessary.<\/p>\n<h3>Is offset stripline necessarily worse than symmetric stripline?<\/h3>\n<p>No. It is a different geometry with different constraints and can be intentional. Compare impedance, available routing and reference continuity for the actual design. A symmetric structure may simplify the initial calculation, but suitability still depends on the requirements and on what can be built consistently.<\/p>\n<h3>Can I keep the same trace width after a stackup change?<\/h3>\n<p>Only after verifying that the new geometry meets the required impedance and layout constraints. A change in either dielectric distance can matter. Recheck the model and approved construction first, and decide whether the fabrication data or artwork needs updating before placing a production order.<\/p>\n<h3>Does an impedance coupon verify every transition?<\/h3>\n<p>No. A coupon for a uniform trace does not necessarily include the vias, launches or reference changes in the actual channel. Define which structures the coupon represents and decide whether the transitions need a separate model, test structure or assembled board measurement for the application.<\/p>\n<h3>Do I measure spacing from the trace centre or its face?<\/h3>\n<p>Use the convention required by the solver or drawing and convert dimensions consistently. A face-to-plane dielectric gap is not the same as a centreline-to-plane dimension. State the convention in the handoff and account for copper thickness exactly once when combining the measurements.<\/p>\n<h3>What should I ask the fabricator to confirm?<\/h3>\n<p>Ask for the finished upper and lower spacing, copper geometry, applicable material inputs and coupon layer. Include the target impedance and tolerance. Confirm the agreed measurement method and keep the answer linked to the actual artwork and stackup revision that will be released.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Compare symmetric and offset stripline, see why equal total plane spacing does not prove equal impedance, and verify the finished layer geometry.<\/p>\n","protected":false},"author":32827,"featured_media":38525,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_uf_show_specific_survey":0,"_uf_disable_surveys":false,"footnotes":""},"categories":[174],"tags":[9150,9149,9151,9152],"class_list":["post-38527","post","type-post","status-publish","format-standard","hentry","category-bestpcb","tag-asymmetric-stripline","tag-offset-stripline","tag-pcb-impedance","tag-reference-planes"],"acf":[],"aioseo_notices":[],"aioseo_head":"\n\t\t<!-- All in One SEO 5.0.4 - aioseo.com -->\n\t<meta name=\"description\" content=\"Compare symmetric and offset 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