{"id":38464,"date":"2026-11-06T16:45:20","date_gmt":"2026-11-06T08:45:20","guid":{"rendered":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/via-in-pad-flatness\/"},"modified":"2026-11-06T16:45:20","modified_gmt":"2026-11-06T08:45:20","slug":"via-in-pad-flatness","status":"publish","type":"post","link":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/via-in-pad-flatness\/","title":{"rendered":"Via-in-Pad Flatness: How to Inspect a Capped BGA Pad"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_89 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/via-in-pad-flatness\/#Identify_the_Surface_That_Will_Receive_Solder\" >Identify the Surface That Will Receive Solder<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/via-in-pad-flatness\/#Compare_Three_Inspections_That_Answer_Different_Questions\" >Compare Three Inspections That Answer Different Questions<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/via-in-pad-flatness\/#Define_Flatness_Parameters_Before_Quoting_a_Limit\" >Define Flatness Parameters Before Quoting a Limit<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/via-in-pad-flatness\/#Separate_a_Dimple_From_Board-Level_Bow\" >Separate a Dimple From Board-Level Bow<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/via-in-pad-flatness\/#Include_a_Neighboring_Reference_Land\" >Include a Neighboring Reference Land<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/via-in-pad-flatness\/#Read_a_Simple_Height_Example\" >Read a Simple Height Example<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/via-in-pad-flatness\/#Choose_an_Inspection_Method_That_Can_Resolve_the_Feature\" >Choose an Inspection Method That Can Resolve the Feature<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/via-in-pad-flatness\/#Distinguish_a_Surface_Signature_From_Its_Cause\" >Distinguish a Surface Signature From Its Cause<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/via-in-pad-flatness\/#Verify_the_Cap_and_the_Fill_When_the_Drawing_Requires_It\" >Verify the Cap and the Fill When the Drawing Requires It<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/via-in-pad-flatness\/#Inspect_a_Useful_First-Article_Sample\" >Inspect a Useful First-Article Sample<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-11\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/via-in-pad-flatness\/#Carry_Surface_Data_Into_Assembly_Review\" >Carry Surface Data Into Assembly Review<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-12\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/via-in-pad-flatness\/#Release_the_Land_Geometry_and_Its_Evidence_Together\" >Release the Land Geometry and Its Evidence Together<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-13\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/via-in-pad-flatness\/#FAQ\" >FAQ<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-14\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/via-in-pad-flatness\/#Prepare_a_BGA_Land_Review\" >Prepare a BGA Land Review<\/a><\/li><\/ul><\/nav><\/div>\n<div class=\"yzp-no-index\"><\/div><p>A filled and capped via can still leave a depression or a raised area on a BGA land. Inspect the finished pad surface relative to an agreed datum; inspect fill and cap integrity separately. A feature that passes electrical continuity can still be unsuitable for the intended assembly.<\/p>\n<p>Consider a hypothetical high-density processor board with some BGA pads directly over filled vias. The design owner wants to compare those lands with neighboring pads before the first board is assembled.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Identify_the_Surface_That_Will_Receive_Solder\"><\/span>Identify the Surface That Will Receive Solder<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Measure the solderable land after the specified fabrication and finish steps. A flat surface before final plating or finish is not necessarily the final geometry. Name the inspection stage and identify which pads contain the via.<\/p>\n<figure><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/capped-bga-pad-field.jpg\" width=\"1120\" height=\"630\" style=\"max-width:100%;height:auto\" alt=\"Unpopulated gold-finished BGA footprint with nearby components\"><figcaption>AI-generated illustration of a pad field; fill and cap quality cannot be inferred from this image.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Compare_Three_Inspections_That_Answer_Different_Questions\"><\/span>Compare Three Inspections That Answer Different Questions<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>No single inspection proves every part of the construction.<\/p>\n<figure class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Inspection<\/strong><\/td>\n<td><strong>Can address<\/strong><\/td>\n<td><strong>Does not establish alone<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Surface profile<\/td>\n<td>Dimple, protrusion or height difference<\/td>\n<td>Internal void or cap continuity<\/td>\n<\/tr>\n<tr>\n<td>Cross-section<\/td>\n<td>Fill, cap and barrel structure on the section<\/td>\n<td>Every pad on the panel<\/td>\n<\/tr>\n<tr>\n<td>Electrical test<\/td>\n<td>Connectivity and isolation at test time<\/td>\n<td>Assembly planarity or solder behavior<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Define_Flatness_Parameters_Before_Quoting_a_Limit\"><\/span>Define Flatness Parameters Before Quoting a Limit<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>The drawing needs an explicit datum, a method and separate decision limits where applicable. <a href=\"https:\/\/www.eurocircuits.com\/technical-guidelines\/pcb-manufacturing-technology\/via-filling-eurocircuits-have-invested-in-the-itc-thp-30-machine\/\">Eurocircuits&#8217; via filling overview<\/a> describes filling and planarization as process steps; it does not establish the limits for this example.<\/p>\n<figure class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Field<\/strong><\/td>\n<td><strong>Report as<\/strong><\/td>\n<td><strong>Purpose<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Local depression<\/td>\n<td>\u00b5m below a defined reference<\/td>\n<td>Identify the recessed region<\/td>\n<\/tr>\n<tr>\n<td>Local protrusion<\/td>\n<td>\u00b5m above that reference<\/td>\n<td>Identify a raised region<\/td>\n<\/tr>\n<tr>\n<td>Pad-to-pad height<\/td>\n<td>\u00b5m with the agreed datum<\/td>\n<td>Check relative land elevations<\/td>\n<\/tr>\n<tr>\n<td>Sampling<\/td>\n<td>Pad IDs, panel location and method<\/td>\n<td>Reproduce the result<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Separate_a_Dimple_From_Board-Level_Bow\"><\/span>Separate a Dimple From Board-Level Bow<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>A dimple is local to the pad or via region. Board-level shape changes the height over a wider area. A tilted sample can make a profile look sloped; document the leveling and reference before calling the shape a cap defect.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Include_a_Neighboring_Reference_Land\"><\/span>Include a Neighboring Reference Land<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Use a reference surface agreed in advance, such as an adjacent unaffected area when that is appropriate for the measurement. Compare like finish and geometry where possible. Avoid selecting the reference after seeing the result simply because it makes the number smaller.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Read_a_Simple_Height_Example\"><\/span>Read a Simple Height Example<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>If an illustrative surface profile is zero at the agreed reference and reaches \u22128 \u00b5m at the center, the local depression is 8 \u00b5m by that definition. If another point reads +5 \u00b5m, report that separately as a protrusion. These numbers are teaching inputs, not acceptance limits.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Choose_an_Inspection_Method_That_Can_Resolve_the_Feature\"><\/span>Choose an Inspection Method That Can Resolve the Feature<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Ask what the instrument can resolve on the actual pad material and size. The report should name the method, location and how the datum was applied. An ordinary microscope image can show a visible feature but should not be treated as a calibrated height result by itself.<\/p>\n<figure><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/bga-pad-optical-inspection.jpg\" width=\"1120\" height=\"630\" style=\"max-width:100%;height:auto\" alt=\"Bare circuit board under an optical inspection station\"><figcaption>AI-generated illustration of inspection context, not a measurement or process validation.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Distinguish_a_Surface_Signature_From_Its_Cause\"><\/span>Distinguish a Surface Signature From Its Cause<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>A recess alone does not prove a particular fill defect or process setting. Check whether the signature follows via geometry, pad type or panel location. Use the fabrication history and a targeted section when necessary to determine whether the fill, planarization or plating requires investigation.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Verify_the_Cap_and_the_Fill_When_the_Drawing_Requires_It\"><\/span>Verify the Cap and the Fill When the Drawing Requires It<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>If the assembly needs a defined cap and filled structure, specify the agreed checks independently of top surface profile. A smooth-looking land cannot rule out an internal defect. A section also has sampling limits, so identify which land and region it represents.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Inspect_a_Useful_First-Article_Sample\"><\/span>Inspect a Useful First-Article Sample<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Select pads and panel locations that represent the constructions being released. Include via-bearing and comparable non-via lands where relevant. Retain the map so the assembler can connect any later solder finding to the corresponding pad type rather than the panel average.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Carry_Surface_Data_Into_Assembly_Review\"><\/span>Carry Surface Data Into Assembly Review<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>If the first assembly shows a solder anomaly, compare the actual pad, stencil, package and reflow evidence. Do not assume a via caused the issue just because it sits below the land. Use the surface report to guide the investigation, not to replace it.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Release_the_Land_Geometry_and_Its_Evidence_Together\"><\/span>Release the Land Geometry and Its Evidence Together<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>State the pad construction, finish, datum, measurement method, sampling and response to exceptions. See the <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/via-in-pad-plated-over\/\">Best Technology via-in-pad guide<\/a> for the general filled-and-capped construction; this inspection applies to the finished surface.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"FAQ\"><\/span>FAQ<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<h3>Does filling the via guarantee a flat land?<\/h3>\n<p>No. Filling and making a finished pad surface are related but different operations. Check the completed surface under the agreed method, and use the required separate inspection for the fill and cap structure. Do not infer compliance from the word filled on a purchase line.<\/p>\n<h3>Can I judge height from the color of a gold pad?<\/h3>\n<p>No. Lighting and surface reflectivity can change the appearance without a corresponding height change. Use an appropriate and verified profile measurement when the requirement is in micrometers. A photograph may help locate the feature but does not replace the measured height.<\/p>\n<h3>Is there a single dimple limit for all BGAs?<\/h3>\n<p>Do not assume one. The accepted value depends on the governing drawing, construction and assembly requirements. Agree on the definition and datum with the responsible teams before fabrication, especially when different suppliers may use different inspection methods or report the result differently.<\/p>\n<h3>What if the measurement includes solder mask?<\/h3>\n<p>Check whether the datum is supposed to reference the solderable land or a different feature. A mask edge can change a profile and make readings incomparable. The report should show where the scan crossed the surface and how unrelated regions were excluded.<\/p>\n<h3>Does X-ray directly measure a pad dimple?<\/h3>\n<p>Do not use a general X-ray observation as proof of local surface height. X-ray can support different inspection tasks depending on the equipment and method. For a specified dimple or protrusion, use the agreed surface measurement and correlate any structural findings separately.<\/p>\n<h3>Can I average several pads to pass a local limit?<\/h3>\n<p>Only if the governing requirement specifically defines such an average. A mean can hide one outlying pad. When the rule is a maximum local deviation, record individual locations and values so the owner can assess the actual worst case before assembly.<\/p>\n<h3>Why check both depression and protrusion?<\/h3>\n<p>They describe opposite departures from the agreed reference and can affect the assembly differently. A single unsigned number can hide whether the surface was raised or recessed. Keep both directions in the report and compare them with the appropriate requirements for the design.<\/p>\n<h3>When should I repeat first-article checks?<\/h3>\n<p>Review them when a material, via construction, finish, process route or other relevant variable changes. The appropriate sample depends on the approved control plan. Keep the old and new configuration identifiers together so an inspection result cannot be assigned to the wrong build.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Prepare_a_BGA_Land_Review\"><\/span>Prepare a BGA Land Review<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Send the stackup, via and BGA pad drawing, proposed measurement method and acceptance limits to <a href=\"mailto:sales@bestpcbs.com\">the Best Technology team<\/a>.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Check a filled and capped BGA pad for dimples and bumps. Define the measurement datum, separate flatness from fill quality, and inspect first articles.<\/p>\n","protected":false},"author":32827,"featured_media":38462,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_uf_show_specific_survey":0,"_uf_disable_surveys":false,"footnotes":""},"categories":[174],"tags":[9110,9111,62,9109],"class_list":["post-38464","post","type-post","status-publish","format-standard","hentry","category-bestpcb","tag-bga-pad","tag-filled-capped-via","tag-pcb-inspection","tag-via-in-pad-flatness"],"acf":[],"aioseo_notices":[],"aioseo_head":"\n\t\t<!-- All in One SEO 5.0.4 - aioseo.com -->\n\t<meta name=\"description\" content=\"Check a filled and capped BGA pad for dimples and bumps. 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