{"id":38450,"date":"2026-11-06T15:46:03","date_gmt":"2026-11-06T07:46:03","guid":{"rendered":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/parallel-pcb-power-vias\/"},"modified":"2026-11-06T15:46:03","modified_gmt":"2026-11-06T07:46:03","slug":"parallel-pcb-power-vias","status":"publish","type":"post","link":"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/parallel-pcb-power-vias\/","title":{"rendered":"Parallel PCB Power Vias: Why Current Does Not Split Evenly"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_89 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/parallel-pcb-power-vias\/#Follow_the_Current_Beyond_the_Via_Barrel\" >Follow the Current Beyond the Via Barrel<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/parallel-pcb-power-vias\/#Compare_an_Ideal_Array_With_a_Constricted_Layout\" >Compare an Ideal Array With a Constricted Layout<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/parallel-pcb-power-vias\/#Record_Barrel_and_Access_Parameters_Separately\" >Record Barrel and Access Parameters Separately<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/parallel-pcb-power-vias\/#Calculate_Current_for_Two_Unequal_Branches\" >Calculate Current for Two Unequal Branches<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/parallel-pcb-power-vias\/#Compare_Loss_Without_Calling_It_an_Amp_Rating\" >Compare Loss Without Calling It an Amp Rating<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/parallel-pcb-power-vias\/#Check_Where_the_Current_Enters_the_Array\" >Check Where the Current Enters the Array<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/parallel-pcb-power-vias\/#Check_How_Current_Leaves_on_the_Other_Layer\" >Check How Current Leaves on the Other Layer<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/parallel-pcb-power-vias\/#Use_a_Single-Via_Tool_for_the_Right_Question\" >Use a Single-Via Tool for the Right Question<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/parallel-pcb-power-vias\/#Check_Local_Heating_and_Shared_Copper\" >Check Local Heating and Shared Copper<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/parallel-pcb-power-vias\/#Decide_When_a_Distributed_Model_Is_Needed\" >Decide When a Distributed Model Is Needed<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-11\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/parallel-pcb-power-vias\/#Verify_the_First_Board_Under_a_Defined_Load\" >Verify the First Board Under a Defined Load<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-12\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/parallel-pcb-power-vias\/#Release_Geometry_and_Acceptance_Together\" >Release Geometry and Acceptance Together<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-13\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/parallel-pcb-power-vias\/#FAQ\" >FAQ<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-14\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/11\/parallel-pcb-power-vias\/#Prepare_a_Power_Layout_Review\" >Prepare a Power Layout Review<\/a><\/li><\/ul><\/nav><\/div>\n<div class=\"yzp-no-index\"><\/div><p>Parallel PCB power vias share current evenly only when their effective paths are sufficiently similar. A via near the incoming trace can carry more current than one behind a narrow copper neck. A single-via calculator can estimate the barrel, but it cannot see those paths or establish the temperature of the array.<\/p>\n<p>Follow a hypothetical DC power converter board where 4 A must transfer from a top copper pour to a bottom pour. Two paths make the math visible; the same questions apply to larger arrays.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Follow_the_Current_Beyond_the_Via_Barrel\"><\/span>Follow the Current Beyond the Via Barrel<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Draw the path from the upstream copper to each via, down the plated wall and through the downstream copper. That complete path sets the division in a simple resistive model. If the copper is shared between branches, model the shared section separately rather than counting it twice.<\/p>\n<figure><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/power-via-array.jpg\" width=\"1120\" height=\"747\" style=\"max-width:100%;height:auto\" alt=\"Populated power board with a plated via array\"><figcaption>AI-generated illustration of power-board context; not a verified current path or layout recommendation.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Compare_an_Ideal_Array_With_a_Constricted_Layout\"><\/span>Compare an Ideal Array With a Constricted Layout<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Use equal sharing as a starting assumption only when the geometry supports it. This table compares situations for the same current transfer.<\/p>\n<figure class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Layout<\/strong><\/td>\n<td><strong>First assumption<\/strong><\/td>\n<td><strong>Check next<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Symmetric feed and exit<\/td>\n<td>Similar branch paths<\/td>\n<td>Confirm both sides and barrel geometry<\/td>\n<\/tr>\n<tr>\n<td>Narrow feed at one end<\/td>\n<td>Closest path may dominate<\/td>\n<td>Inspect the constriction and current density<\/td>\n<\/tr>\n<tr>\n<td>Common copper bottleneck<\/td>\n<td>All current crosses the neck<\/td>\n<td>Check the neck separately from the vias<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Record_Barrel_and_Access_Parameters_Separately\"><\/span>Record Barrel and Access Parameters Separately<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Use finished dimensions from the manufacturer, not the nominal drill alone. The barrel resistance depends on the length of the conducting path and the copper cross-section, not just hole diameter. The worked example uses assumed branch resistances to isolate the effect of access copper.<\/p>\n<figure class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Parameter<\/strong><\/td>\n<td><strong>Unit<\/strong><\/td>\n<td><strong>Needed for<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Finished hole diameter<\/td>\n<td>mm<\/td>\n<td>Barrel geometry<\/td>\n<\/tr>\n<tr>\n<td>Wall plating thickness<\/td>\n<td>\u00b5m<\/td>\n<td>Copper cross-section<\/td>\n<\/tr>\n<tr>\n<td>Conducting barrel length<\/td>\n<td>mm<\/td>\n<td>Resistive path between used layers<\/td>\n<\/tr>\n<tr>\n<td>Access resistance<\/td>\n<td>m\u03a9 per branch<\/td>\n<td>Copper on both sides of the barrel<\/td>\n<\/tr>\n<tr>\n<td>Load and thermal conditions<\/td>\n<td>A, duty cycle, ambient<\/td>\n<td>Validation under the actual duty<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Calculate_Current_for_Two_Unequal_Branches\"><\/span>Calculate Current for Two Unequal Branches<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Take two independent parallel paths between common nodes. Each barrel is assumed to be 1 m\u03a9. Path A has another 1 m\u03a9 of access resistance, and B another 3 m\u03a9, giving 2 and 4 m\u03a9 total. At 4 A total, current divides inversely with branch resistance: about 2.67 A in A and 1.33 A in B, rather than 2 A each. This DC example neglects temperature feedback and shared copper. For the underlying rule, see <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/current-divider-circuit\/\">how a current divider works<\/a>.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Compare_Loss_Without_Calling_It_an_Amp_Rating\"><\/span>Compare Loss Without Calling It an Amp Rating<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>For the assumed 1 m\u03a9 barrels alone, using current squared times resistance gives approximately 7.1 mW in A and 1.8 mW in B. That does not establish temperature or safety: nearby copper, mutual heating and airflow determine how heat leaves. Use the result to decide where to investigate.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Check_Where_the_Current_Enters_the_Array\"><\/span>Check Where the Current Enters the Array<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Look for the narrowest section between the source and the row of vias. A wide plane beyond the neck cannot remove the neck&#8217;s resistance. Consider moving the feed or opening more copper around the array if the geometry allows, then compare the same load case.<\/p>\n<figure><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/11\/plated-via-coupon.jpg\" width=\"1120\" height=\"630\" style=\"max-width:100%;height:auto\" alt=\"Bare PCB coupon with rows of plated through holes\"><figcaption>AI-generated illustration of via geometry, not a current or temperature test.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Check_How_Current_Leaves_on_the_Other_Layer\"><\/span>Check How Current Leaves on the Other Layer<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>A balanced top feed can still become an uneven array if the bottom exit favors one edge. Inspect the receiving copper and any plane voids, slots or clearances. Run the source-to-load path in the correct direction; looking at only one layer can hide the limiting geometry.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Use_a_Single-Via_Tool_for_the_Right_Question\"><\/span>Use a Single-Via Tool for the Right Question<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>A barrel estimate is useful for first-pass geometry checks. The <a href=\"https:\/\/www.bestpcbs.com\/tools\/PCB-Via-Current-Calculator.html\">Best Technology via current calculator<\/a> addresses via sizing; do not treat a result as proof that multiplying by the via count gives the array&#8217;s continuous rating. Review path resistance and board-level thermal behavior separately.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Check_Local_Heating_and_Shared_Copper\"><\/span>Check Local Heating and Shared Copper<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>An individual branch can be overloaded even when the total drop looks acceptable. Conversely, evenly loaded vias can all heat if their surrounding copper shares a poor heat path. Review the complete board under the specified load, ambient, enclosure and cooling conditions.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Decide_When_a_Distributed_Model_Is_Needed\"><\/span>Decide When a Distributed Model Is Needed<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>If the pours share substantial copper, the simple two-branch model is only a teaching aid. Use an appropriate extraction or field model to compare current density through the copper and vias. For fast switching, include loop inductance and return geometry rather than extending the DC result to all frequencies.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Verify_the_First_Board_Under_a_Defined_Load\"><\/span>Verify the First Board Under a Defined Load<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Compare predicted drop and heating with an approved board test at the intended duty cycle. Record the voltage sense locations, ambient, airflow and temperature observation method. If a hot region appears, inspect the current path and setup before assuming the closest via is the only cause.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Release_Geometry_and_Acceptance_Together\"><\/span>Release Geometry and Acceptance Together<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Document the power path, layer transitions, finished via construction, minimum relevant copper, and the actual verification limits. If changing the drill, plating or copper exit, reassess both electrical loss and temperature. An identical via count is not evidence that the updated board behaves the same.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"FAQ\"><\/span>FAQ<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<h3>Do six vias always carry twice as much as three?<\/h3>\n<p>No. More vias add possible paths, but they do not remove a common bottleneck or guarantee balanced current. Compare the feed and exit geometry, barrel dimensions and heat paths. Validate the actual array under its operating conditions instead of multiplying an isolated-via number.<\/p>\n<h3>Does a via near the connector always carry the most?<\/h3>\n<p>No. Distance from the connector is only one clue. Both the incoming and outgoing copper, their widths, and any shared constrictions matter. A nearby via with a poor exit may carry less than a farther one with a lower complete path resistance.<\/p>\n<h3>Is via plating thickness the same as outer copper weight?<\/h3>\n<p>Not necessarily. The finished wall plating and the outer layer copper are different manufacturing quantities. Request the finished barrel requirement that applies to the holes you are using. Using a foil weight as a substitute for a wall thickness can distort the calculation.<\/p>\n<h3>Does a wider finished hole always lower total path resistance?<\/h3>\n<p>It can increase barrel cross-section for a given plating thickness, but the surrounding copper and allowed clearances may also change. Evaluate the entire connection, not the hole alone. A larger barrel does not fix a narrow copper neck immediately before or after it.<\/p>\n<h3>Can I confirm current sharing with a thermal camera alone?<\/h3>\n<p>No. Temperature reflects heating and cooling, and nearby parts or copper can obscure the source. Use the image as a diagnostic clue, compare it with an electrical model or suitable measurements, and record the observation conditions. Do not infer branch current directly from surface color.<\/p>\n<h3>Does filling the hole with solder make the calculation unnecessary?<\/h3>\n<p>No. The resulting fill and current path may not be controlled as assumed, and the surrounding copper still matters. Do not claim an amp rating from visual fill. Use the specified via construction and evidence appropriate to the actual board and operating load.<\/p>\n<h3>Do DC results apply to pulsed current?<\/h3>\n<p>Not in general. Heating depends on the duty and thermal response, while fast edges can make inductance and return geometry important. Use the actual pulse conditions and an appropriate model or test before treating a DC split as a reliable prediction for switching operation.<\/p>\n<h3>What should be shared with a board supplier?<\/h3>\n<p>Provide the layer stack, drill and plating requirements, power path artwork, load and duty, and acceptance plan. Point out narrow sections near the array rather than sending only a via count. The supplier can review buildability, while the design owner retains responsibility for validating system operation.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Prepare_a_Power_Layout_Review\"><\/span>Prepare a Power Layout Review<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Send the layer stack, finished via requirements, layout revision and load assumptions to <a href=\"mailto:sales@bestpcbs.com\">the Best Technology team<\/a>.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>See how copper access and via resistance change current sharing in parallel PCB power vias, and what to check before trusting a simple via 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