{"id":37857,"date":"2026-10-23T18:08:45","date_gmt":"2026-10-23T10:08:45","guid":{"rendered":"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcb-layer-registration\/"},"modified":"2026-10-23T18:08:45","modified_gmt":"2026-10-23T10:08:45","slug":"pcb-layer-registration","status":"publish","type":"post","link":"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcb-layer-registration\/","title":{"rendered":"How Is PCB Layer Registration Controlled in Multilayer Boards?"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_85 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcb-layer-registration\/#What_Is_the_Difference_Between_Layer_Registration_and_Hole_Registration\" >What Is the Difference Between Layer Registration and Hole Registration?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcb-layer-registration\/#What_Causes_PCB_Layers_to_Become_Misaligned\" >What Causes PCB Layers to Become Misaligned?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcb-layer-registration\/#How_Does_Layer_Misregistration_Affect_Annular_Ring\" >How Does Layer Misregistration Affect Annular Ring?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcb-layer-registration\/#What_PCB_Layer_Registration_Tolerance_Should_You_Specify\" >What PCB Layer Registration Tolerance Should You Specify?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcb-layer-registration\/#How_Are_Inner_Layers_Aligned_Before_Lamination\" >How Are Inner Layers Aligned Before Lamination?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcb-layer-registration\/#How_Does_Lamination_Affect_Layer_Alignment\" >How Does Lamination Affect Layer Alignment?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcb-layer-registration\/#How_Is_X-Ray_Used_to_Check_PCB_Layer_Registration\" >How Is X-Ray Used to Check PCB Layer Registration?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcb-layer-registration\/#What_Can_AOI_Microsections_and_Electrical_Testing_Confirm\" >What Can AOI, Microsections and Electrical Testing Confirm?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcb-layer-registration\/#How_Can_PCB_Design_Reduce_Registration_Risk\" >How Can PCB Design Reduce Registration Risk?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcb-layer-registration\/#What_Files_Are_Needed_to_Review_Layer_Registration\" >What Files Are Needed to Review Layer Registration?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-11\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcb-layer-registration\/#PCB_Layer_Registration_FAQs\" >PCB Layer Registration FAQs<\/a><\/li><\/ul><\/nav><\/div>\n<div class=\"yzp-no-index\"><\/div><p><strong><a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcb-layer-registration\/\">PCB layer registration<\/a><\/strong> is the positional alignment of copper features on different layers of a printed circuit board. If an inner-layer pad shifts away from its intended location, a drilled hole can leave too little copper around the barrel, even when the external artwork looks correct. Reliable multilayer fabrication therefore depends on controlling both copper-layer alignment and the relationship between the laminated stack and the drilling coordinates.<\/p>\n<figure class=\"wp-block-image aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/10\/pcb-layer-registration-hero.jpg\" alt=\"Illustrated multilayer PCB registration preparation with copper cores and tooling targets\" width=\"600\" height=\"400\"><\/figure>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"What_Is_the_Difference_Between_Layer_Registration_and_Hole_Registration\"><\/span>What Is the Difference Between Layer Registration and Hole Registration?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Layer-to-layer registration compares copper features on different layers; hole registration compares a hole with the copper features it must connect to or avoid.<\/strong> The two are related, but they are not interchangeable measurements.<\/p>\n<figure class=\"wp-block-table\">\n<table class=\"has-fixed-layout\">\n<thead>\n<tr>\n<th>Registration check<\/th>\n<th>Features being compared<\/th>\n<th>What an error can affect<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Layer-to-layer<\/td>\n<td>Copper targets, pads or patterns on separate layers<\/td>\n<td>Pad overlap, coupled routing and local clearances<\/td>\n<\/tr>\n<tr>\n<td>Drill-to-copper<\/td>\n<td>Drilled hole center and copper pad or clearance center<\/td>\n<td>Remaining annular ring, breakout or unintended plane contact<\/td>\n<\/tr>\n<tr>\n<td>Solder-mask-to-copper<\/td>\n<td>Mask opening and surface pad<\/td>\n<td>Exposed copper and mask coverage<\/td>\n<\/tr>\n<tr>\n<td>Component placement<\/td>\n<td>Component terminals and outer-layer land pattern<\/td>\n<td>Assembly alignment, not internal copper alignment<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<p>For PCB layer to layer registration, the drawing must identify the reference layer or datum and the features being measured. Comparing every layer with a common reference is not the same as reporting the largest separation between any two layers. A board can meet one stated limit and fail another if the measurement definitions differ.<\/p>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"What_Causes_PCB_Layers_to_Become_Misaligned\"><\/span>What Causes PCB Layers to Become Misaligned?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Misalignment can begin before lamination and change during pressing. Etched cores can change dimensions as copper is removed, while temperature, moisture condition, material direction and processing history affect dimensional stability. Tooling wear, incorrect lay-up orientation or movement during bonding can add further error.<\/p>\n<p>The shape of the error matters as much as its maximum value:<\/p>\n<figure class=\"wp-block-table\">\n<table class=\"has-fixed-layout\">\n<thead>\n<tr>\n<th>Observed pattern<\/th>\n<th>Possible explanation to investigate<\/th>\n<th>Useful comparison<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Similar offset at several targets<\/td>\n<td>Translation or datum mismatch<\/td>\n<td>Target coordinates against the same origin<\/td>\n<\/tr>\n<tr>\n<td>Offset changes direction across the panel<\/td>\n<td>Rotation<\/td>\n<td>Targets near opposite panel edges<\/td>\n<\/tr>\n<tr>\n<td>Offset grows with distance from the center<\/td>\n<td>Scale change<\/td>\n<td>X and Y spans before and after processing<\/td>\n<\/tr>\n<tr>\n<td>Different local errors remain after global alignment<\/td>\n<td>Nonuniform distortion<\/td>\n<td>Multiple targets across the usable panel<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<p>These patterns guide investigation; they do not identify the root cause by themselves. For example, shifting the drilling origin can reduce a uniform offset but cannot remove local distortion already locked into a laminated board.<\/p>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"How_Does_Layer_Misregistration_Affect_Annular_Ring\"><\/span>How Does Layer Misregistration Affect Annular Ring?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Misregistration reduces the narrowest copper ring around a hole. For a circular pad and circular drilled hole, a simple geometric estimate is:<\/p>\n<p><strong>Minimum remaining ring = (minimum pad diameter \u2212 maximum drilled-hole diameter) \/ 2 \u2212 center offset<\/strong><\/p>\n<p>The diameters and offset must describe the same manufacturing stage. A finished plated-hole diameter is smaller than the drilled opening; substituting it without accounting for plating can overstate the copper margin.<\/p>\n<p>Consider a 0.60 mm pad and a 0.30 mm drilled opening, ignoring diameter tolerances for this example:<\/p>\n<figure class=\"wp-block-table\">\n<table class=\"has-fixed-layout\">\n<thead>\n<tr>\n<th>Center offset<\/th>\n<th>Narrowest remaining ring<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>0.00 mm<\/td>\n<td>0.150 mm<\/td>\n<\/tr>\n<tr>\n<td>0.05 mm<\/td>\n<td>0.100 mm<\/td>\n<\/tr>\n<tr>\n<td>0.10 mm<\/td>\n<td>0.050 mm<\/td>\n<\/tr>\n<tr>\n<td>0.15 mm<\/td>\n<td>0.000 mm: geometric tangency<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<figure class=\"wp-block-image aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/10\/pcb-layer-registration-ring.jpg\" alt=\"Schematic comparison of a centered drilled hole and an offset hole inside the same copper pad\" width=\"600\" height=\"400\"><\/figure>\n<p>These values illustrate geometry, not an acceptance specification. Etched pad size, drill size variation, layer movement and drilling position all consume margin. Internal clearances matter too: a shifted hole can approach a plane that it should not contact, even if its connected pad retains copper.<\/p>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"What_PCB_Layer_Registration_Tolerance_Should_You_Specify\"><\/span>What PCB Layer Registration Tolerance Should You Specify?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Specify the tolerance together with its reference, measurement method and affected layer pairs. There is no single PCB registration tolerance that can be applied to every stack-up simply by counting layers or naming an acceptance class.<\/p>\n<p>For a PCB layer to layer registration tolerance, clarify:<\/p>\n<ul class=\"wp-block-list\">\n<li>Whether the limit is layer-to-layer, drill-to-pad, or a combined manufacturing allowance.<\/li>\n<li>Whether it is a radial displacement or separate X and Y limits.<\/li>\n<li>Which targets, layers and panel locations are measured.<\/li>\n<li>Whether the result applies before lamination, after lamination or after drilling.<\/li>\n<li>The applicable specification revision, product class and drawing requirements.<\/li>\n<\/ul>\n<p>An X\/Y allowance is not automatically a radial allowance. If both axes permit 0.05 mm simultaneously, the resulting diagonal displacement can reach approximately 0.071 mm. If the intended limit is a 0.05 mm radius, the drawing should say so.<\/p>\n<p><strong>PCB layer registration tolerance must leave adequate copper and clearance at the actual minimum geometry.<\/strong> For Class 2 boards, layer-to-layer registration must be evaluated against the applicable acceptance criteria and the agreed fabrication requirements together. The geometric example above is not an IPC limit, and a class designation alone is not a complete positional tolerance specification.<\/p>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"How_Are_Inner_Layers_Aligned_Before_Lamination\"><\/span>How Are Inner Layers Aligned Before Lamination?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Inner-layer registration uses features tied to the copper artwork, followed by a controlled method of positioning the cores in the lay-up. Optical registration equipment can locate etched targets and establish tooling holes relative to the actual pattern rather than relying only on the cut edge of the laminate.<\/p>\n<p>Inspection before bonding is equally important. Inner-layer AOI compares the visible etched pattern with the design data to detect defects while the copper is accessible. Correct layer identity, orientation and sequence must then be maintained through lay-up. A perfectly aligned but incorrectly oriented core is still wrong.<\/p>\n<figure class=\"wp-block-image aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/10\/pcb-layer-registration-targets.jpg\" alt=\"Reference-based illustration of an etched copper core with separate optical targets and tooling holes\" width=\"600\" height=\"400\"><\/figure>\n<p>Tooling holes and optical targets perform different jobs: one physically locates material; the other provides a measurable reference to the artwork. Their size, shape and position belong to the fabrication tooling scheme and should not be copied from an unrelated board.<\/p>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"How_Does_Lamination_Affect_Layer_Alignment\"><\/span>How Does Lamination Affect Layer Alignment?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Lamination subjects the lay-up to heat, pressure and resin flow. Material movement during this stage can alter the alignment established at loading. Dimensional compensation therefore needs to reflect the selected laminate, copper distribution and process history, rather than one scaling factor used for every job.<\/p>\n<p>In multilayer PCB design, stack-up symmetry and balanced copper distribution help control dimensional behavior and warpage. They do not guarantee registration on their own. A multilayer PCB stackup also needs consistent material orientation, compatible cores and prepregs, and a controlled bonding sequence.<\/p>\n<p>For an <strong>8 layer PCB<\/strong>, for example, reviewing all internal cores and their target positions provides more information than checking only the two outer layers. Common PCB stackups provide a starting point, but the approved material construction and panel arrangement determine the actual manufacturing route. Sequentially laminated structures require attention to the dimensional changes accumulated over multiple bonding cycles.<\/p>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"How_Is_X-Ray_Used_to_Check_PCB_Layer_Registration\"><\/span>How Is X-Ray Used to Check PCB Layer Registration?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>X-ray inspection can reveal internal copper reference features after lamination, when an optical camera can no longer see them directly. A suitable target design and measurement setup allow the positions of internal features to be compared and can support the choice of drilling references.<\/p>\n<p>The result depends on what the image separates clearly. Overlapping targets, unsuitable geometry or insufficient resolution can make individual layers difficult to distinguish. Reporting a single position from an ambiguous image does not prove that every layer is within tolerance.<\/p>\n<p>X-ray-guided drill registration can optimize drilling relative to the bonded copper stack. <strong>It cannot move copper layers that are already laminated together.<\/strong> If different layers have shifted in different directions, the selected drill position may be a compromise; inadequate remaining margins still require disposition.<\/p>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"What_Can_AOI_Microsections_and_Electrical_Testing_Confirm\"><\/span>What Can AOI, Microsections and Electrical Testing Confirm?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>These methods answer different questions. None should be treated as a complete substitute for the others.<\/p>\n<figure class=\"wp-block-table\">\n<table class=\"has-fixed-layout\">\n<thead>\n<tr>\n<th>Method<\/th>\n<th>Useful evidence<\/th>\n<th>Important limitation<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Inner-layer AOI<\/td>\n<td>Visible copper pattern defects before bonding<\/td>\n<td>Does not show final post-lamination layer positions<\/td>\n<\/tr>\n<tr>\n<td>X-ray registration measurement<\/td>\n<td>Internal target positions in the laminated stack<\/td>\n<td>Requires identifiable targets and suitable resolution<\/td>\n<\/tr>\n<tr>\n<td>Microsection<\/td>\n<td>Local hole-wall, pad and interconnection geometry<\/td>\n<td>A selected section may not intersect the worst offset direction<\/td>\n<\/tr>\n<tr>\n<td>Electrical testing<\/td>\n<td>Opens and shorts covered by the test<\/td>\n<td>Does not quantify remaining annular-ring margin<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<figure class=\"wp-block-image aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/10\/pcb-layer-registration-inspection.jpg\" alt=\"Illustrated panel sampling locations for registration inspection, not a measured X-ray result\" width=\"600\" height=\"400\"><\/figure>\n<p>When a registration concern is investigated, identify the panel, coupon location, layer pair, datum and measurement direction. A microsection through one hole at one location is local evidence; it should not silently become a claim about every hole on the panel. Likewise, passing continuity does not show how much manufacturing margin remains before breakout.<\/p>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"How_Can_PCB_Design_Reduce_Registration_Risk\"><\/span>How Can PCB Design Reduce Registration Risk?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Provide room for the expected manufacturing variation before routing becomes too dense to change. The most useful multilayer PCB design guidelines connect pad and clearance geometry to the proposed fabrication route:<\/p>\n<ol>\n<li>Review pad sizes and antipad clearances using the drilled-hole requirements, not only the finished-hole size.<\/li>\n<li>Keep the artwork, drill files, layer order and stack-up revision consistent.<\/li>\n<li>Evaluate narrow internal clearances and small capture pads early in DFM.<\/li>\n<li>Agree on controlled features and registration acceptance before tooling is finalized.<\/li>\n<li>Recheck the margins if material, panelization, via construction or lamination sequence changes.<\/li>\n<\/ol>\n<p>Our <a href=\"https:\/\/www.bestpcbs.com\/products\/multi-layer-pcb.htm\">multilayer PCB manufacturing<\/a> supports FR4 constructions up to 32 layers, subject to the selected structure and engineering review. Layer count alone does not define the achievable registration tolerance.<\/p>\n<p>For <a href=\"https:\/\/www.bestpcbs.com\/products\/HDI-board.htm\">HDI PCB manufacturing<\/a>, small capture features and sequential build-up make registration especially relevant. We support fine-line HDI designs down to 2\/2 mil under applicable manufacturing conditions; this line\/space capability is not a promise of a particular layer-position tolerance.<\/p>\n<p>Layer alignment can also matter to <a href=\"https:\/\/www.bestpcbs.com\/products\/impedance-control-pcb.htm\">impedance-controlled PCBs<\/a>, particularly where coupling depends on the overlap of conductors on different layers. A simple shift over a wide continuous reference plane does not have the same effect as a shift between broadside-coupled traces. Review the actual structure rather than assuming every offset produces the same impedance change.<\/p>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"What_Files_Are_Needed_to_Review_Layer_Registration\"><\/span>What Files Are Needed to Review Layer Registration?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>At <strong>EBest Circuit (Best Technology)<\/strong>, we provide PCB fabrication and DFM support. Send us the complete fabrication data, layer order, proposed stack-up, drill information and drawing tolerances so we can evaluate the construction before production.<\/p>\n<p>For a specific layer-registration requirement, include the affected layers or vias, intended datum, acceptance criteria and any requested inspection records. If a previous lot showed an offset, its measured coordinates and sample location are more useful than an unscaled photograph alone. We will confirm feasible requirements and the agreed inspection scope for the proposed board; do not assume a generic capability value applies to every layer pair.<\/p>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"PCB_Layer_Registration_FAQs\"><\/span>PCB Layer Registration FAQs<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<h3>1. Are SMT fiducials the same as inner-layer registration targets?<\/h3>\n<p>No. SMT fiducials locate a board or component region for assembly equipment. Inner-layer targets support fabrication alignment or measurement. Their purposes and manufacturing stages differ, even if both use recognizable copper shapes.<\/p>\n<h3>2. Can an electrical test pass when layer registration is poor?<\/h3>\n<p>Yes. A connection may remain continuous while its annular-ring margin is reduced. Electrical test results and geometric acceptance need to be evaluated separately.<\/p>\n<h3>3. Can registration be checked on a finished assembled PCB?<\/h3>\n<p>Some internal features may be examined with suitable X-ray equipment, but components, shields and overlapping copper can limit interpretation. Fabrication targets or coupons and production-stage records are usually more useful for investigating a specific layer-pair offset.<\/p>\n<h3>4. Does adding more copper to a pad always solve misregistration?<\/h3>\n<p>No. A larger pad can improve hole capture, but it can reduce spacing to neighboring copper and change routing or electrical behavior. Correct the error source and review both connection margin and isolation clearance.<\/p>\n<p>For a <strong><a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcb-layer-registration\/\">PCB layer registration<\/a><\/strong> review, send your fabrication package and critical feature requirements to <strong><a href=\"mailto:sales@bestpcbs.com\">sales@bestpcbs.com<\/a><\/strong>. We can assess the multilayer construction and clarify the manufacturing and inspection requirements before you release the board.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>PCB layer registration affects hole capture and copper clearance. Learn how tolerances, lamination, X-ray inspection and annular-ring margins are evaluated.<\/p>\n","protected":false},"author":32826,"featured_media":37853,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_uf_show_specific_survey":0,"_uf_disable_surveys":false,"footnotes":""},"categories":[16,5233],"tags":[668,8959,272],"class_list":["post-37857","post","type-post","status-publish","format-standard","hentry","category-pcb-technology","category-quality","tag-multilayer-pcb","tag-pcb-layer-registration","tag-pcb-manufacturing"],"acf":[],"aioseo_notices":[],"aioseo_head":"\n\t\t<!-- All in One SEO 4.9.10 - aioseo.com -->\n\t<meta name=\"description\" content=\"PCB layer registration affects hole capture and copper clearance. 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