{"id":36708,"date":"2026-10-02T10:20:00","date_gmt":"2026-10-02T02:20:00","guid":{"rendered":"https:\/\/www.bestpcbs.com\/blog\/?p=36708"},"modified":"2026-09-22T18:11:04","modified_gmt":"2026-09-22T10:11:04","slug":"pcie-routing-guidelines","status":"publish","type":"post","link":"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcie-routing-guidelines\/","title":{"rendered":"PCIe Routing Guidelines for PCB Design: Impedance, Length Matching, Vias, and Stackup"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_85 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcie-routing-guidelines\/#What_Are_the_Basic_PCIe_Routing_Guidelines\" >What Are the Basic PCIe Routing Guidelines?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcie-routing-guidelines\/#What_Differential_Impedance_Should_PCIe_Traces_Use\" >What Differential Impedance Should PCIe Traces Use?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcie-routing-guidelines\/#Which_PCIe_Routing_Guidelines_Apply_to_Differential_Pair_Routing\" >Which PCIe Routing Guidelines Apply to Differential Pair Routing?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcie-routing-guidelines\/#How_Much_Spacing_Should_PCIe_Traces_Have\" >How Much Spacing Should PCIe Traces Have?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcie-routing-guidelines\/#How_Much_Length_Matching_Does_PCIe_Need\" >How Much Length Matching Does PCIe Need?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcie-routing-guidelines\/#What_PCIe_Routing_Guidelines_Apply_to_Vias_and_Layer_Changes\" >What PCIe Routing Guidelines Apply to Vias and Layer Changes?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcie-routing-guidelines\/#Where_Should_PCIe_AC_Coupling_Capacitors_Be_Placed\" >Where Should PCIe AC Coupling Capacitors Be Placed?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcie-routing-guidelines\/#When_Do_PCIe_Routes_Need_Low-Loss_Material_or_Backdrilling\" >When Do PCIe Routes Need Low-Loss Material or Backdrilling?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcie-routing-guidelines\/#Which_PCIe_Routing_Guidelines_Should_You_Check_Before_PCB_Release\" >Which PCIe Routing Guidelines Should You Check Before PCB Release?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcie-routing-guidelines\/#FAQs_About_PCIe_Routing_Guidelines\" >FAQs About PCIe Routing Guidelines<\/a><\/li><\/ul><\/nav><\/div>\n<div class=\"yzp-no-index\"><\/div>\n<p><strong><a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/pcie-routing-guidelines\/\" title=\"\">PCIe routing guidelines<\/a> help you control differential impedance, P\/N matching, trace spacing, via transitions, return paths, and PCB stackup so the link can maintain reliable signal integrity at the target data rate.<\/strong> These routing decisions become more sensitive as PCIe speed increases, especially when the channel includes long traces, connectors, multiple layer changes, or thick PCBs.<\/p>\n\n\n\n<p>This guide focuses on the <strong><a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/pcie-routing-guidelines\/\" title=\"\">PCIe routing guidelines<\/a> you can apply directly during PCB layout<\/strong>, including differential impedance, pair routing, spacing, length matching, vias, AC coupling, low-loss materials, backdrilling, and the checks to complete before releasing the PCB for fabrication.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full is-resized\"><a href=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/10\/PCIe-Routing-Guidelines.jpg\"><img loading=\"lazy\" decoding=\"async\" width=\"800\" height=\"500\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/10\/PCIe-Routing-Guidelines.jpg\" alt=\"PCIe Routing Guidelines, https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcie-routing-guidelines\/\" class=\"wp-image-36738\" style=\"aspect-ratio:3\/2;object-fit:cover;width:700px\" srcset=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/10\/PCIe-Routing-Guidelines.jpg 800w, https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/10\/PCIe-Routing-Guidelines-300x188.jpg 300w, https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/10\/PCIe-Routing-Guidelines-768x480.jpg 768w\" sizes=\"auto, (max-width: 800px) 100vw, 800px\" \/><\/a><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"What_Are_the_Basic_PCIe_Routing_Guidelines\"><\/span>What Are the Basic PCIe Routing Guidelines?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Before routing the first lane, confirm the <strong>PCIe generation, transmitter and receiver, channel topology, impedance target, and final PCB stackup<\/strong>. These decisions determine most of the routing constraints that follow.<\/p>\n\n\n\n<p>Use these <strong>PCIe routing guidelines<\/strong> as the starting point:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Define the stackup before setting trace width and P\/N gap.<\/strong> Both depend on dielectric thickness, finished copper, and reference-plane distance.<\/li>\n\n\n\n<li><strong>Use the impedance specified for the actual PCIe interface.<\/strong> Do not assume that every controller, FPGA, SoC, or connector uses the same value.<\/li>\n\n\n\n<li><strong>Route P and N together.<\/strong> Keep both conductors on the same layer with similar bends, neck-downs, pads, and via transitions.<\/li>\n\n\n\n<li><strong>Match P to N before matching separate lanes.<\/strong> Intra-pair skew and lane-to-lane skew are different constraints.<\/li>\n\n\n\n<li><strong>Keep a continuous reference plane beneath the route.<\/strong> Avoid plane splits, slots, and large voids.<\/li>\n\n\n\n<li><strong>Separate neighboring lanes enough to control crosstalk.<\/strong> P\/N gap and pair-to-pair spacing solve different problems.<\/li>\n\n\n\n<li><strong>Minimize layer changes.<\/strong> Every transition introduces vias and can leave an unused via stub.<\/li>\n\n\n\n<li><strong>Keep P\/N via structures symmetrical.<\/strong> Both conductors should see similar drills, pads, antipads, and layer spans.<\/li>\n\n\n\n<li><strong>Route AC coupling capacitors symmetrically.<\/strong> Keep both paths short and balanced through the component footprints.<\/li>\n\n\n\n<li><strong>Use low-loss material or backdrilling only when the route justifies it.<\/strong> Neither should be added automatically because the interface is PCIe Gen 4 or Gen 5.<\/li>\n<\/ul>\n\n\n\n<p>These rules cover the layout decisions that have the greatest direct impact on PCIe routing.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"What_Differential_Impedance_Should_PCIe_Traces_Use\"><\/span>What Differential Impedance Should PCIe Traces Use?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p><strong>Use the differential impedance specified by the controller, FPGA, SoC, connector, or platform you are designing around.<\/strong> An <strong>85 \u03a9 differential target is common in many PCIe implementations<\/strong>, while some chip-to-chip links may use 100 \u03a9. The correct value is the one defined for the actual interface.<\/p>\n\n\n\n<p>Once the target is known, set the geometry from the real PCB construction:<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li><strong>Choose the routing layer and reference plane.<\/strong><\/li>\n\n\n\n<li><strong>Use the actual dielectric thickness and finished copper thickness.<\/strong><\/li>\n\n\n\n<li><strong>Solve trace width and P\/N gap together.<\/strong><\/li>\n\n\n\n<li><strong>Check whether that geometry can pass through the BGA escape and connector area.<\/strong><\/li>\n\n\n\n<li><strong>Recalculate the pair if the stackup changes.<\/strong><\/li>\n<\/ol>\n\n\n\n<p>One of the most important <strong>PCIe routing guidelines<\/strong> is to derive the width and gap from the final stackup rather than copy a geometry from another board. A 4 mil trace with a 6 mil gap can produce a different impedance when dielectric thickness, copper thickness, or reference-plane distance changes.<\/p>\n\n\n\n<p>The P\/N gap should also not be adjusted independently just to make routing easier. <strong>Trace width, pair gap, copper thickness, dielectric thickness, and reference-plane distance form one transmission-line structure.<\/strong><\/p>\n\n\n\n<p>If the nominal geometry cannot pass through a dense BGA breakout, use a <strong>short, symmetrical neck-down<\/strong>. Keep both conductors similar and return to the normal controlled-impedance geometry as soon as the breakout allows.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large is-resized\"><a href=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/10\/PCIe-Routing-Guidelines-2.png\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"683\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/10\/PCIe-Routing-Guidelines-2-1024x683.png\" alt=\"PCIe Routing Guidelines, https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcie-routing-guidelines\/\" class=\"wp-image-36740\" style=\"aspect-ratio:3\/2;object-fit:cover;width:700px\" srcset=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/10\/PCIe-Routing-Guidelines-2-1024x683.png 1024w, https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/10\/PCIe-Routing-Guidelines-2-300x200.png 300w, https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/10\/PCIe-Routing-Guidelines-2-768x512.png 768w, https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/10\/PCIe-Routing-Guidelines-2.png 1536w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/a><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Which_PCIe_Routing_Guidelines_Apply_to_Differential_Pair_Routing\"><\/span>Which PCIe Routing Guidelines Apply to Differential Pair Routing?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p><strong>Route each PCIe P\/N pair as one electrical structure and keep its geometry as consistent as practical from transmitter to receiver.<\/strong> The long straight portion of a route is usually straightforward; BGA breakouts, capacitor pads, connectors, bends, and vias are where asymmetry is more likely to appear.<\/p>\n\n\n\n<p>For the main route:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Keep P and N on the same layer.<\/strong><\/li>\n\n\n\n<li><strong>Maintain the calculated trace width and pair gap.<\/strong><\/li>\n\n\n\n<li><strong>Use similar bends on both conductors.<\/strong><\/li>\n\n\n\n<li><strong>Keep pad entry and exit geometry balanced.<\/strong><\/li>\n\n\n\n<li><strong>Keep BGA neck-down sections short.<\/strong><\/li>\n\n\n\n<li><strong>Avoid branches, unused trace extensions, and conventional test-point stubs.<\/strong><\/li>\n\n\n\n<li><strong>Do not separate P and N for long distances.<\/strong><\/li>\n\n\n\n<li><strong>Avoid routing one conductor around an obstacle while the other remains straight.<\/strong><\/li>\n\n\n\n<li><strong>Minimize unnecessary layer changes.<\/strong><\/li>\n<\/ul>\n\n\n\n<p>The objective is not visual symmetry for its own sake. <strong>P and N should experience nearly the same electrical environment.<\/strong> A short, balanced deviation is usually better than forcing one conductor into a very different path.<\/p>\n\n\n\n<p>Do not make the P\/N gap smaller simply because tighter coupling appears safer. The correct gap comes from the impedance solution. An unnecessarily tight pair can make BGA escape more difficult and increase sensitivity to fabrication variation.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"How_Much_Spacing_Should_PCIe_Traces_Have\"><\/span>How Much Spacing Should PCIe Traces Have?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p><strong>The P\/N gap inside one differential pair and the spacing between separate PCIe pairs are not the same rule.<\/strong><\/p>\n\n\n\n<p>The <strong>P\/N gap<\/strong> is part of the differential-impedance geometry. Once the stackup and impedance target are fixed, keep that gap stable through the main route unless a short constrained region requires a controlled change.<\/p>\n\n\n\n<p>The spacing between different PCIe pairs is mainly used to limit crosstalk. Increase clearance when:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Two lanes run parallel for a long distance.<\/li>\n\n\n\n<li>A PCIe lane runs beside a reference clock.<\/li>\n\n\n\n<li>DDR, USB, Ethernet, or another high-speed interface is nearby.<\/li>\n\n\n\n<li>Switching power circuitry is close to the route.<\/li>\n\n\n\n<li>Several high-speed pairs share a narrow routing corridor.<\/li>\n<\/ul>\n\n\n\n<p>For spacing, <strong>PCIe routing guidelines<\/strong> should distinguish between the geometry that sets impedance and the clearance used to reduce coupling. Parallel length matters as much as physical separation: two pairs close together for a few millimeters do not present the same risk as two pairs running side by side across most of the PCB.<\/p>\n\n\n\n<p>If routing space is limited, <strong>reduce the distance over which two lanes run in parallel before squeezing the clearance along the entire route<\/strong>. Moving one pair earlier, changing routing direction, or shortening the shared corridor can be more useful than applying a tighter global spacing rule.<\/p>\n\n\n\n<p>Rules such as <strong>3W or 5W<\/strong> can be useful as starting heuristics, but they should not be treated as universal PCIe limits. The final spacing should reflect the actual stackup, reference-plane distance, parallel length, and nearby aggressors.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"How_Much_Length_Matching_Does_PCIe_Need\"><\/span>How Much Length Matching Does PCIe Need?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p><strong>Match P to N within each lane first. Do not automatically tune every PCIe lane to exactly the same physical length.<\/strong><\/p>\n\n\n\n<p>Three different constraints are often confused:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Intra-pair skew:<\/strong> the difference between P and N inside one differential pair.<\/li>\n\n\n\n<li><strong>Inter-lane skew:<\/strong> the delay difference between separate PCIe lanes.<\/li>\n\n\n\n<li><strong>Channel reach:<\/strong> the complete electrical path from transmitter to receiver.<\/li>\n<\/ul>\n\n\n\n<p>Practical <strong>PCIe routing guidelines<\/strong> prioritize intra-pair P\/N matching before unnecessary lane-to-lane tuning. Excessive P\/N mismatch reduces differential symmetry, so use the skew limit specified by the selected controller or platform rather than copying a generic value from another design.<\/p>\n\n\n\n<p>PCIe receivers can deskew multiple lanes, which means an x4, x8, or x16 link does not automatically require every pair to have identical copper length. If the platform specifies a lane-to-lane limit, handle it separately from P\/N matching.<\/p>\n\n\n\n<p>When tuning is required:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Correct the mismatch close to where it occurs when practical.<\/strong><\/li>\n\n\n\n<li><strong>Use only as much serpentine routing as necessary.<\/strong><\/li>\n\n\n\n<li><strong>Keep neighboring meander segments far enough apart to limit self-coupling.<\/strong><\/li>\n\n\n\n<li><strong>Avoid dense accordion-style tuning.<\/strong><\/li>\n\n\n\n<li><strong>Do not create a crosstalk problem just to correct a small length difference.<\/strong><\/li>\n<\/ul>\n\n\n\n<p>TX and RX also do not need to have the same physical length simply because they belong to the same PCIe interface. Each direction should satisfy its own routing constraints.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"What_PCIe_Routing_Guidelines_Apply_to_Vias_and_Layer_Changes\"><\/span>What PCIe Routing Guidelines Apply to Vias and Layer Changes?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p><strong>Use as few layer changes as practical and treat each transition as a combined signal-and-return structure.<\/strong> A PCIe via is not automatically a problem; the concern is whether the transition keeps P\/N geometry balanced, preserves the return path, and leaves an acceptable via stub.<\/p>\n\n\n\n<p>When changing layers, check:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>P\/N via symmetry:<\/strong> both signal vias should use similar drills, pads, and layer spans.<\/li>\n\n\n\n<li><strong>Trace entry and exit:<\/strong> keep the approach to both vias balanced.<\/li>\n\n\n\n<li><strong>Antipad geometry:<\/strong> avoid noticeably different plane openings around P and N.<\/li>\n\n\n\n<li><strong>Ground stitching:<\/strong> provide a short return path between ground reference planes.<\/li>\n\n\n\n<li><strong>Unused barrel:<\/strong> identify how much plated via remains above or below the signal exit.<\/li>\n<\/ul>\n\n\n\n<p>A common problem occurs when a signal enters a through via from the top layer and exits on an upper inner layer of a thick PCB. <strong>Most of the barrel below the signal layer remains unused<\/strong>, so the resulting stub can be much longer than it would be if the signal exited near the bottom of the board.<\/p>\n\n\n\n<p>Before specifying backdrilling, check whether you can reduce the stub by changing the routing layer, shortening the via span, or using a blind or buried via. If those options are not practical and the remaining barrel affects the channel, backdrilling becomes a reasonable option.<\/p>\n\n\n\n<p>The reference path must remain continuous as well. Do not cross a plane split simply because P and N cross it together. When moving between two ground-referenced layers, place ground stitching vias close to the signal transition so the return current does not have to take a long detour.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Where_Should_PCIe_AC_Coupling_Capacitors_Be_Placed\"><\/span>Where Should PCIe AC Coupling Capacitors Be Placed?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p><strong>Place PCIe AC coupling capacitors according to the selected device or platform guidance, then route through the footprints as part of the differential pair.<\/strong> The capacitor area should not become a large geometry change in an otherwise controlled channel.<\/p>\n\n\n\n<p>Keep the layout simple:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Use the required capacitance and package.<\/strong><\/li>\n\n\n\n<li><strong>Use matching components on P and N.<\/strong><\/li>\n\n\n\n<li><strong>Align both capacitor footprints.<\/strong><\/li>\n\n\n\n<li><strong>Keep entry and exit routing symmetrical.<\/strong><\/li>\n\n\n\n<li><strong>Keep fan-in and fan-out short.<\/strong><\/li>\n\n\n\n<li><strong>Avoid long neck-down sections.<\/strong><\/li>\n\n\n\n<li><strong>Avoid unused pad extensions or test branches.<\/strong><\/li>\n\n\n\n<li><strong>Check whether another board or module already includes the required AC coupling.<\/strong><\/li>\n<\/ul>\n\n\n\n<p>The preferred transition is:<\/p>\n\n\n\n<p><strong>controlled pair \u2192 short capacitor transition \u2192 controlled pair<\/strong><\/p>\n\n\n\n<p>If one conductor travels through a different pad approach or noticeably longer route than the other, the capacitor region can introduce unnecessary asymmetry.<\/p>\n\n\n\n<p>Also confirm the TX direction before placement. PCIe TX and RX are separate unidirectional channels, so the AC coupling capacitor groups for each direction may be physically located near different devices.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large is-resized\"><a href=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/10\/PCIe-Routing-Guidelines-3-1.png\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"683\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/10\/PCIe-Routing-Guidelines-3-1-1024x683.png\" alt=\"PCIe Routing Guidelines, https:\/\/www.bestpcbs.com\/blog\/2026\/10\/pcie-routing-guidelines\/\" class=\"wp-image-36744\" style=\"aspect-ratio:3\/2;object-fit:cover;width:700px\" srcset=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/10\/PCIe-Routing-Guidelines-3-1-1024x683.png 1024w, https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/10\/PCIe-Routing-Guidelines-3-1-300x200.png 300w, https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/10\/PCIe-Routing-Guidelines-3-1-768x512.png 768w, https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/10\/PCIe-Routing-Guidelines-3-1.png 1536w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/a><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"When_Do_PCIe_Routes_Need_Low-Loss_Material_or_Backdrilling\"><\/span>When Do PCIe Routes Need Low-Loss Material or Backdrilling?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p><strong>Use low-loss material when distributed channel loss is the problem; use backdrilling when a via stub is the problem.<\/strong> These two decisions should be made from the actual route rather than the PCIe generation alone.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><thead><tr><th><strong>Condition<\/strong><\/th><th><strong>What to Check<\/strong><\/th><\/tr><\/thead><tbody><tr><td>Long PCB route<\/td><td>Total insertion loss<\/td><\/tr><tr><td>Multiple connectors<\/td><td>Combined connector and channel loss<\/td><\/tr><tr><td>High-loss laminate<\/td><td>Whether dielectric loss consumes too much margin<\/td><\/tr><tr><td>Rough copper<\/td><td>Conductor-loss contribution<\/td><\/tr><tr><td>Thick PCB with short via span<\/td><td>Remaining via stub<\/td><\/tr><tr><td>Long unused via barrel<\/td><td>Whether backdrilling is warranted<\/td><\/tr><tr><td>Short onboard route<\/td><td>Standard or improved FR-4 may be sufficient<\/td><\/tr><tr><td>Limited Gen 5 margin<\/td><td>Review both material loss and via transitions<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p>Low-loss material becomes more useful when the route is long, several connectors are present, or dielectric and conductor losses consume too much margin. <strong>A short onboard route with few transitions may not justify an expensive low-loss laminate simply because it runs PCIe Gen 4 or Gen 5.<\/strong><\/p>\n\n\n\n<p>Backdrilling addresses a different issue. If a through via leaves a long unused barrel, that stub can create a significant discontinuity. The risk is greater on thicker PCBs where the signal exits close to one side of the board.<\/p>\n\n\n\n<p>The distinction is straightforward:<\/p>\n\n\n\n<p><strong>Low-loss laminate reduces loss along the route. Backdrilling reduces the discontinuity caused by unused via barrel.<\/strong><\/p>\n\n\n\n<p>One does not replace the other.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Which_PCIe_Routing_Guidelines_Should_You_Check_Before_PCB_Release\"><\/span>Which PCIe Routing Guidelines Should You Check Before PCB Release?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Before generating final fabrication data, use these <strong>PCIe routing guidelines<\/strong> as a final check of the actual routed channel rather than relying only on the CAD rule report.<\/p>\n\n\n\n<p>Confirm the following:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Is the differential impedance based on the final PCB stackup?<\/strong><\/li>\n\n\n\n<li><strong>Do P and N stay on the same layer through the main route?<\/strong><\/li>\n\n\n\n<li><strong>Are BGA neck-downs short and symmetrical?<\/strong><\/li>\n\n\n\n<li><strong>Does P\/N skew meet the applicable requirement?<\/strong><\/li>\n\n\n\n<li><strong>Have lane-to-lane limits been checked separately where required?<\/strong><\/li>\n\n\n\n<li><strong>Are long parallel PCIe lanes sufficiently separated?<\/strong><\/li>\n\n\n\n<li><strong>Are clocks and other strong aggressors kept away from the route?<\/strong><\/li>\n\n\n\n<li><strong>Does every route section have a continuous reference plane?<\/strong><\/li>\n\n\n\n<li><strong>Do layer transitions include an appropriate return path?<\/strong><\/li>\n\n\n\n<li><strong>Are P\/N signal vias symmetrical?<\/strong><\/li>\n\n\n\n<li><strong>Have long unused via stubs been identified?<\/strong><\/li>\n\n\n\n<li><strong>Are AC coupling capacitors routed symmetrically?<\/strong><\/li>\n\n\n\n<li><strong>Does the selected PCB material provide enough loss margin?<\/strong><\/li>\n\n\n\n<li><strong>Are required backdrill locations clearly defined?<\/strong><\/li>\n\n\n\n<li><strong>Has the stackup remained unchanged since the impedance geometry was calculated?<\/strong><\/li>\n<\/ul>\n\n\n\n<p>If several of these items are difficult to confirm, review the routing before release. The final layout should keep <strong>impedance, P\/N symmetry, spacing, length matching, vias, and return paths consistent across the same PCIe channel<\/strong>, rather than simply passing separate CAD checks.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"FAQs_About_PCIe_Routing_Guidelines\"><\/span>FAQs About PCIe Routing Guidelines<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p><strong>Q1: Can PCIe P and N be swapped?<\/strong><br><strong>A1: Many PCIe implementations support polarity inversion within a differential pair.<\/strong> Confirm that the selected controller and endpoint support it before using P\/N swapping to simplify routing.<\/p>\n\n\n\n<p><strong>Q2: Can PCIe lanes be reordered during BGA breakout?<\/strong><br><strong>A2: Only when the selected devices support lane reversal or lane mapping.<\/strong> Lane reordering is different from swapping P and N within one differential pair.<\/p>\n\n\n\n<p><strong>Q3: Can PCIe traces use 90-degree bends?<\/strong><br><strong>A3: Avoid abrupt geometry changes where practical.<\/strong> Smooth or 45-degree routing is usually easier to keep symmetrical, but maintaining consistent P\/N geometry matters more than the visual bend angle alone.<\/p>\n\n\n\n<p><strong>Q4: Can PCIe traces run on an outer PCB layer?<\/strong><br><strong>A4: Yes, as long as the outer-layer geometry is designed for the required impedance.<\/strong> Include solder mask and the actual reference-plane distance in the impedance calculation.<\/p>\n\n\n\n<p><strong>Q5: Does solder mask affect PCIe impedance?<\/strong><br><strong>A5: Yes, particularly for microstrip routing.<\/strong> Solder mask changes the dielectric environment around the trace and should be included in the impedance model.<\/p>\n\n\n\n<p><strong>Q6: Can test points be added to PCIe traces?<\/strong><br><strong>A6: Avoid conventional branched test points because they create stubs.<\/strong> If measurement access is required, use a probing structure suitable for the required bandwidth.<\/p>\n\n\n\n<p><strong>Q7: Can PCIe traces pass through a dense BGA breakout?<\/strong><br><strong>A7: Yes.<\/strong> Use a short, symmetrical neck-down where necessary and return to the normal controlled-impedance geometry after leaving the escape region.<\/p>\n\n\n\n<p><strong>Q8: Can PCIe and USB share the same routing layer?<\/strong><br><strong>A8: Yes, if the interfaces have enough separation and do not run parallel for unnecessarily long distances.<\/strong> Each interface should still follow its own impedance and routing constraints.<\/p>\n\n\n\n<p><strong>Q9: Does fiber weave affect PCIe routing?<\/strong><br><strong>A9: It can become relevant on longer, higher-speed routes because P and N may travel through different glass and resin distributions.<\/strong> If skew margin is tight, review the laminate construction and routing direction.<\/p>\n\n\n\n<p><strong>Q10: Should ground copper be poured next to PCIe pairs?<\/strong><br><strong>A10: Only when it is intentionally included in the impedance geometry.<\/strong> Nearby copper with inconsistent clearance can change both impedance and coupling along the route.<\/p>\n\n\n\n<p>Applying these <strong>PCIe routing guidelines<\/strong> consistently helps keep impedance, P\/N symmetry, spacing, vias, and reference paths under control before the board reaches fabrication. Before release, verify that the <strong>final stackup, controlled-impedance geometry, P\/N matching, reference planes, via structure, and material still match the assumptions used during layout<\/strong>.<\/p>\n\n\n\n<p>If you want to review the manufacturability of a completed PCIe PCB before production, send your <strong>Gerber or ODB++ files, proposed stackup, impedance requirements, quantity, and delivery target<\/strong> to <strong><a>sales@bestpcbs.com<\/a><\/strong>.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>PCIe routing guidelines help you control differential impedance, P\/N matching, trace spacing, via transitions, return paths, and PCB stackup so the link can maintain reliable signal integrity at the target data rate. These routing decisions become more sensitive as PCIe speed increases, especially when the channel includes long traces, connectors, multiple layer changes, or thick [&hellip;]<\/p>\n","protected":false},"author":33247,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_uf_show_specific_survey":0,"_uf_disable_surveys":false,"footnotes":""},"categories":[175,174,5789],"tags":[8629,8630,8627],"class_list":["post-36708","post","type-post","status-publish","format-standard","hentry","category-best-pcb","category-bestpcb","category-pcb-design","tag-pcie-differential-pair-routing","tag-pcie-length-matching","tag-pcie-routing-guidelines"],"acf":[],"aioseo_notices":[],"aioseo_head":"\n\t\t<!-- All in One SEO 4.9.10 - aioseo.com -->\n\t<meta name=\"description\" content=\"Learn PCIe routing guidelines for differential impedance, length matching, trace spacing, vias, stackup, AC coupling, and PCB layout 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