{"id":36537,"date":"2026-09-21T14:22:40","date_gmt":"2026-09-21T06:22:40","guid":{"rendered":"https:\/\/www.bestpcbs.com\/blog\/?p=36537"},"modified":"2026-09-21T14:24:35","modified_gmt":"2026-09-21T06:24:35","slug":"cowos-l","status":"publish","type":"post","link":"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/cowos-l\/","title":{"rendered":"CoWoS-L Explained: RDL and LSI for Larger AI Packages"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_85 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/cowos-l\/#What_Is_CoWoS-L_Packaging\" >What Is CoWoS-L Packaging?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/cowos-l\/#How_Do_RDL_and_LSI_Work_Together_in_CoWoS-L\" >How Do RDL and LSI Work Together in CoWoS-L?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/cowos-l\/#Why_Can_CoWoS-L_Support_Larger_Packages\" >Why Can CoWoS-L Support Larger Packages?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/cowos-l\/#How_Is_a_CoWoS-L_Package_Manufactured\" >How Is a CoWoS-L Package Manufactured?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/cowos-l\/#How_Does_CoWoS-L_Support_Power_Delivery\" >How Does CoWoS-L Support Power Delivery?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/cowos-l\/#Where_Is_CoWoS-L_Packaging_Used\" >Where Is CoWoS-L Packaging Used?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/cowos-l\/#What_PCB_Assembly_Checks_Matter_for_CoWoS-L_Packages\" >What PCB Assembly Checks Matter for CoWoS-L Packages?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/cowos-l\/#FAQs_About_CoWoS-L\" >FAQs About CoWoS-L<\/a><\/li><\/ul><\/nav><\/div>\n<div class=\"yzp-no-index\"><\/div><p><a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/cowos-l\/\">CoWoS-L<\/a> combines a redistribution-layer (RDL) interposer with local silicon interconnects (LSI). The RDL spans the larger routing platform; embedded silicon bridges provide dense links at selected die interfaces. This division helps integrate more logic and high-bandwidth memory without using one continuous silicon interposer across the full area.<\/p>\n<figure style=\"max-width: 600px; margin: 24px auto;\"><img decoding=\"async\" style=\"width: 100%; max-width: 600px; max-height: 400px; height: auto; object-fit: contain;\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/09\/cowos-l-hero.jpg\" alt=\"Conceptual CoWoS-L package with embedded local silicon interconnects\" data-first-enter-image=\"true\" \/><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"What_Is_CoWoS-L_Packaging\"><\/span>What Is CoWoS-L Packaging?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>CoWoS-L packaging is TSMC\u2019s CoWoS architecture that embeds local silicon interconnects within an RDL-based interposer for large multi-die computing packages.<\/p>\n<p>A CoWoS-L cross section contains logic dies and HBM at the top, an interposer incorporating RDL and local silicon beneath them, and a separate package substrate below. RDL means redistribution layer: patterned conductors redistribute connections across the platform. LSI means local silicon interconnect: dense silicon-based routing placed where neighboring die interfaces need it.<\/p>\n<p>Calling this only an \u201corganic interposer\u201d misses the embedded silicon and molded integration structure. It is not silicon-free, and its package substrate is not the system PCB. For the foundry context, see our introduction to <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/taiwan-semiconductor-manufacturing-company\/\">TSMC\u2019s manufacturing technologies<\/a>.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"How_Do_RDL_and_LSI_Work_Together_in_CoWoS-L\"><\/span>How Do RDL and LSI Work Together in CoWoS-L?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>LSI handles dense local die-to-die connections, while RDL distributes connections over the wider interposer footprint.<\/p>\n<figure style=\"max-width: 600px; margin: 24px auto;\"><img decoding=\"async\" style=\"width: 100%; max-width: 600px; max-height: 400px; height: auto; object-fit: contain;\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/09\/cowos-l-lsi-routing-v2.jpg\" alt=\"Local die-to-die signal path within the silicon bridge above wider RDL routing\" \/><\/figure>\n<div class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Structure<\/strong><\/td>\n<td><strong>Location<\/strong><\/td>\n<td><strong>Interconnect role<\/strong><\/td>\n<\/tr>\n<tr>\n<td>LSI<\/td>\n<td>Selected neighboring die interfaces<\/td>\n<td>High-density local links using fine silicon-based wiring<\/td>\n<\/tr>\n<tr>\n<td>RDL<\/td>\n<td>Across the wider interposer<\/td>\n<td>Broader redistribution and integration with the embedded structures<\/td>\n<\/tr>\n<tr>\n<td>Package substrate<\/td>\n<td>Below the interposer<\/td>\n<td>Connections toward the finished component\u2019s board interface<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n<p>TSMC describes CoWoS-L LSI with multiple layers of submicron copper wiring and connections including SoC-to-SoC, SoC-to-chiplet, and SoC-to-HBM. The bridge occupies the region serving those interfaces; it is not simply a small silicon support underneath an arbitrary part of the package.<\/p>\n<p>Consider two logic dies whose high-density interfaces face each other. An LSI region can connect those edges while the wider RDL carries other connections. Rotating one die may move its interface away from the intended landing region, forcing changes to bridge position and routing. Die orientation and LSI placement must therefore be co-designed.<\/p>\n<p>The bridge does not generate bandwidth by itself. Link width, signaling rate, electrical characteristics, and the transmitting and receiving circuits still determine usable throughput.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Why_Can_CoWoS-L_Support_Larger_Packages\"><\/span>Why Can CoWoS-L Support Larger Packages?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>CoWoS-L extends the interposer footprint through a wider RDL platform while concentrating fine silicon routing at local interfaces, instead of enlarging one continuous silicon interposer everywhere.<\/p>\n<p>TSMC\u2019s public overview identifies a 3.5-reticle CoWoS-L generation that entered production in 2024. This is a dated technology generation, not a permanent maximum. Reticle multiples describe interposer scale relative to an exposure field; they do not specify the component\u2019s outer dimensions, BGA pitch, or HBM count.<\/p>\n<ul>\n<li><strong>More placement area:<\/strong> the platform can accommodate additional or larger logic and memory components when supported by the package design.<\/li>\n<li><strong>Localized fine wiring:<\/strong> high-density silicon regions follow the die interfaces rather than covering the entire footprint.<\/li>\n<li><strong>Separate size limits:<\/strong> interposer area, package substrate outline, and cooling assembly envelope remain different dimensions.<\/li>\n<\/ul>\n<p>Larger still means more manufacturing coordination. Mold, copper, silicon, and the organic substrate respond differently to temperature. Warpage, interconnect stress, routing yield, and cooling all require qualification. Less full-area silicon does not prove that every CoWoS-L product is cheaper than a CoWoS-S alternative.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"How_Is_a_CoWoS-L_Package_Manufactured\"><\/span>How Is a CoWoS-L Package Manufactured?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>The CoWoS-L process flow integrates local silicon interconnects into a molded RDL platform, attaches the top dies, and completes the assembly on a package substrate.<\/p>\n<ol>\n<li><strong>Plan the floorplan:<\/strong> align SoC, chiplet, and HBM interface locations with the required LSI regions and reserve power-routing space.<\/li>\n<li><strong>Integrate the embedded structures:<\/strong> incorporate the local silicon elements, and applicable embedded passive components, into the reconstituted interposer structure.<\/li>\n<li><strong>Form the RDL connections:<\/strong> create the redistribution wiring that connects the embedded regions and wider package interfaces.<\/li>\n<li><strong>Attach the top dies:<\/strong> TSMC describes a chip-last approach in which the interposer platform is prepared before top-chip assembly.<\/li>\n<li><strong>Complete substrate integration and verification:<\/strong> assemble the package substrate and thermal structure and verify links, power behavior, and reliability.<\/li>\n<\/ol>\n<figure style=\"max-width: 600px; margin: 24px auto;\"><img decoding=\"async\" style=\"width: 100%; max-width: 600px; max-height: 400px; height: auto; object-fit: contain;\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/09\/cowos-l-process-flow.jpg\" alt=\"CoWoS-L functional stages from floorplan through assembly and verification\" \/><\/figure>\n<p>Critical controls include embedded-element position, RDL registration, surface planarity, and joint formation. A displaced bridge or a local height error can compromise the fine die interface even if the overall package outline is correct.<\/p>\n<p>This sequence describes functional stages, not a proprietary process recipe. Exact mold materials, bonding temperatures, tolerances, and inspection acceptance criteria must come from the qualified package process.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"How_Does_CoWoS-L_Support_Power_Delivery\"><\/span>How Does CoWoS-L Support Power Delivery?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>CoWoS-L supports power delivery through its interconnect network and the integration of stand-alone embedded deep trench capacitors (eDTCs) beneath the SoC.<\/p>\n<figure style=\"max-width: 600px; margin: 24px auto;\"><img decoding=\"async\" style=\"width: 100%; max-width: 600px; max-height: 400px; height: auto; object-fit: contain;\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/09\/cowos-l-power-delivery.jpg\" alt=\"Embedded eDTC beneath the SoC within the RDL interposer above a separate package substrate\" \/><\/figure>\n<p>TSMC identifies this eDTC integration in its <a href=\"https:\/\/3dfabric.tsmc.com\/english\/dedicatedFoundry\/technology\/cowos.htm\">official CoWoS technology overview<\/a>. Placing capacitance near the load can shorten the local current loop and reduce the inductive penalty of supplying rapid current changes. The benefit depends on the actual connection geometry, capacitor characteristics, and complete power network.<\/p>\n<ul>\n<li><strong>Local transient support:<\/strong> nearby capacitance supplies part of a fast current demand before more distant supply paths respond.<\/li>\n<li><strong>Power-path coordination:<\/strong> package conductors, board planes, capacitors, and voltage regulators must meet the device\u2019s supply limits together.<\/li>\n<li><strong>Impedance control:<\/strong> capacitance and interconnect inductance can create resonances, so adding capacitance is not automatically an improvement at every frequency.<\/li>\n<\/ul>\n<p>For an illustrative target, a permitted 30 mV voltage change during a 100 A current step gives Z = \u0394V\/\u0394I = 0.3 m\u03a9. These are example inputs, not a CoWoS-L rating. A real design needs its own tolerance and frequency-dependent package, board, and regulator models.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Where_Is_CoWoS-L_Packaging_Used\"><\/span>Where Is CoWoS-L Packaging Used?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>CoWoS-L is used for large AI and HPC packages that need dense local connections among logic dies, chiplets, and HBM on a larger interposer platform.<\/p>\n<ul>\n<li><strong>Multi-die AI accelerators:<\/strong> local bridges connect the compute interfaces, while the wider floorplan accommodates logic and memory integration.<\/li>\n<li><strong>HBM-based computing packages:<\/strong> SoC-to-HBM connections combine local routing density with space for the required memory arrangement.<\/li>\n<li><strong>Chiplet-based HPC designs:<\/strong> dense connections between selected chiplets support integration without making every part of the routing platform silicon.<\/li>\n<\/ul>\n<p>TSMC\u2019s disclosed SoC-to-SoC, SoC-to-chiplet, and SoC-to-HBM connection forms support these application categories. They are not a claim that every chiplet processor or AI accelerator uses CoWoS-L. Naming a particular product requires a disclosed packaging variant, not an inference from its HBM count or performance.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"What_PCB_Assembly_Checks_Matter_for_CoWoS-L_Packages\"><\/span>What PCB Assembly Checks Matter for CoWoS-L Packages?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>PCB assembly checks must follow the specific finished component or module\u2019s land pattern, handling limits, reflow instructions, warpage requirements, and thermal-mechanical design.<\/p>\n<ul>\n<li><strong>Board interface:<\/strong> confirm whether the delivered item is a directly soldered component or a module with its own board\/connector interface.<\/li>\n<li><strong>Land pattern and escape routing:<\/strong> use the released ball map and pad geometry; LSI dimensions do not become PCB trace dimensions.<\/li>\n<li><strong>Moisture handling and reflow:<\/strong> use the device\u2019s specified storage, exposure, and thermal-profile limits, not a generic \u201cCoWoS-L temperature.\u201d<\/li>\n<li><strong>Coplanarity and support:<\/strong> review the component\u2019s allowed deformation, board support, heatsink loads, and attachment keep-outs.<\/li>\n<li><strong>Inspection and testing:<\/strong> agree on accessible joint-inspection methods and electrical or functional tests appropriate to the assembly. Visual inspection alone cannot verify hidden BGA joints.<\/li>\n<\/ul>\n<p>Our <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/advanced-hdi-pcbs\/\">advanced HDI PCB guide<\/a> covers board-level routing options. At EBest Circuit, we review PCB fabrication and PCBA requirements against the actual design and component documentation\u2014not the interposer\u2019s marketing dimensions. Send your Gerber files, stackup, BOM, quantities, and component assembly specifications to <a href=\"mailto:sales@bestpcbs.com\">sales@bestpcbs.com<\/a>. This board-level support is separate from TSMC\u2019s CoWoS-L package manufacturing.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"FAQs_About_CoWoS-L\"><\/span>FAQs About CoWoS-L<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Does CoWoS-L eliminate silicon?<\/strong><\/p>\n<p>No. It retains silicon in local interconnect regions. The wider RDL platform changes where silicon is used, not whether silicon is present.<\/p>\n<p><strong>Is LSI another processor?<\/strong><\/p>\n<p>No. In CoWoS-L, LSI is a local silicon interconnect structure that routes signals between die interfaces; it is not an additional computing die.<\/p>\n<p><strong>Is one LSI bridge enough for every package?<\/strong><\/p>\n<p>Not necessarily. The number and location of bridges follow the interfaces being connected. Multiple logic dies and HBM stacks can require several local regions.<\/p>\n<p><strong>Does an embedded eDTC replace PCB decoupling?<\/strong><\/p>\n<p>No. Embedded capacitance supports part of the local supply network. Board capacitors and the voltage regulator must still satisfy the component\u2019s wider power-delivery requirements.<\/p>\n<p><strong>Is 3.5 reticles the maximum CoWoS-L size?<\/strong><\/p>\n<p>No. It identifies a published production generation rather than a permanent ceiling. Obtain the qualified dimensions and availability for the intended design instead of treating a roadmap target as a released package.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Learn how CoWoS-L combines RDL, local silicon interconnects and embedded capacitors for large AI packages, with practical PCB assembly checks.<\/p>\n","protected":false},"author":623,"featured_media":36533,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_uf_show_specific_survey":0,"_uf_disable_surveys":false,"footnotes":""},"categories":[175,5789,16],"tags":[8562,8565,8566,8563,8564],"class_list":["post-36537","post","type-post","status-publish","format-standard","hentry","category-best-pcb","category-pcb-design","category-pcb-technology","tag-cowos-l","tag-cowos-l-cross-section","tag-cowos-l-lsi","tag-cowos-l-packaging","tag-cowos-l-process-flow"],"acf":[],"aioseo_notices":[],"aioseo_head":"\n\t\t<!-- All in One SEO 4.9.10 - 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