{"id":35635,"date":"2026-09-10T08:47:26","date_gmt":"2026-09-10T00:47:26","guid":{"rendered":"https:\/\/www.bestpcbs.com\/blog\/?p=35635"},"modified":"2026-09-10T08:49:21","modified_gmt":"2026-09-10T00:49:21","slug":"co-packaged-optics","status":"publish","type":"post","link":"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/co-packaged-optics\/","title":{"rendered":"What Is Co-Packaged Optics (CPO)? Technology, Applications, Challenges, and PCB Design"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_85 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/co-packaged-optics\/#What_Is_Co-Packaged_Optics_CPO\" >What Is Co-Packaged Optics (CPO)?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/co-packaged-optics\/#How_Does_Co-Packaged_Optics_Work\" >How Does Co-Packaged Optics Work?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/co-packaged-optics\/#What_Technologies_Make_Co-Packaged_Optics_Possible\" >What Technologies Make Co-Packaged Optics Possible?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/co-packaged-optics\/#Co-Packaged_Optics_vs_Pluggable_Optics_What_Is_the_Difference\" >Co-Packaged Optics vs Pluggable Optics: What Is the Difference?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/co-packaged-optics\/#Co-Packaged_Optics_vs_NPO_vs_LPO_How_Do_They_Compare\" >Co-Packaged Optics vs NPO vs LPO: How Do They Compare?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/co-packaged-optics\/#What_Are_the_Main_Benefits_of_Co-Packaged_Optics\" >What Are the Main Benefits of Co-Packaged Optics?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/co-packaged-optics\/#What_Are_the_Main_Challenges_of_Co-Packaged_Optics\" >What Are the Main Challenges of Co-Packaged Optics?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/co-packaged-optics\/#Why_Is_Co-Packaged_Optics_Important_for_AI_Data_Centers\" >Why Is Co-Packaged Optics Important for AI Data Centers?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/co-packaged-optics\/#Where_Is_Co-Packaged_Optics_Used_Today\" >Where Is Co-Packaged Optics Used Today?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/co-packaged-optics\/#How_Does_Advanced_Packaging_Support_Co-Packaged_Optics\" >How Does Advanced Packaging Support Co-Packaged Optics?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-11\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/co-packaged-optics\/#How_Does_Co-Packaged_Optics_Change_PCB_and_System_Design\" >How Does Co-Packaged Optics Change PCB and System Design?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-12\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/co-packaged-optics\/#What_PCB_Requirements_Matter_in_Co-Packaged_Optics_Systems\" >What PCB Requirements Matter in Co-Packaged Optics Systems?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-13\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/co-packaged-optics\/#What_Should_You_Consider_When_Manufacturing_PCBs_for_CPO_Hardware\" >What Should You Consider When Manufacturing PCBs for CPO Hardware?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-14\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/co-packaged-optics\/#FAQs_About_Co-Packaged_Optics\" >FAQs About Co-Packaged Optics<\/a><\/li><\/ul><\/nav><\/div>\n<div class=\"yzp-no-index\"><\/div>\n<p><a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/co-packaged-optics\/\">Co-Packaged Optics<\/a> (CPO) is an optical interconnect architecture that places optical engines close to high-bandwidth chips such as switch ASICs, processors, and accelerators. By shortening the electrical path between the chip and the optical interface, CPO can reduce high-speed signal loss, lower I\/O power, and support much higher bandwidth density than conventional front-panel pluggable optics.<\/p>\n\n\n\n<p>CPO is moving from an emerging concept into real high-capacity networking hardware, driven particularly by AI data centers and hyperscale computing. For hardware engineers, this shift also changes how advanced packaging, thermal management, fiber routing, power delivery, PCB stackups, and system integration are approached.<\/p>\n\n\n\n<figure class=\"wp-block-image\"><img decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/09\/co-packaged-optics-cpo-hero.jpg\" alt=\"Co-Packaged Optics CPO architecture with ASIC, optical engines and fiber\"\/><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"What_Is_Co-Packaged_Optics_CPO\"><\/span>What Is Co-Packaged Optics (CPO)?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Co-Packaged Optics integrates optical engines within or immediately beside the package of a high-performance electronic chip, allowing high-speed electrical signals to travel only a short distance before being converted to light.<\/p>\n\n\n\n<p>In a conventional pluggable-optics architecture, signals travel from the ASIC across the PCB to optical transceivers installed at the front panel. CPO moves this electrical-to-optical conversion much closer to the silicon.<\/p>\n\n\n\n<div class=\"flow\">ASIC or processor \u2192 short electrical connection \u2192 optical engine \u2192 fiber<\/div>\n\n\n\n<p>The package can contain separate electronic and photonic dies rather than integrating every function onto one chip. CPO is therefore an optical and electronic integration architecture, not a single type of optical component.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"How_Does_Co-Packaged_Optics_Work\"><\/span>How Does Co-Packaged Optics Work?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Co-Packaged Optics works by converting high-speed electrical data into optical signals close to the ASIC or processor and carrying the longer-distance portion of the link over fiber.<\/p>\n\n\n\n<figure class=\"wp-block-image\"><img decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/09\/co-packaged-optics-signal-flow.jpg\" alt=\"Co-Packaged Optics transmit and receive signal flow from ASIC to optical engine and fiber\"\/><\/figure>\n\n\n\n<p>A typical transmit path is:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The ASIC generates high-speed electrical data.<\/li>\n\n\n\n<li>A short electrical connection carries it to the optical engine.<\/li>\n\n\n\n<li>Driver electronics prepare the signal.<\/li>\n\n\n\n<li>A photonic integrated circuit modulates light with the data.<\/li>\n\n\n\n<li>Fiber carries the optical signal to another device.<\/li>\n<\/ul>\n\n\n\n<p>The receive path reverses the process:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Fiber delivers the incoming optical signal.<\/li>\n\n\n\n<li>A photodetector converts light into an electrical signal.<\/li>\n\n\n\n<li>A TIA and related electronics process the signal.<\/li>\n\n\n\n<li>The data reaches the ASIC over a short electrical connection.<\/li>\n<\/ul>\n\n\n\n<p>Many CPO architectures use an external laser source (ELS). Light is generated away from the ASIC and delivered to the optical engine through fiber. OIF has standardized external-laser approaches for co-packaged optical systems through its ELSFP work, including field-replaceable laser modules.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"What_Technologies_Make_Co-Packaged_Optics_Possible\"><\/span>What Technologies Make Co-Packaged Optics Possible?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>CPO relies on silicon photonics, photonic integrated circuits, high-speed electronics, precision optical coupling, and heterogeneous integration working together.<\/p>\n\n\n\n<p><strong>Silicon photonics<\/strong><\/p>\n\n\n\n<p>Silicon photonics enables optical functions such as waveguides, modulators, couplers, and photodetectors to be fabricated in compact semiconductor-based devices.<\/p>\n\n\n\n<p><strong>Photonic integrated circuits<\/strong><\/p>\n\n\n\n<p>The PIC handles functions such as optical modulation, detection, routing, and coupling. Multiple optical channels can be integrated into one photonic engine to increase aggregate bandwidth.<\/p>\n\n\n\n<p><strong>High-speed electronic ICs<\/strong><\/p>\n\n\n\n<p>Drivers, TIAs, clocking circuits, and other interface electronics connect the optical section to the main ASIC.<\/p>\n\n\n\n<p><strong>External laser technology<\/strong><\/p>\n\n\n\n<p>Many architectures separate the laser from the optical engine to improve thermal conditions and serviceability.<\/p>\n\n\n\n<p><strong>Precision optical coupling<\/strong><\/p>\n\n\n\n<p>Fiber must be accurately aligned with the photonic interface. Small positional errors can increase coupling loss, so optical assembly requires much tighter mechanical control than ordinary board-level connectors.<\/p>\n\n\n\n<p>These technologies provide the functional building blocks. Bringing them into one compact hardware platform is primarily an advanced-packaging task.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Co-Packaged_Optics_vs_Pluggable_Optics_What_Is_the_Difference\"><\/span>Co-Packaged Optics vs Pluggable Optics: What Is the Difference?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The main difference between Co-Packaged Optics and pluggable optics is the location of the optical engine: CPO places it close to the ASIC, while pluggable optics keeps the optical module at the system faceplate.<\/p>\n\n\n\n<figure class=\"wp-block-image\"><img decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/09\/co-packaged-optics-vs-pluggable.jpg\" alt=\"Comparison of Co-Packaged Optics and pluggable optics showing short versus long electrical paths\"\/><\/figure>\n\n\n\n<div class=\"table-wrap wp-block-table\">\n<table>\n<thead>\n<tr>\n<th>Item<\/th>\n<th>Pluggable Optics<\/th>\n<th>Co-Packaged Optics<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Optical engine location<\/td>\n<td>Front panel<\/td>\n<td>Close to ASIC<\/td>\n<\/tr>\n<tr>\n<td>High-speed electrical path<\/td>\n<td>Relatively long<\/td>\n<td>Very short<\/td>\n<\/tr>\n<tr>\n<td>PCB channel demand<\/td>\n<td>Higher<\/td>\n<td>Reduced near optical interface<\/td>\n<\/tr>\n<tr>\n<td>Electrical loss<\/td>\n<td>Higher at very high rates<\/td>\n<td>Lower<\/td>\n<\/tr>\n<tr>\n<td>Bandwidth density<\/td>\n<td>Limited by faceplate space<\/td>\n<td>Potentially much higher<\/td>\n<\/tr>\n<tr>\n<td>Module replacement<\/td>\n<td>Simple<\/td>\n<td>More complex<\/td>\n<\/tr>\n<tr>\n<td>Packaging<\/td>\n<td>Mature and modular<\/td>\n<td>Highly integrated<\/td>\n<\/tr>\n<tr>\n<td>Thermal design<\/td>\n<td>Module and ASIC more separated<\/td>\n<td>Optics and ASIC interact closely<\/td>\n<\/tr>\n<tr>\n<td>Deployment maturity<\/td>\n<td>Widely established<\/td>\n<td>Entering broader production<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n\n\n\n<p>Pluggable optics remains attractive because individual modules can be replaced or upgraded without disturbing the main switch package.<\/p>\n\n\n\n<p>CPO trades some of that modularity for a shorter electrical path. The trade becomes more attractive as SerDes speed, channel loss, power consumption, and faceplate density become harder to scale.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Co-Packaged_Optics_vs_NPO_vs_LPO_How_Do_They_Compare\"><\/span>Co-Packaged Optics vs NPO vs LPO: How Do They Compare?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>CPO, NPO, and LPO mainly differ in how close the optical engine sits to the ASIC and how much electrical processing remains between the ASIC and optics.<\/p>\n\n\n\n<div class=\"table-wrap wp-block-table\">\n<table>\n<thead>\n<tr>\n<th>Architecture<\/th>\n<th>Optical Location<\/th>\n<th>Electrical Reach<\/th>\n<th>Serviceability<\/th>\n<th>Integration<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Traditional pluggable<\/td>\n<td>Front panel<\/td>\n<td>Longest<\/td>\n<td>High<\/td>\n<td>Low<\/td>\n<\/tr>\n<tr>\n<td>LPO<\/td>\n<td>Front panel<\/td>\n<td>Long<\/td>\n<td>High<\/td>\n<td>Low<\/td>\n<\/tr>\n<tr>\n<td>NPO<\/td>\n<td>Near ASIC<\/td>\n<td>Short<\/td>\n<td>Moderate<\/td>\n<td>Medium<\/td>\n<\/tr>\n<tr>\n<td>CPO<\/td>\n<td>At or within ASIC package environment<\/td>\n<td>Shortest<\/td>\n<td>More difficult<\/td>\n<td>Highest<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n\n\n\n<p><strong>Linear Pluggable Optics (LPO)<\/strong> retains a front-panel optical module while simplifying the signal-processing chain to reduce DSP-related power.<\/p>\n\n\n\n<p><strong>Near-Packaged Optics (NPO)<\/strong> places the optical engine near the ASIC without integrating it as tightly into the package.<\/p>\n\n\n\n<p><strong>Co-Packaged Optics (CPO)<\/strong> moves optics closest to the ASIC and has the highest degree of integration.<\/p>\n\n\n\n<p>As the optical engine moves closer to the ASIC, electrical reach generally falls, but package complexity and service requirements increase.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"What_Are_the_Main_Benefits_of_Co-Packaged_Optics\"><\/span>What Are the Main Benefits of Co-Packaged Optics?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The main CPO benefits are lower electrical channel loss, lower I\/O power potential, greater bandwidth density, and better scalability at very high data rates.<\/p>\n\n\n\n<p>They result mainly from shortening the ASIC-to-optics electrical path:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Lower electrical loss:<\/strong> shorter high-speed connections introduce less attenuation.<\/li>\n\n\n\n<li><strong>Lower I\/O power potential:<\/strong> short channels can reduce the need for aggressive equalization, retimers, or additional signal conditioning.<\/li>\n\n\n\n<li><strong>Higher bandwidth density:<\/strong> optical bandwidth is less dependent on the number of pluggable modules that fit on the front panel.<\/li>\n\n\n\n<li><strong>Better bandwidth scaling:<\/strong> increasing ASIC bandwidth does not require every optical lane to traverse a long PCB channel.<\/li>\n\n\n\n<li><strong>Less demanding ASIC-to-optics board routing:<\/strong> much of this interface moves toward the package.<\/li>\n<\/ul>\n\n\n\n<p>These advantages become more valuable as per-lane data rate and total system bandwidth rise.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"What_Are_the_Main_Challenges_of_Co-Packaged_Optics\"><\/span>What Are the Main Challenges of Co-Packaged Optics?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The main CPO challenges are thermal management, optical alignment, package yield, testing, fiber attachment, laser delivery, serviceability, and standardization.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Thermal management:<\/strong> high-power ASICs create a difficult environment for nearby optical devices.<\/li>\n\n\n\n<li><strong>Optical alignment:<\/strong> fiber-to-photonic interfaces require precise positioning to maintain coupling efficiency.<\/li>\n\n\n\n<li><strong>Package yield:<\/strong> one defective electronic or optical component can affect the value of a complex multi-die package.<\/li>\n\n\n\n<li><strong>Testability:<\/strong> both electrical and optical functions need to be screened before and after integration.<\/li>\n\n\n\n<li><strong>Fiber attachment:<\/strong> fiber arrays require repeatable alignment and adequate mechanical reliability.<\/li>\n\n\n\n<li><strong>External laser delivery:<\/strong> optical power must reach the photonic engines with controlled loss.<\/li>\n\n\n\n<li><strong>Serviceability:<\/strong> integrated optical engines are more difficult to replace than front-panel transceivers.<\/li>\n\n\n\n<li><strong>Standardization:<\/strong> electrical, optical, laser, package, and management interfaces are still developing.<\/li>\n<\/ul>\n\n\n\n<p>Standardization is already progressing. OIF has published a 3.2 Tb\/s co-packaged module implementation agreement as well as external-laser implementation agreements for CPO systems.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Why_Is_Co-Packaged_Optics_Important_for_AI_Data_Centers\"><\/span>Why Is Co-Packaged Optics Important for AI Data Centers?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Co-Packaged Optics is important for AI data centers because large accelerator clusters require rapidly increasing network bandwidth while power and electrical-channel loss become harder to control.<\/p>\n\n\n\n<p>As AI clusters scale, several requirements rise together:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>GPU\/XPU-to-GPU\/XPU traffic<\/li>\n\n\n\n<li>switch capacity<\/li>\n\n\n\n<li>SerDes data rate<\/li>\n\n\n\n<li>bandwidth density<\/li>\n\n\n\n<li>network power consumption<\/li>\n<\/ul>\n\n\n\n<p>CPO reduces the board-level electrical distance between the switching silicon and optics before moving the traffic onto fiber.<\/p>\n\n\n\n<p>Commercial hardware now shows the scale involved. NVIDIA&#8217;s Spectrum-X Ethernet Photonics uses 200 Gb\/s SerDes, and its SN6800 platform reaches 409.6 Tb\/s total bandwidth. NVIDIA stated in May 2026 that Spectrum-X Ethernet Photonics CPO switches were in production as part of the Vera Rubin platform.<\/p>\n\n\n\n<p>This makes CPO especially relevant to AI scale-up fabrics, scale-out networks, high-radix Ethernet, and other accelerator-heavy infrastructure.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Where_Is_Co-Packaged_Optics_Used_Today\"><\/span>Where Is Co-Packaged Optics Used Today?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>CPO is already entering production in AI and hyperscale networking, while applications such as direct processor optical I\/O and broader disaggregated computing remain at earlier stages of adoption.<\/p>\n\n\n\n<figure class=\"wp-block-image\"><img decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/09\/co-packaged-optics-applications.jpg\" alt=\"Co-Packaged Optics applications in AI data centers, hyperscale cloud and HPC optical fabrics\"\/><\/figure>\n\n\n\n<p><strong>Current co-packaged optics applications include:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>AI data center networks:<\/strong> CPO connects very high-capacity switching silicon to optical fabrics used between accelerator systems.<\/li>\n\n\n\n<li><strong>Hyperscale cloud networks:<\/strong> cloud operators face similar bandwidth-density and electrical-reach constraints as switch capacity increases.<\/li>\n\n\n\n<li><strong>High-performance computing:<\/strong> large HPC systems require high-bandwidth communication between compute nodes.<\/li>\n\n\n\n<li><strong>High-capacity Ethernet switching:<\/strong> switches are one of the clearest early commercial applications of CPO.<\/li>\n\n\n\n<li><strong>Large routing platforms:<\/strong> high-throughput networking equipment can benefit when front-panel density and long electrical channels limit further scaling.<\/li>\n<\/ul>\n\n\n\n<p>Commercialization is no longer hypothetical. Broadcom announced its 102.4 Tb\/s Tomahawk 6\u2013Davisson CPO Ethernet switch in 2025 as its third-generation CPO platform, while NVIDIA reported production of Spectrum-X Ethernet Photonics systems in 2026.<\/p>\n\n\n\n<p><strong>Emerging applications include:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>processor-to-processor optical I\/O<\/li>\n\n\n\n<li>GPU and XPU optical interfaces<\/li>\n\n\n\n<li>chiplet-to-chiplet optical links<\/li>\n\n\n\n<li>disaggregated compute and memory systems<\/li>\n\n\n\n<li>future optical connections between separated compute resources<\/li>\n<\/ul>\n\n\n\n<p>These emerging uses extend the same principle beyond network switching: convert data to light closer to the device when conventional electrical interconnect becomes inefficient in bandwidth, reach, or power.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"How_Does_Advanced_Packaging_Support_Co-Packaged_Optics\"><\/span>How Does Advanced Packaging Support Co-Packaged Optics?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Advanced packaging supports CPO by placing electronic and photonic dies close enough to communicate over short, dense electrical connections while maintaining optical alignment and thermal control.<\/p>\n\n\n\n<figure class=\"wp-block-image\"><img decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/09\/co-packaged-optics-advanced-packaging.jpg\" alt=\"Exploded Co-Packaged Optics package showing ASIC, PIC, EIC, interposer, substrate, thermal interface and fiber array\"\/><\/figure>\n\n\n\n<p>A CPO assembly may combine:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>switch or compute ASICs<\/li>\n\n\n\n<li>PICs<\/li>\n\n\n\n<li>electronic driver and receiver ICs<\/li>\n\n\n\n<li>optical engines<\/li>\n\n\n\n<li>organic package substrates<\/li>\n\n\n\n<li>silicon or organic interposers<\/li>\n\n\n\n<li>redistribution structures<\/li>\n\n\n\n<li>micro-bumps or other fine-pitch connections<\/li>\n\n\n\n<li>fiber coupling interfaces<\/li>\n\n\n\n<li>thermal interfaces<\/li>\n<\/ul>\n\n\n\n<p>The packaging architecture must solve three problems at once:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>keep high-speed electrical interconnects short;<\/li>\n\n\n\n<li>maintain accurate optical coupling;<\/li>\n\n\n\n<li>provide an effective thermal path away from high-power silicon.<\/li>\n<\/ul>\n\n\n\n<p>Depending on the platform, this may involve 2.5D integration, interposers, chiplets, fine-pitch redistribution, micro-bumps, or hybrid bonding.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"How_Does_Co-Packaged_Optics_Change_PCB_and_System_Design\"><\/span>How Does Co-Packaged Optics Change PCB and System Design?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>CPO changes PCB design by moving some of the fastest ASIC-to-optics routing into the package while increasing the importance of board-level power delivery, dense breakout routing, thermal management, and mechanical integration.<\/p>\n\n\n\n<p>The PCB still carries several critical responsibilities:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Power delivery:<\/strong> high-power ASICs and supporting electronics require low-impedance power distribution.<\/li>\n\n\n\n<li><strong>Remaining high-speed links:<\/strong> PCIe, memory, clocks, control, management, and other interfaces still need controlled signal integrity.<\/li>\n\n\n\n<li><strong>BGA escape routing:<\/strong> large advanced packages can require dense multilayer breakout.<\/li>\n\n\n\n<li><strong>Fiber-related mechanical layout:<\/strong> fiber exits, bend radius, connectors, cold plates, and heat sinks affect component placement.<\/li>\n\n\n\n<li><strong>Thermal integration:<\/strong> package position, PCB copper, airflow, and cooling hardware influence the complete thermal path.<\/li>\n<\/ul>\n\n\n\n<div class=\"note\"><strong>CPO does not eliminate the PCB. It changes which PCB functions become most demanding.<\/strong><\/div>\n\n\n\n<p>Long ASIC-to-optics board traces can be reduced, while power, remaining high-speed connections, cooling, mechanical clearances, and package breakout remain board-level design concerns.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"What_PCB_Requirements_Matter_in_Co-Packaged_Optics_Systems\"><\/span>What PCB Requirements Matter in Co-Packaged Optics Systems?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>CPO systems typically need PCBs with controlled impedance, suitable low-loss materials, dense multilayer routing, robust power distribution, accurate dimensions, and support for large advanced packages.<\/p>\n\n\n\n<figure class=\"wp-block-image\"><img decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/09\/co-packaged-optics-pcb-requirements.jpg\" alt=\"PCB requirements for Co-Packaged Optics including controlled impedance, HDI, BGA breakout, power layers, thermal vias and Rogers FR-4 hybrid stackup\"\/><\/figure>\n\n\n\n<p>Typical requirements include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Low-loss laminate:<\/strong> for high-speed electrical links that remain on the board.<\/li>\n\n\n\n<li><strong>Controlled impedance:<\/strong> for SerDes, PCIe, clocks, and other high-speed channels.<\/li>\n\n\n\n<li><a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/hdi-pcb\/\"><strong>HDI structures:<\/strong><\/a> microvias and sequential lamination may be needed for dense package breakout.<\/li>\n\n\n\n<li><strong>High layer count:<\/strong> signal, power, and ground routing can require complex stackups.<\/li>\n\n\n\n<li><strong>Power integrity:<\/strong> high-current ASICs need suitable planes, copper distribution, and via capacity.<\/li>\n\n\n\n<li><strong>Fine-pitch BGA routing:<\/strong> large advanced packages can require tight trace and via geometry.<\/li>\n\n\n\n<li><strong>Dimensional control:<\/strong> important around package, cooling, fiber, and connector interfaces.<\/li>\n\n\n\n<li><strong>Thermal structures:<\/strong> thermal vias, copper planes, copper inlays, or other heat-spreading features may be required.<\/li>\n\n\n\n<li><strong>Backdrilling:<\/strong> through-hole via stubs may need removal on sensitive high-speed channels.<\/li>\n\n\n\n<li><strong>Surface finish:<\/strong> the finish should match the assembly and reliability requirements.<\/li>\n<\/ul>\n\n\n\n<p>The PCB specification should come from the actual channel, package, power, and mechanical requirements rather than from a generic \u201cCPO PCB\u201d stackup.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"What_Should_You_Consider_When_Manufacturing_PCBs_for_CPO_Hardware\"><\/span>What Should You Consider When Manufacturing PCBs for CPO Hardware?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>When manufacturing PCBs for CPO hardware, the main concerns are material selection, impedance control, stackup repeatability, HDI capability, power delivery, dimensional accuracy, thermal requirements, and prototype-to-production consistency.<\/p>\n\n\n\n<p>A useful RFQ package should include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>PCB stackup<\/li>\n\n\n\n<li>laminate grade or loss target<\/li>\n\n\n\n<li>dielectric thickness<\/li>\n\n\n\n<li>finished board thickness<\/li>\n\n\n\n<li>copper weight<\/li>\n\n\n\n<li>controlled-impedance values and tolerance<\/li>\n\n\n\n<li>minimum trace and spacing<\/li>\n\n\n\n<li>via and microvia structure<\/li>\n\n\n\n<li>backdrill requirements<\/li>\n\n\n\n<li>BGA pitch<\/li>\n\n\n\n<li>dimensional tolerances<\/li>\n\n\n\n<li>thermal requirements<\/li>\n\n\n\n<li>surface finish<\/li>\n\n\n\n<li>assembly drawings<\/li>\n\n\n\n<li>prototype and production quantity<\/li>\n<\/ul>\n\n\n\n<p>For high-speed channels, include the operating data rate and insertion-loss target when available.<\/p>\n\n\n\n<p>At EBest Circuit, we bring more than 20 years of PCB and PCBA manufacturing experience to CPO-related hardware, with production capabilities in both China and Vietnam. We support low-loss multilayer PCBs, HDI, controlled impedance, fine-pitch BGA designs, advanced thermal structures, and complex stackups for high-speed systems where signal integrity, power delivery, and manufacturing consistency all matter.<\/p>\n\n\n\n<p>Our advantage is not limited to board fabrication. For CPO and AI-related high-speed hardware, we have experience with Rogers materials such as RO4350B, RO4003C, RO3003, RO3010, and RT\/duroid 5880, as well as Rogers\/FR-4 hybrid multilayer constructions. We can combine material selection, controlled-impedance stackups, HDI routing, fine-pitch BGA breakout, thermal design, and PCBA in one manufacturing flow, supporting projects from prototype builds through volume production.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"FAQs_About_Co-Packaged_Optics\"><\/span>FAQs About Co-Packaged Optics<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p><strong>1. Is co-packaged optics the same as silicon photonics?<\/strong><\/p>\n\n\n\n<p>No. Silicon photonics is a technology used to create integrated optical components, while CPO is a system and packaging architecture that places optical engines close to high-performance electronic chips. Silicon photonics is one of the technologies that can enable CPO.<\/p>\n\n\n\n<p><strong>2. Will co-packaged optics replace pluggable optics?<\/strong><\/p>\n\n\n\n<p>Not completely. Pluggable optics offers strong serviceability, an established ecosystem, and simple replacement. CPO is more attractive where bandwidth density, electrical reach, and power become limiting factors. Both architectures are likely to coexist across different applications.<\/p>\n\n\n\n<p><strong>3. What is the difference between CPO and optical I\/O?<\/strong><\/p>\n\n\n\n<p>CPO is a specific integration approach, while optical I\/O is a broader concept. CPO commonly refers to optics integrated around switch or compute packages to replace longer electrical links. Optical I\/O can also include direct optical interfaces on processors, accelerators, chiplets, and other semiconductor devices.<\/p>\n\n\n\n<p><strong>4. Why does CPO often use external lasers?<\/strong><\/p>\n\n\n\n<p>CPO often uses external lasers to separate the laser source from the hot ASIC environment. This can improve thermal conditions and simplify laser replacement. The optical engine receives laser light through fiber and uses that light for modulation.<\/p>\n\n\n\n<p><strong>5. Is co-packaged optics only used in AI data centers?<\/strong><\/p>\n\n\n\n<p>No. AI infrastructure is currently a major driver, but CPO can also support hyperscale cloud networks, HPC systems, high-capacity routers, telecom equipment, disaggregated computing, and emerging processor optical I\/O.<\/p>\n\n\n\n<p><strong>6. What are the biggest barriers to CPO adoption?<\/strong><\/p>\n\n\n\n<p>The biggest barriers are manufacturing and integration complexity. Key issues include thermal management, packaging yield, optical alignment, fiber attach, manufacturing cost, test complexity, serviceability, laser architecture, and standardization.<\/p>\n\n\n\n<p><strong>7. Does CPO still require <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/08\/high-speed-pcb-design\/\">high-speed PCBs<\/a>?<\/strong><\/p>\n\n\n\n<p>Yes. CPO shortens some of the highest-speed electrical paths, but the system still contains board-level high-speed links, power distribution, control interfaces, BGA routing, connectors, and other circuitry. PCB design remains an important part of the platform.<\/p>\n\n\n\n<p><strong>8. Which companies are developing co-packaged optics?<\/strong><\/p>\n\n\n\n<p>Leading co-packaged optics companies include Broadcom, NVIDIA, Marvell, Intel, Cisco, and Ayar Labs. The broader ecosystem also includes foundries, packaging companies, laser suppliers, fiber manufacturers, and optical-component suppliers working on different parts of the CPO platform.<\/p>\n\n\n\n<div class=\"cta\">If you are developing high-speed networking, AI hardware, optical I\/O, or other CPO-related electronics, send your <strong>Gerber files, stackup, BOM, impedance requirements, and assembly drawings to <a href=\"mailto:sales@bestpcbs.com\">sales@bestpcbs.com<\/a><\/strong>. We can review your PCB manufacturability, material selection, HDI structures, controlled impedance, thermal requirements, and PCBA needs before production.<\/div>\n\n\n\n<section class=\"sources\" aria-label=\"References\"><strong>Selected references<\/strong>\n<ul>\n<li><a href=\"https:\/\/www.oiforum.com\/technical-work\/implementation-agreements-ias\/\" target=\"_blank\" rel=\"nofollow noopener\">OIF Implementation Agreements<\/a><\/li>\n<li><a href=\"https:\/\/developer.nvidia.com\/blog\/scaling-power-efficient-ai-factories-with-nvidia-spectrum-x-ethernet-photonics\/\" target=\"_blank\" rel=\"nofollow noopener\">NVIDIA Spectrum-X Ethernet Photonics<\/a><\/li>\n<li><a href=\"https:\/\/investors.broadcom.com\/news-releases\/news-release-details\/broadcom-announces-tomahawkr-6-davisson-industrys-first-1024\" target=\"_blank\" rel=\"nofollow noopener\">Broadcom Tomahawk 6\u2013Davisson CPO announcement<\/a><\/li>\n<\/ul>\n<\/section>\n","protected":false},"excerpt":{"rendered":"<p>Learn how Co-Packaged Optics (CPO) works, where it is used, its key challenges, and the PCB requirements behind high-speed AI data-center hardware.<\/p>\n","protected":false},"author":623,"featured_media":35629,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_uf_show_specific_survey":0,"_uf_disable_surveys":false,"footnotes":""},"categories":[7636,175,5789,16],"tags":[8292,8293,8295,8296,8294],"class_list":["post-35635","post","type-post","status-publish","format-standard","hentry","category-ai-pcb","category-best-pcb","category-pcb-design","category-pcb-technology","tag-co-packaged-optics-tag","tag-co-packaged-optics-cpo","tag-co-packaged-optics-applications","tag-co-packaged-optics-companies","tag-what-is-co-packaged-optics"],"acf":[],"aioseo_notices":[],"aioseo_head":"\n\t\t<!-- All in One SEO 4.9.10 - aioseo.com -->\n\t<meta name=\"description\" content=\"Learn how Co-Packaged Optics (CPO) works, where it is used, its key challenges, and the PCB requirements behind high-speed AI data-center hardware.\" \/>\n\t<meta name=\"robots\" content=\"max-image-preview:large\" \/>\n\t<meta name=\"author\" content=\"Love PCB\"\/>\n\t<link rel=\"canonical\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/co-packaged-optics\/\" \/>\n\t<meta name=\"generator\" content=\"All in One SEO (AIOSEO) 4.9.10\" \/>\n\t\t<meta property=\"og:locale\" content=\"en_US\" \/>\n\t\t<meta property=\"og:site_name\" content=\"PCB &amp; MCPCB - EBest PCB - More Technical Details &amp; News on PCB, MCPCB &amp; Ceramic PCB from EBest PCB\" \/>\n\t\t<meta property=\"og:type\" content=\"article\" \/>\n\t\t<meta property=\"og:title\" content=\"Co-Packaged Optics (CPO): Applications and PCB Design\" \/>\n\t\t<meta property=\"og:description\" content=\"Learn how Co-Packaged Optics (CPO) works, where it is used, its key challenges, and the PCB requirements behind high-speed AI data-center hardware.\" \/>\n\t\t<meta property=\"og:url\" content=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/co-packaged-optics\/\" \/>\n\t\t<meta property=\"og:image\" content=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2025\/08\/logo.png\" \/>\n\t\t<meta property=\"og:image:secure_url\" content=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2025\/08\/logo.png\" \/>\n\t\t<meta property=\"article:published_time\" content=\"2026-09-10T00:47:26+00:00\" \/>\n\t\t<meta property=\"article:modified_time\" content=\"2026-09-10T00:49:21+00:00\" \/>\n\t\t<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/Bestpcbs1\" \/>\n\t\t<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n\t\t<meta name=\"twitter:site\" content=\"@bestpcbs\" \/>\n\t\t<meta name=\"twitter:title\" content=\"Co-Packaged Optics (CPO): Applications and PCB Design\" \/>\n\t\t<meta name=\"twitter:description\" content=\"Learn how Co-Packaged Optics (CPO) works, where it is used, its key challenges, and the PCB requirements behind high-speed AI data-center hardware.\" \/>\n\t\t<meta name=\"twitter:creator\" content=\"@bestpcbs\" \/>\n\t\t<meta name=\"twitter:image\" content=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2016\/02\/logo.gif\" \/>\n\t\t<script type=\"application\/ld+json\" class=\"aioseo-schema\">\n\t\t\t{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"BlogPosting\",\"@id\":\"https:\\\/\\\/www.bestpcbs.com\\\/blog\\\/2026\\\/09\\\/co-packaged-optics\\\/#blogposting\",\"name\":\"Co-Packaged Optics (CPO): Applications and PCB Design\",\"headline\":\"What Is Co-Packaged Optics (CPO)? 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