{"id":35359,"date":"2026-09-05T15:29:04","date_gmt":"2026-09-05T07:29:04","guid":{"rendered":"https:\/\/www.bestpcbs.com\/blog\/?p=35359"},"modified":"2026-09-05T15:29:56","modified_gmt":"2026-09-05T07:29:56","slug":"stacked-vs-staggered-microvias-reliability-hdi-dfm","status":"publish","type":"post","link":"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/stacked-vs-staggered-microvias-reliability-hdi-dfm\/","title":{"rendered":"Stacked vs Staggered Microvias: Reliability and HDI DFM"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_85 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/stacked-vs-staggered-microvias-reliability-hdi-dfm\/#Stacked_vs_Staggered_Microvias_at_a_Glance\" >Stacked vs Staggered Microvias at a Glance<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/stacked-vs-staggered-microvias-reliability-hdi-dfm\/#How_Stacked_and_Staggered_Microvia_Structures_Are_Built\" >How Stacked and Staggered Microvia Structures Are Built<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/stacked-vs-staggered-microvias-reliability-hdi-dfm\/#Why_Stacked_Microvias_Save_Routing_Area\" >Why Stacked Microvias Save Routing Area<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/stacked-vs-staggered-microvias-reliability-hdi-dfm\/#Why_Staggered_Microvias_Can_Simplify_Reliability_Control\" >Why Staggered Microvias Can Simplify Reliability Control<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/stacked-vs-staggered-microvias-reliability-hdi-dfm\/#Reliability_Risks_That_Need_Attention_in_Stacked_Structures\" >Reliability Risks That Need Attention in Stacked Structures<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/stacked-vs-staggered-microvias-reliability-hdi-dfm\/#Capture_Pads_Alignment_and_Registration\" >Capture Pads, Alignment, and Registration<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/stacked-vs-staggered-microvias-reliability-hdi-dfm\/#Why_Copper_Filling_and_Planarization_Matter\" >Why Copper Filling and Planarization Matter<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/stacked-vs-staggered-microvias-reliability-hdi-dfm\/#Signal_Power_and_Thermal_Considerations\" >Signal, Power, and Thermal Considerations<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/stacked-vs-staggered-microvias-reliability-hdi-dfm\/#Cost_and_Lead-Time_Drivers\" >Cost and Lead-Time Drivers<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/stacked-vs-staggered-microvias-reliability-hdi-dfm\/#Inspection_and_Qualification_Evidence_to_Request\" >Inspection and Qualification Evidence to Request<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-11\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/stacked-vs-staggered-microvias-reliability-hdi-dfm\/#Decision_Checklist_Stack_Stagger_or_Redesign_the_Transition\" >Decision Checklist: Stack, Stagger, or Redesign the Transition<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-12\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/stacked-vs-staggered-microvias-reliability-hdi-dfm\/#What_to_Send_for_EBest_Circuit_HDI_DFM_and_Quotation\" >What to Send for EBest Circuit HDI DFM and Quotation<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-13\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/stacked-vs-staggered-microvias-reliability-hdi-dfm\/#Stacked_vs_Staggered_Microvia_FAQ\" >Stacked vs Staggered Microvia FAQ<\/a><\/li><\/ul><\/nav><\/div>\n<div class=\"yzp-no-index\"><\/div><style>\n#post-35359 h1._title, #post-35359 .entry h2, #post-35359 .entry h3 { word-break: normal; overflow-wrap: anywhere; }\n.ebest-inline-cta{margin:2em 0;padding:24px;border-radius:14px;background:#eaf5fb;border-left:5px solid #1478a6}.ebest-inline-cta__title{margin:0 0 8px;font-size:1.25rem;font-weight:700;color:#17394a}.ebest-inline-cta__actions{display:flex;flex-wrap:wrap;gap:12px;margin-top:14px}.ebest-inline-cta__button{flex:1 1 240px;min-width:0;max-width:100%;box-sizing:border-box;padding:12px 16px;border-radius:7px;background:#1478a6;color:#fff!important;text-align:center;text-decoration:none;font-weight:700}.ebest-final-cta{margin:2em 0 0;padding:26px;border-radius:14px;background:#123a4b;color:#fff}.ebest-final-cta a{color:#fff;font-weight:700}\n<\/style>\n<figure style=\"max-width:100%;margin:1.5em 0;overflow-x:hidden\"><img fetchpriority=\"high\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/09\/stacked-vs-staggered-microvia-hero.jpg\" alt=\"HDI PCB and cross-section comparing stacked and staggered microvia structures\" width=\"1672\" height=\"941\" loading=\"eager\" decoding=\"async\" style=\"display:block;width:100%;max-width:100%;height:auto;margin:0 auto\"><figcaption>Stacked and staggered microvias solve different HDI routing problems and create different fabrication controls.<\/figcaption><\/figure>\n<p><strong>Stacked microvias align vertically through successive build-up layers, while staggered microvias step sideways from one layer transition to the next.<\/strong> Stacking preserves routing area and can support dense BGA escape, but it concentrates manufacturing interfaces in one column. Staggering needs more lateral space, yet it can simplify filling and reduce dependence on a long, perfectly aligned vertical structure.<\/p>\n<p>The choice is not \u201cadvanced versus basic.\u201d It should be made from the actual layer transitions, package pitch, routing channels, dielectric thickness, via geometry, assembly profile and the fabricator&#8217;s qualified HDI process.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Stacked_vs_Staggered_Microvias_at_a_Glance\"><\/span>Stacked vs Staggered Microvias at a Glance<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<div style=\"overflow-x:auto\">\n<table>\n<tbody>\n<tr>\n<td><strong>Decision factor<\/strong><\/td>\n<td><strong>Stacked microvias<\/strong><\/td>\n<td><strong>Staggered microvias<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Routing area<\/td>\n<td>Small vertical footprint<\/td>\n<td>Needs lateral offset and landing space<\/td>\n<\/tr>\n<tr>\n<td>Build dependency<\/td>\n<td>Relies on aligned, filled underlying structures<\/td>\n<td>Each transition lands on an offset capture pad<\/td>\n<\/tr>\n<tr>\n<td>Process sensitivity<\/td>\n<td>Higher sensitivity to fill, planarity and registration<\/td>\n<td>More layout area but fewer vertical interfaces in one column<\/td>\n<\/tr>\n<tr>\n<td>Typical reason to choose<\/td>\n<td>Very dense escape or constrained routing corridor<\/td>\n<td>Available area and preference for a less concentrated structure<\/td>\n<\/tr>\n<tr>\n<td>DFM evidence<\/td>\n<td>Stackup, fill plan, cross-sections and qualification data<\/td>\n<td>Offset geometry, capture pads, registration and layer-clearance review<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n<p>This comparison is directional. Final geometry and permitted layer combinations must come from the selected manufacturer&#8217;s capability review, not from a universal online rule.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"How_Stacked_and_Staggered_Microvia_Structures_Are_Built\"><\/span>How Stacked and Staggered Microvia Structures Are Built<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Both structures are created through sequential build-up: form one dielectric layer, laser-drill the microvia, metallize it, then repeat for the next layer transition.<\/strong> A stacked design places the next microvia directly over the filled and planarized structure below. A staggered design shifts the next via so it lands on a separate capture pad.<\/p>\n<p>That sequence makes stackup communication essential. A drawing that only says \u201cblind via\u201d does not tell CAM which layers connect, whether vias stack, whether fill is required, or which structures carry critical signals.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Why_Stacked_Microvias_Save_Routing_Area\"><\/span>Why Stacked Microvias Save Routing Area<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>A vertical stack uses less planar space than an offset chain.<\/strong> This can preserve escape channels under fine-pitch BGAs, shorten transitions and keep nearby routing available for power, ground or high-speed nets.<\/p>\n<p>The density benefit is real only if the structure can be manufactured reliably. Adding more transitions to a column increases dependency on each laser-drill, metallization, fill, planarization and registration step. Designers should not stack automatically where a staggered route, buried via or different fanout could meet the same electrical task.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Why_Staggered_Microvias_Can_Simplify_Reliability_Control\"><\/span>Why Staggered Microvias Can Simplify Reliability Control<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Staggering distributes adjacent microvias laterally instead of building one continuous vertical column.<\/strong> When the package and routing area allow the offsets, it can reduce reliance on the surface of a filled microvia as the foundation for the next laser via.<\/p>\n<p>The tradeoff is space. Every offset needs a valid capture pad, trace connection and clearance from adjacent features. A loose stagger can also make the route longer or consume a channel needed by another net.<\/p>\n<div class=\"ebest-inline-cta\">\n<p class=\"ebest-inline-cta__title\">Unsure whether your HDI transition should stack or stagger?<\/p>\n<p>Send the BGA map, stackup, via table, critical nets and available escape geometry. EBest Circuit can review the structure before artwork release.<\/p>\n<div class=\"ebest-inline-cta__actions\"><a class=\"ebest-inline-cta__button\" href=\"https:\/\/www.bestpcbs.com\/pcb-quote\/\">Request an HDI DFM Review<\/a><\/div>\n<\/div>\n<h2><span class=\"ez-toc-section\" id=\"Reliability_Risks_That_Need_Attention_in_Stacked_Structures\"><\/span>Reliability Risks That Need Attention in Stacked Structures<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>The most important risk is an imperfect interface inside a structure that depends on every layer transition.<\/strong> Incomplete copper fill, voids, depressed fill, weak interconnection, misregistration or material stress can accumulate through the column.<\/p>\n<ul>\n<li>A void or fill depression can affect the landing surface for the next microvia.<\/li>\n<li>Registration error can reduce the effective capture area at an interface.<\/li>\n<li>Repeated thermal excursions can stress copper-to-copper and copper-to-dielectric interfaces.<\/li>\n<li>Material expansion behavior influences strain during reflow and service.<\/li>\n<li>A structure that passes continuity may still require cross-sectional or reliability evidence.<\/li>\n<\/ul>\n<p>Reliability cannot be inferred from the word \u201cfilled.\u201d The specification should identify the stack, materials, acceptance criteria and required qualification evidence.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Capture_Pads_Alignment_and_Registration\"><\/span>Capture Pads, Alignment, and Registration<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Capture-pad geometry must tolerate the combined registration budget of imaging, lamination and laser drilling.<\/strong> A nominally centered CAD feature can lose effective land if process shifts align in the same direction.<\/p>\n<p>For stacked vias, alignment must support the interface between successive features. For staggered vias, the offset must leave enough pad and connecting copper without violating spacing or blocking escape routes. Review finished geometry rather than judging only the drill file.<\/p>\n<p>Related design foundations are covered in our <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-annular-ring\/\">PCB annular ring guide<\/a> and <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/08\/microvia-aspect-ratio\/\">microvia aspect-ratio guide<\/a>.<\/p>\n<figure style=\"max-width:100%;margin:1.5em 0;overflow-x:hidden\"><img src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/09\/microvia-structure-comparison.jpg\" alt=\"Cross-sectional comparison of vertical stacked microvias and offset staggered microvias\" width=\"1672\" height=\"941\" loading=\"lazy\" decoding=\"async\" style=\"display:block;width:100%;max-width:100%;height:auto;margin:0 auto\"><figcaption>A stacked column depends on aligned filled interfaces; a staggered chain trades lateral area for separated layer transitions.<\/figcaption><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"Why_Copper_Filling_and_Planarization_Matter\"><\/span>Why Copper Filling and Planarization Matter<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>A microvia that supports another microvia generally needs a controlled filled and planarized surface.<\/strong> The next build-up layer must start from a stable landing condition. Fill voids, overfill, underfill or an uneven surface can affect imaging, lamination and the next laser-drilled feature.<\/p>\n<p>Specify the required structure and acceptance result, then let the fabricator propose the qualified fill route. Do not substitute generic material names or assumed plating values for process evidence. Via-in-pad applications add assembly-flatness and solder-control concerns; see the <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/via-in-pad-plated-over\/\">VIPPO design and inspection guide<\/a>.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Signal_Power_and_Thermal_Considerations\"><\/span>Signal, Power, and Thermal Considerations<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Geometry selection must serve the net, not only fabrication convenience.<\/strong> A compact stacked transition may reduce routing detour, but the complete return path, reference-plane change, anti-pad and nearby stitching strategy still determine electrical behavior.<\/p>\n<p>For power paths, review current distribution and copper connection at every layer. Do not describe a microvia stack as a thermal solution without checking the complete heat path. Multiple distributed structures may behave differently from one concentrated column.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Cost_and_Lead-Time_Drivers\"><\/span>Cost and Lead-Time Drivers<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Cost follows sequential build complexity, yield exposure, fill requirements, registration demands, inspection and qualification\u2014not the via name alone.<\/strong> A dense stacked design may require more controlled cycles and evidence, while staggering may require a larger breakout region or another routing layer.<\/p>\n<p>Ask for alternatives during DFM. A small fanout change, adjusted layer transition or mixed structure can reduce risk without changing the product function. Compare proposals using the same stackup and acceptance requirements.<\/p>\n<div class=\"ebest-inline-cta\">\n<p class=\"ebest-inline-cta__title\">Need a manufacturable microvia cost comparison?<\/p>\n<p>Provide the current and acceptable alternative stackups, quantities, material needs, BGA pitch and inspection level. We can compare the real process impact.<\/p>\n<div class=\"ebest-inline-cta__actions\"><a class=\"ebest-inline-cta__button\" href=\"https:\/\/www.bestpcbs.com\/pcb-quote\/\">Send the HDI Stackup<\/a><\/div>\n<\/div>\n<h2><span class=\"ez-toc-section\" id=\"Inspection_and_Qualification_Evidence_to_Request\"><\/span>Inspection and Qualification Evidence to Request<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Use evidence that represents the actual microvia structure and production process.<\/strong> Useful controls can include coupon design, cross-sections, plating\/fill review, registration checks, electrical test and agreed thermal-stress or reliability qualification.<\/p>\n<p>The inspection plan should identify which stack is sampled, where coupons are placed, how interfaces are judged and what happens after a nonconformance. A generic statement that the board is electrically tested does not replace structural evidence.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Decision_Checklist_Stack_Stagger_or_Redesign_the_Transition\"><\/span>Decision Checklist: Stack, Stagger, or Redesign the Transition<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<ol>\n<li>Map every required layer transition from the actual net and BGA escape.<\/li>\n<li>Confirm how much lateral routing area is available.<\/li>\n<li>Identify which structures must align vertically and why.<\/li>\n<li>Review microvia geometry against each dielectric layer.<\/li>\n<li>Confirm capture pads, clearances, fill and planarization.<\/li>\n<li>Ask for the fabricator&#8217;s qualified structure and inspection evidence.<\/li>\n<li>Compare a staggered or mixed alternative before locking a tall stack.<\/li>\n<li>Freeze the approved via table, stackup and deviation process.<\/li>\n<\/ol>\n<h2><span class=\"ez-toc-section\" id=\"What_to_Send_for_EBest_Circuit_HDI_DFM_and_Quotation\"><\/span>What to Send for EBest Circuit HDI DFM and Quotation<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>A useful RFQ connects design files to the exact microvia structure.<\/strong> Send Gerber or ODB++, drill\/via data, fabrication drawing, stackup, material requirements, BGA package information, critical nets, controlled-impedance targets, quantities, assembly needs, inspection requirements and target delivery.<\/p>\n<p>EBest Circuit can review whether the proposed stack, stagger or mixed strategy is clear and suitable for quotation, flag missing information and return project-specific questions. Any dimensional or process capability must be confirmed against the current build and approved factory route.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Stacked_vs_Staggered_Microvia_FAQ\"><\/span>Stacked vs Staggered Microvia FAQ<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<h3>What is the main difference between stacked and staggered microvias?<\/h3>\n<p>Stacked microvias align vertically; staggered microvias shift laterally between successive layer transitions.<\/p>\n<h3>Are staggered microvias always more reliable?<\/h3>\n<p>No. They can avoid a continuous vertical interface column, but reliability still depends on geometry, materials, process control and the actual design.<\/p>\n<h3>Why use stacked microvias?<\/h3>\n<p>They preserve routing area and can enable dense vertical transitions where the BGA escape or board outline leaves little lateral space.<\/p>\n<h3>Do stacked microvias need copper filling?<\/h3>\n<p>A microvia used as the landing foundation for another typically needs a qualified fill and planarization process. Confirm the exact structure with the fabricator.<\/p>\n<h3>How many microvias can be stacked?<\/h3>\n<p>There is no responsible universal answer. The permitted structure depends on the selected manufacturer&#8217;s qualified process, materials, dimensions and reliability requirements.<\/p>\n<h3>What is a microvia capture pad?<\/h3>\n<p>It is the copper land where the laser-drilled microvia terminates and connects to the target layer.<\/p>\n<h3>Can stacked and staggered microvias be mixed?<\/h3>\n<p>Yes, a board may use different structures where density and risk differ, provided the via table and stackup define them clearly.<\/p>\n<h3>Does electrical test prove a microvia stack is structurally reliable?<\/h3>\n<p>Electrical test confirms connectivity at test time; structural and reliability evidence may still be required for critical builds.<\/p>\n<h3>What data prevents microvia quotation errors?<\/h3>\n<p>Provide layer-pair definitions, stackup, hole\/pad data, fill needs, quantities, materials, inspection criteria and any approved alternatives.<\/p>\n<h3>When should the fabricator review the microvia strategy?<\/h3>\n<p>Before layout constraints are frozen, and again before production release after the complete stackup and files are available.<\/p>\n<div class=\"ebest-final-cta\">\n<p><strong>Validate the HDI via structure before it becomes a yield problem.<\/strong><\/p>\n<p>Send your Gerber\/ODB++, drill data, stackup, BGA map, materials, quantities and target delivery.<\/p>\n<div class=\"ebest-inline-cta__actions\"><a class=\"ebest-inline-cta__button\" href=\"mailto:sales@bestpcbs.com\">Email the Engineering Team<\/a><a class=\"ebest-inline-cta__button\" href=\"https:\/\/www.bestpcbs.com\/pcb-quote\/\">Request an HDI PCB Quote<\/a><\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"<p>Compare stacked vs staggered microvias for HDI PCBs, including routing density, reliability, copper filling, capture pads, inspection, cost and RFQ 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