{"id":35053,"date":"2026-09-03T09:28:03","date_gmt":"2026-09-03T01:28:03","guid":{"rendered":"https:\/\/www.bestpcbs.com\/blog\/?p=35053"},"modified":"2026-09-03T09:28:18","modified_gmt":"2026-09-03T01:28:18","slug":"sic-packages","status":"publish","type":"post","link":"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/sic-packages\/","title":{"rendered":"SiC Packages: How Package Choice Changes PCB Design"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_85 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/sic-packages\/#What_Are_SiC_Packages\" >What Are SiC Packages?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/sic-packages\/#Why_Does_SiC_Package_Choice_Matter\" >Why Does SiC Package Choice Matter?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/sic-packages\/#Which_SiC_Package_Types_Are_Used_in_Power_Electronics\" >Which SiC Package Types Are Used in Power Electronics?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/sic-packages\/#SiC_MOSFET_Packages\" >SiC MOSFET Packages<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/sic-packages\/#How_Do_SiC_Power_Modules_Differ_from_Discrete_Packages\" >How Do SiC Power Modules Differ from Discrete Packages?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/sic-packages\/#What_Does_SiC_Power_Module_Packaging_Need_from_the_PCB\" >What Does SiC Power Module Packaging Need from the PCB?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/sic-packages\/#How_Does_a_Kelvin_Source_Change_the_PCB_Layout\" >How Does a Kelvin Source Change the PCB Layout?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/sic-packages\/#How_Should_the_Commutation_and_Gate_Loops_Be_Routed\" >How Should the Commutation and Gate Loops Be Routed?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/sic-packages\/#How_Do_Top-Side_and_Bottom-Side_Cooling_Differ\" >How Do Top-Side and Bottom-Side Cooling Differ?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/sic-packages\/#What_PCB_and_Assembly_Details_Should_Be_Checked\" >What PCB and Assembly Details Should Be Checked?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-11\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/sic-packages\/#How_Should_SiC_Package_Assembly_Be_Inspected\" >How Should SiC Package Assembly Be Inspected?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-12\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/sic-packages\/#Which_SiC_Package_Fits_the_Application\" >Which SiC Package Fits the Application?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-13\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/sic-packages\/#FAQ_About_SiC_Packages\" >FAQ About SiC Packages<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-14\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/sic-packages\/#How_Can_EBest_Circuit_Support_Your_SiC_Power_PCB\" >How Can EBest Circuit Support Your SiC Power PCB?<\/a><\/li><\/ul><\/nav><\/div>\n<div class=\"yzp-no-index\"><\/div><p><a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/sic-packages\/\">SiC packages<\/a> do more than protect a silicon-carbide die. The selected package establishes the electrical terminals, internal interconnects, thermal path, mounting method, insulation features, and physical interface to the PCB or bus structure. Those details directly affect switching overshoot, EMI, heat removal, board area, assembly, and inspection.<\/p>\n<p>This guide focuses on power-semiconductor packaging for SiC MOSFETs, Schottky diodes, and power modules. It explains how to compare common package families and translate the device choice into PCB, PCBA, cooling, and mechanical requirements.<\/p>\n<div style=\"width: 100%; max-width: 600px; margin: 24px auto; text-align: center;\"><img loading=\"lazy\" decoding=\"async\" style=\"display: block; width: 100%; max-width: 600px; max-height: 400px; height: auto; object-fit: contain; border-radius: 8px;\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/09\/sic-packages-hero.jpg\" alt=\"SiC Packages including discrete devices, a power module, and a power PCB\" width=\"600\" height=\"400\" data-first-enter-image=\"true\" \/><\/div>\n<h2><span class=\"ez-toc-section\" id=\"What_Are_SiC_Packages\"><\/span>What Are SiC Packages?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>A SiC package is the mechanical, electrical, and thermal structure that connects a silicon-carbide power die to the rest of the system. It may contain one device, several parallel dies, a half bridge, a three-phase bridge, temperature sensing, or other integrated functions.<\/p>\n<p>The package is not the same as the semiconductor technology. Two SiC MOSFETs with similar voltage and on-resistance ratings can behave differently in the same converter because their lead arrangement, Kelvin connection, internal inductance, exposed thermal surface, insulation, and recommended layout are different.<\/p>\n<p>Before creating a footprint, use the full manufacturer part number and its current datasheet. A family name such as TO-247, TOLL, or a module platform does not guarantee identical pinout, dimensions, creepage features, pad layout, mounting method, or thermal limits across suppliers.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Why_Does_SiC_Package_Choice_Matter\"><\/span>Why Does SiC Package Choice Matter?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Package choice matters because SiC devices can switch with fast voltage and current edges. The package and PCB together form parasitic inductances and capacitances that may limit usable switching speed or create overshoot, ringing, false turn-on, common-mode current, and measurement error.<\/p>\n<ul>\n<li><strong>Electrical path:<\/strong> lead length, terminal geometry, internal bonds, and bus overlap affect loop inductance.<\/li>\n<li><strong>Gate control:<\/strong> a dedicated Kelvin-source terminal can separate the driver return from load current.<\/li>\n<li><strong>Thermal path:<\/strong> heat may leave through a rear tab, a bottom pad, an insulated baseplate, or a top-side cooling surface.<\/li>\n<li><strong>Assembly:<\/strong> the package may require through-hole soldering, reflow, press-fit connections, screw terminals, or controlled mounting pressure.<\/li>\n<li><strong>Insulation:<\/strong> terminal spacing, exposed metal, isolation material, slots, coating, and the surrounding mechanics all influence the final insulation design.<\/li>\n<li><strong>Service strategy:<\/strong> a module can simplify replacement at system level, while a dense SMD solution may reduce size but require more specialized rework.<\/li>\n<\/ul>\n<h2><span class=\"ez-toc-section\" id=\"Which_SiC_Package_Types_Are_Used_in_Power_Electronics\"><\/span>Which SiC Package Types Are Used in Power Electronics?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Current SiC portfolios span through-hole discretes, surface-mount discretes, top-side-cooled packages, and multi-die power modules. Availability depends on device generation, voltage, current, qualification, and manufacturer, so the list below is a design map rather than a universal catalog.<\/p>\n<div class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Package family<\/strong><\/td>\n<td><strong>Board interface<\/strong><\/td>\n<td><strong>Main design consequence<\/strong><\/td>\n<\/tr>\n<tr>\n<td>TO-247-3<\/td>\n<td>Through-hole, three main leads, rear thermal tab<\/td>\n<td>Familiar mounting, but the shared source path can add gate-loop feedback<\/td>\n<\/tr>\n<tr>\n<td>TO-247-4<\/td>\n<td>Through-hole with a dedicated Kelvin-source lead<\/td>\n<td>Separates driver return from power-source current when routed correctly<\/td>\n<\/tr>\n<tr>\n<td>TO-263 \/ D2PAK variants<\/td>\n<td>Surface mount with a large bottom-side pad<\/td>\n<td>Compact assembly; solder joint, copper spreading, and board thermal path are critical<\/td>\n<\/tr>\n<tr>\n<td>TOLL \/ Thin-TOLL<\/td>\n<td>Low-profile leadless surface mount<\/td>\n<td>Short electrical paths and small area, with tight land-pattern and reflow control<\/td>\n<\/tr>\n<tr>\n<td>TOLT \/ other top-side-cooled SMD<\/td>\n<td>Surface mount plus a top thermal interface<\/td>\n<td>Moves most heat toward a top heat sink and reduces dependence on PCB heat flow<\/td>\n<\/tr>\n<tr>\n<td>Insulated power module<\/td>\n<td>Pins, press-fit contacts, or terminals plus a baseplate\/top cooling surface<\/td>\n<td>Integrates multiple dies but adds bus, mounting, flatness, torque, and interface requirements<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n<p>TO package labels describe a mechanical family, not the complete electrical behavior. Compare the exact package drawing, pin assignment, isolation construction, thermal impedance, stray inductance data, land pattern, and mounting note for the selected orderable part.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"SiC_MOSFET_Packages\"><\/span>SiC MOSFET Packages<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>SiC MOSFET packages<\/strong> are often compared by voltage and current rating first, but the board should be planned around four additional questions: where the switching current flows, where the gate current returns, where the heat exits, and how the part is assembled.<\/p>\n<p>A three-lead through-hole package can be practical for established mechanical designs and lower-density production. A four-lead version provides a Kelvin-source connection, but only delivers its intended benefit when the gate driver returns to that dedicated terminal instead of sharing the high-current source route. Surface-mount packages shorten connections and support automated placement, yet exposed-pad soldering and heat spreading become part of the PCB design.<\/p>\n<p>Do not copy a silicon MOSFET footprint or gate network solely because the outline looks familiar. Faster SiC switching can expose inductance, coupling, probe-access, and insulation weaknesses that were acceptable in the earlier design.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"How_Do_SiC_Power_Modules_Differ_from_Discrete_Packages\"><\/span>How Do SiC Power Modules Differ from Discrete Packages?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>SiC power modules<\/strong> place multiple power dies and internal interconnects in one package, often on an insulated ceramic-metal substrate. A module can reduce the number of separate power packages and offer a compact bridge structure, but it does not remove the need for low-inductance external connections, controlled cooling, and coordinated mechanical design.<\/p>\n<div style=\"width: 100%; max-width: 600px; margin: 24px auto; text-align: center;\"><img loading=\"lazy\" decoding=\"async\" style=\"display: block; width: 100%; max-width: 600px; max-height: 400px; height: auto; object-fit: contain; border-radius: 8px;\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/09\/sic-discrete-vs-power-module.jpg\" alt=\"Comparison of a discrete SiC package and a SiC power module\" width=\"600\" height=\"400\" \/><\/div>\n<div class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Decision area<\/strong><\/td>\n<td><strong>Discrete packages<\/strong><\/td>\n<td><strong>Power modules<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Power-stage flexibility<\/td>\n<td>Individual devices can be arranged for the required topology<\/td>\n<td>Topology and internal connections are partly fixed by the module<\/td>\n<\/tr>\n<tr>\n<td>External interconnect<\/td>\n<td>PCB copper commonly carries power and gate connections<\/td>\n<td>PCB, busbar, terminals, or press-fit structures may share the interconnect task<\/td>\n<\/tr>\n<tr>\n<td>Cooling<\/td>\n<td>Managed per device through tab, bottom pad, or top surface<\/td>\n<td>Managed through a larger insulated baseplate or top cooling interface<\/td>\n<\/tr>\n<tr>\n<td>Assembly<\/td>\n<td>THT or reflow processes; more individual placements<\/td>\n<td>Fewer power placements, but tighter mounting, flatness, and torque control<\/td>\n<\/tr>\n<tr>\n<td>Repair approach<\/td>\n<td>A single device may be replaceable, depending on layout and damage<\/td>\n<td>The module is normally treated as one replaceable unit<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n<p>For a new <strong>sic power module design<\/strong>, freeze the electrical topology and the cooling\/mechanical stack together. Selecting a module after the PCB outline is fixed often creates long bus paths, obstructed driver placement, or an impractical heat-sink interface.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"What_Does_SiC_Power_Module_Packaging_Need_from_the_PCB\"><\/span>What Does SiC Power Module Packaging Need from the PCB?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>SiC power module packaging<\/strong> needs a PCB and mechanical assembly that respect the module&#8217;s terminal map, isolation boundary, cooling surface, and mounting sequence. The control PCB may carry gate-drive and sensing connections while a busbar or separate copper structure carries the main current.<\/p>\n<ul>\n<li>Keep gate-driver connections short and matched where parallel switches or bridge legs require symmetry.<\/li>\n<li>Place local DC-link capacitors so their current loop to the module terminals is physically compact.<\/li>\n<li>Do not route sensitive sensing lines beside high-dv\/dt nodes or through the high-current return path.<\/li>\n<li>Include tolerance for terminal position, press-fit holes, connector engagement, mounting holes, and heat-sink flatness.<\/li>\n<li>Define torque, mounting order, thermal-interface material, and allowable mechanical stress from the module supplier&#8217;s instructions.<\/li>\n<li>Provide safe probe access for gate voltage, switch-node behavior, current measurement, and temperature validation.<\/li>\n<\/ul>\n<p>Some modules expose an electrically insulated cooling surface; others require additional insulation. Never infer isolation from appearance. Use the exact module documentation and the end-product safety standard.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"How_Does_a_Kelvin_Source_Change_the_PCB_Layout\"><\/span>How Does a Kelvin Source Change the PCB Layout?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>A Kelvin-source pin gives the gate driver a dedicated reference closer to the semiconductor source potential. It reduces the unwanted voltage in the gate loop caused by load-current di\/dt through a shared source inductance.<\/p>\n<div style=\"width: 100%; max-width: 600px; margin: 24px auto; text-align: center;\"><img loading=\"lazy\" decoding=\"async\" style=\"display: block; width: 100%; max-width: 600px; max-height: 400px; height: auto; object-fit: contain; border-radius: 8px;\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/09\/sic-kelvin-source-pcb-layout.jpg\" alt=\"SiC MOSFET PCB layout with separate gate loop, Kelvin source, and power loop\" width=\"600\" height=\"400\" \/><\/div>\n<p>The PCB must preserve that separation:<\/p>\n<ul>\n<li>Return the driver&#8217;s source\/reference connection directly to the Kelvin-source terminal.<\/li>\n<li>Carry load current through the main source terminal and its wider power path.<\/li>\n<li>Place the driver, local isolated supply decoupling, and gate resistor close to the MOSFET.<\/li>\n<li>Avoid overlapping the gate path with drain or switch-node copper where capacitive coupling can inject noise.<\/li>\n<li>When devices are paralleled, review gate-path symmetry and the manufacturer&#8217;s recommended gate-resistor arrangement.<\/li>\n<\/ul>\n<p>A Kelvin terminal is not a license to lengthen the gate loop. Package inductance, via transitions, connector inductance, and the external return geometry still affect switching behavior.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"How_Should_the_Commutation_and_Gate_Loops_Be_Routed\"><\/span>How Should the Commutation and Gate Loops Be Routed?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Route the commutation loop and gate loop as two deliberately controlled structures. The high-current loop should be short and use closely coupled outgoing and return conductors. The gate loop should be compact, protected from the switch node, and referenced to the correct source terminal.<\/p>\n<ol>\n<li><strong>Place the local DC-link capacitor first.<\/strong> Put it across the switching cell before routing peripheral power paths.<\/li>\n<li><strong>Minimize loop area.<\/strong> Use overlapping planes or closely spaced conductors where voltage and insulation constraints allow.<\/li>\n<li><strong>Keep switch-node copper purposeful.<\/strong> It must carry current and spread heat, but excess area can increase capacitive coupling.<\/li>\n<li><strong>Place the driver next to the device.<\/strong> Long control traces add inductance and make the gate more vulnerable to noise.<\/li>\n<li><strong>Separate sensing from power current.<\/strong> Current shunts, desaturation protection, temperature sensing, and voltage dividers need controlled reference paths.<\/li>\n<li><strong>Design measurement access.<\/strong> Probe loops and long ground leads can misrepresent fast waveforms; plan low-inductance test connections.<\/li>\n<\/ol>\n<p>For systems above basic low-voltage logic levels, package spacing is only one part of the insulation path. Our <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/08\/high-voltage-pcb-design\/\">high-voltage PCB design<\/a> guide explains why working voltage, transients, pollution degree, altitude, material group, coating, slots, and nearby metalwork must be reviewed together.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"How_Do_Top-Side_and_Bottom-Side_Cooling_Differ\"><\/span>How Do Top-Side and Bottom-Side Cooling Differ?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Top-side cooling sends heat directly from the package&#8217;s exposed upper surface to a heat sink or cold plate. Bottom-side cooling sends heat into a soldered pad and then through PCB copper, vias, an insulated metal substrate, or a lower heat spreader.<\/p>\n<div style=\"width: 100%; max-width: 600px; margin: 24px auto; text-align: center;\"><img loading=\"lazy\" decoding=\"async\" style=\"display: block; width: 100%; max-width: 600px; max-height: 400px; height: auto; object-fit: contain; border-radius: 8px;\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/09\/sic-package-cooling-paths.jpg\" alt=\"Top-side and bottom-side cooling paths for SiC surface-mount packages\" width=\"600\" height=\"400\" \/><\/div>\n<p>Top-side cooling can reduce the PCB&#8217;s thermal burden and free the lower board surface for routing or insulation. It introduces mechanical questions about interface compression, heat-sink flatness, package-height tolerance, electrical isolation, and assembly sequence. Bottom-side cooling can be simpler mechanically, but board thermal resistance and solder-joint quality become more influential.<\/p>\n<p>For bottom-side exposed pads, <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/thermal-vias\/\">thermal vias<\/a> may help move heat through the board. Their diameter, pitch, plating, fill\/cap method, connection to inner copper, and effect on solder wicking must be designed as one thermal and assembly system. Thermal simulation should be correlated with measurements on the assembled unit under representative load and airflow.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"What_PCB_and_Assembly_Details_Should_Be_Checked\"><\/span>What PCB and Assembly Details Should Be Checked?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Manufacturing review should begin before the device footprint is locked. High-current copper, large exposed pads, mixed thermal mass, isolation slots, and heat-sink hardware can create competing fabrication and assembly requirements.<\/p>\n<ul>\n<li><strong>Footprint source:<\/strong> use the current package drawing and recommended land pattern for the exact part number.<\/li>\n<li><strong>Copper construction:<\/strong> state finished copper, plated features, current paths, copper balance, and any heavy-copper transition.<\/li>\n<li><strong>Stencil design:<\/strong> divide large paste apertures where needed and define the target from package and process guidance.<\/li>\n<li><strong>Reflow and moisture handling:<\/strong> follow the component&#8217;s package-specific limits; do not apply a generic profile to every SiC device.<\/li>\n<li><strong>THT handling:<\/strong> control lead forming, insertion, solder fill, component standoff, heat-sink attachment, and mechanical load.<\/li>\n<li><strong>Module mechanics:<\/strong> document coplanarity, hole tolerance, fastener stack, torque, thermal interface, and assembly order.<\/li>\n<li><strong>Cleanliness and coating:<\/strong> confirm flux residues, coating keep-outs, coverage near high-voltage pins, and compatibility with the operating environment.<\/li>\n<\/ul>\n<p>Heavy copper may support current distribution and spreading, but it also changes etching, resin fill, drilling, plating, solder mask, and reflow behavior. Review our <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/06\/4-layer-heavy-copper-pcb\/\">4-layer heavy copper PCB<\/a> article when the power stage uses thick copper rather than a separate bus structure.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"How_Should_SiC_Package_Assembly_Be_Inspected\"><\/span>How Should SiC Package Assembly Be Inspected?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Inspection must match the joint and package. AOI can check visible leads, polarity, placement, and surface solder. It cannot fully assess a hidden exposed-pad joint, internal voiding, or an obscured module interface.<\/p>\n<div style=\"width: 100%; max-width: 600px; margin: 24px auto; text-align: center;\"><img loading=\"lazy\" decoding=\"async\" style=\"display: block; width: 100%; max-width: 600px; max-height: 400px; height: auto; object-fit: contain; border-radius: 8px;\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/09\/sic-package-xray-inspection.jpg\" alt=\"X-ray inspection of solder beneath a high-power SiC package on a PCB assembly\" width=\"600\" height=\"400\" \/><\/div>\n<ul>\n<li>Use AOI or visual inspection for visible terminals, alignment, solder bridges, polarity, and component damage.<\/li>\n<li>Use X-ray where the critical solder interface is hidden and the acceptance plan requires it.<\/li>\n<li>Inspect THT solder fill and lead condition according to the agreed workmanship criteria.<\/li>\n<li>Verify module seating, fastener torque records, interface coverage, connector engagement, and isolation hardware.<\/li>\n<li>Validate electrically with controlled power-up, gate-waveform checks, protection tests, temperature monitoring, and application-relevant load conditions.<\/li>\n<\/ul>\n<p><a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/04\/x-ray-inspection-for-pcb-assembly\/\">X-ray inspection for PCB assembly<\/a> is evidence about hidden joint geometry, not proof of complete electrical or thermal performance. Define what the image must detect and how the result will be judged before production.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Which_SiC_Package_Fits_the_Application\"><\/span>Which SiC Package Fits the Application?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>The best package is the one that satisfies the complete electrical, thermal, mechanical, assembly, safety, and sourcing case. A smaller outline is not automatically better, and a module is not automatically easier.<\/p>\n<div class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Project priority<\/strong><\/td>\n<td><strong>Package direction to evaluate<\/strong><\/td>\n<td><strong>Required confirmation<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Familiar through-hole mechanics<\/td>\n<td>TO-247 family<\/td>\n<td>Kelvin option, lead spacing, heat-sink isolation, and solder process<\/td>\n<\/tr>\n<tr>\n<td>Compact automated assembly<\/td>\n<td>D2PAK, TOLL, or related SMD family<\/td>\n<td>Land pattern, stencil, void control, board thermal path, and rework<\/td>\n<\/tr>\n<tr>\n<td>Direct heat extraction above the PCB<\/td>\n<td>Top-side-cooled SMD package<\/td>\n<td>Interface material, compression, height tolerance, and electrical isolation<\/td>\n<\/tr>\n<tr>\n<td>Integrated bridge at higher power<\/td>\n<td>SiC power module<\/td>\n<td>Bus layout, cooling plate, terminal system, driver placement, and mounting sequence<\/td>\n<\/tr>\n<tr>\n<td>Fast switching with controlled gate reference<\/td>\n<td>Package with a Kelvin-source terminal<\/td>\n<td>Pinout, separate return routing, gate-loop geometry, and overshoot validation<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n<p>Before release, provide the device orderable part number, datasheet revision, footprint source, schematic, Gerber or ODB++ data, stackup, copper requirements, BOM, assembly drawing, cooling stack, mechanical drawing, insulation requirements, applicable workmanship criteria, test plan, quantity, and target schedule. This package lets the PCB and assembly teams review the same physical system instead of making separate assumptions.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"FAQ_About_SiC_Packages\"><\/span>FAQ About SiC Packages<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Are all four-lead SiC MOSFET packages Kelvin-source devices?<\/strong> No. Check the exact pin assignment in the datasheet. A fourth lead can support a Kelvin-source function, but package families and pin orders are not interchangeable.<\/p>\n<p><strong>Can a TO-247-4 device use a TO-247-3 PCB footprint?<\/strong> Do not assume so. The lead count, spacing, body dimensions, mounting geometry, and intended source routing may differ. Use the recommended footprint for the exact part.<\/p>\n<p><strong>Does a SiC power module eliminate PCB parasitic inductance?<\/strong> No. Internal module design can reduce some parasitics, but external bus, capacitor, gate-driver, sensing, and connector paths still contribute inductance and coupling.<\/p>\n<p><strong>Is top-side cooling always better than bottom-side cooling?<\/strong> No. It can shorten the heat path through the package, but it adds heat-sink, interface, tolerance, isolation, and assembly requirements. The better choice depends on the complete mechanical and thermal design.<\/p>\n<p><strong>Can solder-void limits be copied from another exposed-pad package?<\/strong> No. Use the device supplier&#8217;s mounting guidance, the agreed workmanship criteria, thermal model, and validated assembly process. Location and shape can matter as much as total void area.<\/p>\n<p><strong>Do faster SiC edges always improve converter performance?<\/strong> No. Faster switching may reduce switching loss, but can increase overshoot, ringing, EMI, common-mode current, and stress if the package and PCB loops are not controlled.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"How_Can_EBest_Circuit_Support_Your_SiC_Power_PCB\"><\/span>How Can EBest Circuit Support Your SiC Power PCB?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>At EBest Circuit, we support PCB design review, prototyping, fabrication, component sourcing, PCB assembly, AOI, X-ray inspection, and functional-test coordination for power-electronics projects. For a SiC design, our review can connect the selected package to the footprint, stackup, copper distribution, thermal-via structure, insulation features, stencil strategy, assembly sequence, and inspection plan.<\/p>\n<p>Send the exact SiC part numbers, Gerber files, BOM, stackup or current requirements, cooling and mechanical drawings, test requirements, and quantity to <a href=\"mailto:sales@bestpcbs.com\">sales@bestpcbs.com<\/a>. We will review the manufacturing package and identify PCB or assembly items that should be resolved before production. For reference during design release, keep this <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/sic-packages\/\">SiC packages guide<\/a> with the approved component and mechanical documentation.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Compare SiC packages, discrete and module formats, cooling paths, Kelvin-source routing, assembly risks, and PCB design checks for power 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09:26:04","updated":"2026-09-03 02:31:35","seo_analyzer_scan_date":null},"aioseo_breadcrumb":"<div class=\"aioseo-breadcrumbs\"><span class=\"aioseo-breadcrumb\">\n\t\t\t<a href=\"https:\/\/www.bestpcbs.com\/blog\" title=\"Home\">Home<\/a>\n\t\t<\/span><span class=\"aioseo-breadcrumb-separator\">\u00bb<\/span><span class=\"aioseo-breadcrumb\">\n\t\t\t<a href=\"https:\/\/www.bestpcbs.com\/blog\/category\/pcb-technology\/\" title=\"PCB Technology\">PCB Technology<\/a>\n\t\t<\/span><span class=\"aioseo-breadcrumb-separator\">\u00bb<\/span><span class=\"aioseo-breadcrumb\">\n\t\t\tSiC Packages: How Package Choice Changes PCB Design\n\t\t<\/span><\/div>","aioseo_breadcrumb_json":[{"label":"Home","link":"https:\/\/www.bestpcbs.com\/blog"},{"label":"PCB Technology","link":"https:\/\/www.bestpcbs.com\/blog\/category\/pcb-technology\/"},{"label":"SiC Packages: How Package Choice Changes PCB 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