{"id":34859,"date":"2026-09-01T14:39:42","date_gmt":"2026-09-01T06:39:42","guid":{"rendered":"https:\/\/www.bestpcbs.com\/blog\/?p=34859"},"modified":"2026-09-01T14:57:53","modified_gmt":"2026-09-01T06:57:53","slug":"uhdi-printed-circuit-board","status":"publish","type":"post","link":"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/uhdi-printed-circuit-board\/","title":{"rendered":"UHDI Printed Circuit Board: Design Rules, Stackup, and DFM"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_85 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/uhdi-printed-circuit-board\/#What_Is_a_UHDI_Printed_Circuit_Board\" >What Is a UHDI Printed Circuit Board?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/uhdi-printed-circuit-board\/#How_Does_UHDI_Differ_from_Conventional_HDI\" >How Does UHDI Differ from Conventional HDI?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/uhdi-printed-circuit-board\/#HDI_PCB_Design_Guidelines_for_UHDI_Layouts\" >HDI PCB Design Guidelines for UHDI Layouts<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/uhdi-printed-circuit-board\/#HDI_PCB_Stackup_Decisions_for_UHDI\" >HDI PCB Stackup Decisions for UHDI<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/uhdi-printed-circuit-board\/#How_Does_the_HDI_PCB_Manufacturing_Process_Change_for_UHDI\" >How Does the HDI PCB Manufacturing Process Change for UHDI?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/uhdi-printed-circuit-board\/#Which_DFM_Risks_Cause_UHDI_Prototype_Failure\" >Which DFM Risks Cause UHDI Prototype Failure?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/uhdi-printed-circuit-board\/#What_Inspection_Evidence_Should_Be_Defined\" >What Inspection Evidence Should Be Defined?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/uhdi-printed-circuit-board\/#How_Do_UHDI_Choices_Affect_Cost_and_Lead_Time\" >How Do UHDI Choices Affect Cost and Lead Time?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/uhdi-printed-circuit-board\/#What_Should_Be_Included_in_a_UHDI_RFQ_Package\" >What Should Be Included in a UHDI RFQ Package?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/uhdi-printed-circuit-board\/#FAQ_About_UHDI_Printed_Circuit_Boards\" >FAQ About UHDI Printed Circuit Boards<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-11\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/uhdi-printed-circuit-board\/#How_Can_EBest_Circuit_Review_Your_UHDI_Project\" >How Can EBest Circuit Review Your UHDI Project?<\/a><\/li><\/ul><\/nav><\/div>\n<div class=\"yzp-no-index\"><\/div><p>A <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/uhdi-printed-circuit-board\/\">UHDI printed circuit board<\/a> moves beyond conventional HDI when at least one critical feature enters the ultra-fine range. That change affects far more than trace width. The imaging method, copper build, microvia geometry, dielectric thickness, registration plan, solder mask, inspection criteria, and assembly interface must be treated as one manufacturing system.<\/p>\n<p>This guide helps design and procurement teams decide whether a project is truly UHDI, where early DFM work prevents redesign, and what evidence should be agreed before prototype release. It also separates published working thresholds from a supplier&#8217;s confirmed production capability\u2014an important distinction when yield, reliability, and repeatability matter.<\/p>\n<figure class=\"wp-block-image\" style=\"max-width:600px;margin:24px auto;\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/09\/uhdi-printed-circuit-board-hero.jpg\" alt=\"UHDI printed circuit board with ultra-fine traces and laser microvias\" width=\"600\" height=\"400\" style=\"display:block;width:100%;max-width:600px;max-height:400px;height:auto;object-fit:contain;margin:0 auto;\"><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"What_Is_a_UHDI_Printed_Circuit_Board\"><\/span>What Is a UHDI Printed Circuit Board?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>UHDI means ultra-high-density interconnect. The industry&#8217;s working definition generally places a board in UHDI territory when one or more features go beyond the highest conventional HDI producibility range. Common reference thresholds include:<\/p>\n<ul>\n<li>Conductor line width below 50 \u00b5m.<\/li>\n<li>Conductor spacing below 50 \u00b5m.<\/li>\n<li>Build-up dielectric thickness below 50 \u00b5m.<\/li>\n<li>Laser microvia diameter below 75 \u00b5m.<\/li>\n<\/ul>\n<p>These figures are useful screening points, not permission to combine every minimum on one design. A board with 45 \u00b5m spacing on one layer may require a different process route from a board with 60 \u00b5m traces and 50 \u00b5m microvias. Material, copper thickness, panel format, feature distribution, registration tolerance, surface finish, and annual volume all affect the real production window.<\/p>\n<p>The shorter phrase <strong>ultra hdi pcb<\/strong> often refers to the same technology. In practice, the fabrication drawing should state the actual features and acceptance requirements instead of relying on the label alone.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"How_Does_UHDI_Differ_from_Conventional_HDI\"><\/span>How Does UHDI Differ from Conventional HDI?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Conventional HDI gains density through laser microvias, blind or buried connections, sequential lamination, and via-in-pad. UHDI keeps those concepts but pushes selected geometries beyond conventional HDI process limits. That shift changes both the fabrication method and the amount of process verification required.<\/p>\n<div class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Design Area<\/strong><\/td>\n<td><strong>Conventional HDI<\/strong><\/td>\n<td><strong>UHDI Consideration<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Fine conductors<\/td>\n<td>Often produced by optimized subtractive etching<\/td>\n<td>May require mSAP, SAP, or another ultra-fine-line process<\/td>\n<\/tr>\n<tr>\n<td>Microvias<\/td>\n<td>Laser-drilled vias commonly around the 0.10 mm class<\/td>\n<td>Smaller geometry needs tighter drilling, plating, and registration control<\/td>\n<\/tr>\n<tr>\n<td>Dielectrics<\/td>\n<td>Build-up films selected around a proven HDI stackup<\/td>\n<td>Very thin dielectrics make copper balance and via aspect ratio more sensitive<\/td>\n<\/tr>\n<tr>\n<td>Inspection<\/td>\n<td>AOI, electrical test, impedance test, and microsection as specified<\/td>\n<td>More detailed coupons, dimensional evidence, and agreed acceptance rules may be needed<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n<p>A designer should therefore ask, \u201cWhich features require UHDI?\u201d rather than applying ultra-fine geometry across every layer. Restricting the most demanding rules to the package escape or other density-critical zones can improve yield and cost without sacrificing electrical performance.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"HDI_PCB_Design_Guidelines_for_UHDI_Layouts\"><\/span>HDI PCB Design Guidelines for UHDI Layouts<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Useful <strong>hdi pcb design guidelines<\/strong> begin with the fabricator&#8217;s production window, not the CAD tool&#8217;s minimum setting. The following decisions should be closed before routing is frozen:<\/p>\n<ul>\n<li><strong>Define the density driver.<\/strong> Record BGA pitch, pad diameter, escape count, available routing channels, and the layers that genuinely need ultra-fine features.<\/li>\n<li><strong>Use regional rules.<\/strong> Keep wider traces and spaces outside dense package fields where possible. A mixed-rule design is usually easier to control than a board built entirely at the minimum.<\/li>\n<li><strong>Separate line and space values.<\/strong> Do not assume a supplier&#8217;s minimum line width automatically permits the same minimum clearance after plating.<\/li>\n<li><strong>Coordinate copper with geometry.<\/strong> Thicker copper is harder to resolve into very fine conductors. Base copper and final copper must both appear in the fabrication notes.<\/li>\n<li><strong>Treat solder mask as a precision layer.<\/strong> Mask registration, dam width, pad definition, and via treatment can determine whether fine-pitch assembly is practical.<\/li>\n<li><strong>Control impedance from the real stackup.<\/strong> Trace geometry, dielectric thickness, resin content, copper profile, and reference-plane distance must be reviewed together.<\/li>\n<\/ul>\n<p>Do not design every feature at a supplier&#8217;s stated limit. The published minimum may describe a test coupon or a restricted build, while the stable production value may be wider. A useful DFM conversation distinguishes prototype feasibility, repeatable production, and the conditions attached to each.<\/p>\n<figure class=\"wp-block-image\" style=\"max-width:600px;margin:24px auto;\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/09\/uhdi-hdi-feature-comparison.jpg\" alt=\"Comparison of conventional HDI and UHDI PCB trace and microvia geometry\" width=\"600\" height=\"400\" style=\"display:block;width:100%;max-width:600px;max-height:400px;height:auto;object-fit:contain;margin:0 auto;\"><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"HDI_PCB_Stackup_Decisions_for_UHDI\"><\/span>HDI PCB Stackup Decisions for UHDI<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>An <strong>hdi pcb stackup<\/strong> cannot be finalized independently from the escape strategy. The number of build-up layers, microvia spans, plane assignment, material family, and impedance targets determine the lamination sequence and the inspection plan.<\/p>\n<p>Review these points together:<\/p>\n<ul>\n<li><strong>Build-up architecture:<\/strong> confirm whether 1+N+1, 2+N+2, any-layer, or another construction is actually required.<\/li>\n<li><strong>Microvia type:<\/strong> use staggered microvias where routing permits; specify stacked structures only where density justifies the additional process and reliability burden.<\/li>\n<li><strong>Via aspect ratio:<\/strong> match microvia diameter to dielectric depth. A small opening through an unnecessarily deep dielectric creates plating risk.<\/li>\n<li><strong>Via fill and cap:<\/strong> via-in-pad normally requires a defined fill, planarization, and cap-plating sequence before component assembly.<\/li>\n<li><strong>Stack symmetry:<\/strong> balance copper and dielectric construction to reduce bow, twist, and registration drift through repeated thermal cycles.<\/li>\n<li><strong>Material availability:<\/strong> confirm the exact laminate, build-up film, copper foil profile, thickness tolerance, and approved substitutes before impedance values are released.<\/li>\n<\/ul>\n<p>Early stackup review is especially important when UHDI routing is combined with high-speed interfaces. Our existing guide to <a href=\"https:\/\/www.bestpcbs.com\/products\/HDI-board.htm\">HDI PCB structures<\/a> explains conventional 1+N+1, 2+N+2, and every-layer interconnect concepts, while the separate <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/06\/uhdi-pcb-2\/\">80 GHz UHDI PCB article<\/a> focuses on RF material and impedance concerns.<\/p>\n<figure class=\"wp-block-image\" style=\"max-width:600px;margin:24px auto;\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/09\/uhdi-pcb-stackup-microvias.jpg\" alt=\"UHDI PCB stackup showing staggered and stacked laser microvias\" width=\"600\" height=\"400\" style=\"display:block;width:100%;max-width:600px;max-height:400px;height:auto;object-fit:contain;margin:0 auto;\"><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"How_Does_the_HDI_PCB_Manufacturing_Process_Change_for_UHDI\"><\/span>How Does the HDI PCB Manufacturing Process Change for UHDI?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>The <strong>hdi pcb manufacturing process<\/strong> normally uses sequential build-up, laser drilling, copper deposition, imaging, plating, lamination, and electrical verification. UHDI adds tighter interactions between these steps and may change the conductor-forming method.<\/p>\n<ol>\n<li><strong>Engineering review:<\/strong> identify every sub-50 \u00b5m feature, microvia span, impedance structure, copper requirement, and inspection coupon.<\/li>\n<li><strong>Material and process selection:<\/strong> choose a laminate, build-up dielectric, copper foil, and imaging route that can hold the requested geometry.<\/li>\n<li><strong>Core and build-up imaging:<\/strong> form fine conductors with a process selected for the target line, space, and copper thickness.<\/li>\n<li><strong>Laser drilling and desmear:<\/strong> control via diameter, taper, landing accuracy, and the condition of the target pad.<\/li>\n<li><strong>Metallization and filling:<\/strong> establish reliable copper in the microvia, fill specified structures, and planarize via-in-pad surfaces.<\/li>\n<li><strong>Sequential lamination:<\/strong> repeat build-up cycles while controlling registration, resin flow, copper balance, and thickness.<\/li>\n<li><strong>Surface formation:<\/strong> apply solder mask and surface finish without consuming the clearances needed for fine-pitch assembly.<\/li>\n<li><strong>Inspection and test:<\/strong> use AOI, electrical testing, microsection, dimensional measurement, impedance testing, or other project-specific evidence.<\/li>\n<\/ol>\n<p>Subtractive etching can support some near-UHDI geometries, but very fine and consistent conductors may require modified semi-additive or semi-additive processing. The correct route depends on feature size, copper thickness, layer location, panel scale, volume, and supplier capability. It should be confirmed before the layout is locked.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Which_DFM_Risks_Cause_UHDI_Prototype_Failure\"><\/span>Which DFM Risks Cause UHDI Prototype Failure?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>UHDI prototypes most often become expensive when a local density decision triggers an unplanned process change. The risk is rarely one number in isolation.<\/p>\n<ul>\n<li><strong>Minimum geometry used everywhere:<\/strong> reduces the process margin across the whole panel even though only a small BGA area needs it.<\/li>\n<li><strong>Excessive stacked microvias:<\/strong> increases lamination count and concentrates thermo-mechanical stress.<\/li>\n<li><strong>Unconfirmed copper build:<\/strong> fine lines may not survive the plating and etching sequence at the requested final copper.<\/li>\n<li><strong>Ambiguous via notes:<\/strong> missing fill, cap, target-layer, or aspect-ratio requirements can change both cost and reliability.<\/li>\n<li><strong>Late impedance modeling:<\/strong> forces trace-width or dielectric changes after routing is complete.<\/li>\n<li><strong>Insufficient mask clearance:<\/strong> causes assembly constraints even when the copper pattern can be fabricated.<\/li>\n<li><strong>No agreed acceptance plan:<\/strong> leaves the customer and supplier evaluating fine features with different criteria.<\/li>\n<\/ul>\n<p>A strong DFM response should show what must change, why it matters, and whether the recommendation affects electrical performance. \u201cCannot build\u201d is not enough; the customer needs an alternative feature, stackup, or process route.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"What_Inspection_Evidence_Should_Be_Defined\"><\/span>What Inspection Evidence Should Be Defined?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Electrical continuity alone cannot prove that a UHDI process is stable. The inspection plan should follow the critical risks in the design and may include:<\/p>\n<ul>\n<li>AOI coverage for fine-line layers.<\/li>\n<li>Microsection locations that represent stacked or staggered microvias.<\/li>\n<li>Measurement of finished line width, spacing, dielectric thickness, and via geometry.<\/li>\n<li>Impedance coupons that match the controlled layers and copper construction.<\/li>\n<li>Electrical test coverage and netlist source.<\/li>\n<li>Surface-finish thickness or wire-bond acceptance criteria when applicable.<\/li>\n<li>Assembly X-ray or other inspection for fine-pitch packages when the project includes PCBA.<\/li>\n<\/ul>\n<p>At EBest Circuit, our documented quality resources include AOI, electrical testing, impedance testing, microsection inspection, copper-thickness testing, 2D measurement, and X-ray inspection for relevant assembly work. The final test plan still depends on the product, customer specification, and confirmed process route. See our <a href=\"https:\/\/www.bestpcbs.com\/quality\/index.htm\">PCB quality and testing overview<\/a> for the broader control framework.<\/p>\n<figure class=\"wp-block-image\" style=\"max-width:600px;margin:24px auto;\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/09\/uhdi-pcb-inspection.jpg\" alt=\"UHDI PCB microsection and automated optical inspection workflow\" width=\"600\" height=\"400\" style=\"display:block;width:100%;max-width:600px;max-height:400px;height:auto;object-fit:contain;margin:0 auto;\"><\/figure>\n<h2><span class=\"ez-toc-section\" id=\"How_Do_UHDI_Choices_Affect_Cost_and_Lead_Time\"><\/span>How Do UHDI Choices Affect Cost and Lead Time?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>UHDI does not automatically make the lowest system cost, even when it reduces board area. Cost and lead time rise when a design adds specialized material, semi-additive conductor formation, more lamination cycles, stacked microvias, tight registration, extra coupons, or low-yield feature combinations.<\/p>\n<p>The practical cost levers are:<\/p>\n<ul>\n<li>How many layers actually need ultra-fine line and space.<\/li>\n<li>Whether a standard panel and material construction can be used.<\/li>\n<li>The number of sequential lamination cycles.<\/li>\n<li>Staggered versus stacked microvia architecture.<\/li>\n<li>Base and finished copper thickness.<\/li>\n<li>Surface finish and fine-pitch assembly requirements.<\/li>\n<li>Prototype quantity, test evidence, and volume forecast.<\/li>\n<\/ul>\n<p>A compact UHDI board can still lower total product cost when it removes connectors, reduces board area or layer count, shortens critical interconnects, or enables a smaller enclosure. The comparison should therefore use total system impact, not PCB unit price alone.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"What_Should_Be_Included_in_a_UHDI_RFQ_Package\"><\/span>What Should Be Included in a UHDI RFQ Package?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Provide enough information for the supplier to evaluate the exact feature combination. A useful package includes:<\/p>\n<ul>\n<li>Gerber or ODB++ fabrication data and the fabrication drawing.<\/li>\n<li>Proposed layer stackup, material family, finished thickness, and copper weights.<\/li>\n<li>A list of the minimum line, minimum spacing, smallest microvia, and affected layers.<\/li>\n<li>Microvia spans, stacked or staggered structure, via fill, and cap-plating notes.<\/li>\n<li>Controlled-impedance table and reference-layer information.<\/li>\n<li>Surface finish, solder mask, legend, and assembly constraints.<\/li>\n<li>Test standard, inspection evidence, coupon requirements, and acceptance class.<\/li>\n<li>Prototype quantity, expected annual volume, and requested delivery date.<\/li>\n<li>BOM, pick-and-place data, and assembly drawing when PCBA is required.<\/li>\n<\/ul>\n<p>For a general supplier overview, you can also review our existing <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/04\/uhdi-pcb\/\">UHDI PCB fabrication page<\/a>. Its purpose is supplier selection, while this page is intended to help engineering teams prepare a manufacturable design package.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"FAQ_About_UHDI_Printed_Circuit_Boards\"><\/span>FAQ About UHDI Printed Circuit Boards<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<h3>Is every board with microvias a UHDI PCB?<\/h3>\n<p>No. Microvias are common in conventional HDI. UHDI is associated with one or more features beyond conventional HDI thresholds, such as sub-50 \u00b5m lines or spaces, sub-50 \u00b5m build-up dielectrics, or microvias below the 75 \u00b5m range.<\/p>\n<h3>Does UHDI always require mSAP?<\/h3>\n<p>No. The conductor-forming method depends on the target geometry, copper thickness, layer, panel, and supplier. Some near-UHDI features may be possible with advanced subtractive control, while tighter and more uniform conductors may need mSAP or SAP.<\/p>\n<h3>Are stacked microvias better than staggered microvias?<\/h3>\n<p>Not automatically. Stacked microvias save routing area, but they add process complexity and reliability sensitivity. Use them where density requires them; use staggered structures where the layout allows a more forgiving construction.<\/p>\n<h3>Can standard HDI design rules be reused for UHDI?<\/h3>\n<p>They are a starting point, not a release condition. UHDI requires a supplier-specific review of fine-line formation, dielectric depth, via geometry, copper build, registration, solder mask, inspection, and production volume.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"How_Can_EBest_Circuit_Review_Your_UHDI_Project\"><\/span>How Can EBest Circuit Review Your UHDI Project?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>EBest Circuit has provided PCB and PCBA support since 2006. We work with customers on PCB design review, prototyping, multilayer and HDI fabrication, component sourcing, assembly, and testing. Our documented management and compliance resources include ISO 9001:2015, ISO 13485:2016, IATF 16949, AS9100D, UL, RoHS, and REACH; applicability should be confirmed for the specific product and production route.<\/p>\n<p>For a true UHDI request, we do not treat a marketing label as a capability approval. Our team first reviews the line and space by layer, dielectric construction, microvia geometry, copper build, stackup, impedance, surface finish, quantity, and required evidence. We then confirm whether the project fits an available process route or needs design adjustment. You can also review our broader <a href=\"https:\/\/www.bestpcbs.com\/about\/capability.htm\">PCB manufacturing capability<\/a> information.<\/p>\n<p>Send your Gerber or ODB++ files, stackup, impedance table, fabrication drawing, quantity, and test requirements to <a href=\"mailto:sales@bestpcbs.com\">sales@bestpcbs.com<\/a>. We will help identify the density-critical features, return practical DFM feedback, and confirm a manufacturable path for your <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/09\/uhdi-printed-circuit-board\/\">UHDI printed circuit board<\/a> before quotation.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Learn how a UHDI printed circuit board differs from HDI, including fine-line thresholds, microvias, stackup, fabrication risks, inspection, and DFM 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