{"id":32139,"date":"2026-07-23T18:23:15","date_gmt":"2026-07-23T10:23:15","guid":{"rendered":"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-aspect-ratio\/"},"modified":"2026-07-23T18:33:32","modified_gmt":"2026-07-23T10:33:32","slug":"pcb-aspect-ratio","status":"publish","type":"post","link":"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-aspect-ratio\/","title":{"rendered":"How to Calculate PCB Aspect Ratio and Choose the Right Via Size?"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_84 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-aspect-ratio\/#What_Is_PCB_Aspect_Ratio_and_Why_Does_It_Matter_When_Choosing_Via_Size\" >What Is PCB Aspect Ratio and Why Does It Matter When Choosing Via Size?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-aspect-ratio\/#Which_Measurements_Do_You_Need_Before_Calculating_PCB_Aspect_Ratio\" >Which Measurements Do You Need Before Calculating PCB Aspect Ratio?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-aspect-ratio\/#What_Is_the_PCB_Aspect_Ratio_Formula_and_How_Do_You_Apply_It_to_Different_Via_Types\" >What Is the PCB Aspect Ratio Formula, and How Do You Apply It to Different Via Types?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-aspect-ratio\/#Should_You_Use_Drill_Size_or_Finished_Hole_Size_in_the_Calculation\" >Should You Use Drill Size or Finished Hole Size in the Calculation?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-aspect-ratio\/#How_Do_You_Calculate_the_Minimum_Via_Hole_Size_for_a_Given_Board_Thickness\" >How Do You Calculate the Minimum Via Hole Size for a Given Board Thickness?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-aspect-ratio\/#What_Are_the_Typical_PCB_Aspect_Ratio_Limits_for_Different_Via_Types\" >What Are the Typical PCB Aspect Ratio Limits for Different Via Types?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-aspect-ratio\/#How_Do_Board_Thickness_Layer_Count_and_Stackup_Affect_Via_Size\" >How Do Board Thickness, Layer Count and Stackup Affect Via Size?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-aspect-ratio\/#How_Do_Pad_Diameter_Annular_Ring_and_Hole_Tolerance_Affect_Final_Via_Size\" >How Do Pad Diameter, Annular Ring and Hole Tolerance Affect Final Via Size?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-aspect-ratio\/#How_Do_Copper_Plating_and_Reliability_Requirements_Affect_Via_Size_Selection\" >How Do Copper Plating and Reliability Requirements Affect Via Size Selection?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-aspect-ratio\/#When_Should_You_Choose_Through-Hole_Blind_Buried_or_Microvias\" >When Should You Choose Through-Hole, Blind, Buried or Microvias?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-11\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-aspect-ratio\/#How_Can_You_Check_PCB_Aspect_Ratio_and_Via_Size_During_DFM_Review\" >How Can You Check PCB Aspect Ratio and Via Size During DFM Review?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-12\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-aspect-ratio\/#Which_Via_Sizing_Mistakes_Increase_Cost_or_Cause_Fabrication_Defects\" >Which Via Sizing Mistakes Increase Cost or Cause Fabrication Defects?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-13\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-aspect-ratio\/#What_Via_Specifications_and_PCB_Files_Should_You_Send_for_Manufacturing_Review\" >What Via Specifications and PCB Files Should You Send for Manufacturing Review?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-14\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-aspect-ratio\/#FAQs_About_PCB_Aspect_Ratio\" >FAQs About PCB Aspect Ratio<\/a><\/li><\/ul><\/nav><\/div>\n<div class=\"yzp-no-index\"><\/div><style>.post-32139 h1._title{word-break:normal!important;overflow-wrap:break-word!important}<\/style>\n<p><strong><a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-aspect-ratio\/\">PCB Aspect Ratio<\/a> is plated-hole depth divided by reference diameter.<\/strong> Calculate it from the actual via span and the fabricator\u2019s diameter convention, then verify the pad, annular ring, plating and tolerances before approving the via.<\/p>\n<p class=\"article-image\" style=\"text-align:center;margin:1.5rem auto;\"><img fetchpriority=\"high\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/07\/pcb-aspect-ratio-hero.jpg\" alt=\"PCB Aspect Ratio shown on a multilayer board with a plated through-hole cross-section\" width=\"600\" height=\"400\" style=\"display:block;width:100%;max-width:600px;height:auto;margin:0 auto;\" class=\"aligncenter size-full\" loading=\"eager\" decoding=\"async\"><\/p>\n<h2><span class=\"ez-toc-section\" id=\"What_Is_PCB_Aspect_Ratio_and_Why_Does_It_Matter_When_Choosing_Via_Size\"><\/span>What Is PCB Aspect Ratio and Why Does It Matter When Choosing Via Size?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>PCB Aspect Ratio compares plated-hole depth with hole diameter.<\/strong> A higher PCB Aspect Ratio makes desmear, solution exchange and copper deposition at the barrel center more difficult, increasing the risk of thin copper, voids and thermal-cycle failure.<\/p>\n<ul>\n<li><strong>Plating:<\/strong> Confirm that the ratio is below the fabricator\u2019s approved limit with allowance for board-thickness and hole-size tolerances.<\/li>\n<li><strong>Routing:<\/strong> Check whether a larger drill and pad would remove routing channels or reduce plane clearance.<\/li>\n<li><strong>Via structure:<\/strong> Use blind, buried or microvias only when a shorter span solves a verified density or signal-integrity constraint.<\/li>\n<li><strong>Complete geometry:<\/strong> Approve the via only when the hole, pad, annular ring, antipad and layer span pass together.<\/li>\n<\/ul>\n<h2><span class=\"ez-toc-section\" id=\"Which_Measurements_Do_You_Need_Before_Calculating_PCB_Aspect_Ratio\"><\/span>Which Measurements Do You Need Before Calculating PCB Aspect Ratio?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>You need two calculation inputs\u2014plated depth and reference diameter\u2014plus the geometry and tolerances required to validate the result.<\/strong> Take them from the released stackup, drill chart and fabrication drawing.<\/p>\n<ul>\n<li><strong>Depth:<\/strong> Use finished board thickness for through holes, drilled sub-lamination thickness for buried vias, and the actual start-to-stop span for blind vias.<\/li>\n<li><strong>Diameter:<\/strong> Record nominal drill size and finished-hole size separately; identify which value the fabricator uses for its limit.<\/li>\n<li><strong>Padstack:<\/strong> Record pad and antipad diameters, required annular ring, and capture\/target pads for microvias.<\/li>\n<li><strong>Tolerances:<\/strong> Include maximum plated depth, minimum permitted reference diameter and drill-position tolerance.<\/li>\n<li><strong>Process:<\/strong> Identify mechanical drilling, controlled-depth drilling or laser drilling and the applicable supplier limit.<\/li>\n<\/ul>\n<p><strong>Create one row per via family:<\/strong> start\/stop layers, drill method, nominal\/maximum depth, nominal\/minimum reference diameter, finished-hole requirement, pad diameter and process limit. If \u201ctool size\u201d and \u201cfinished hole\u201d are identical without a plating allowance, clarify the data before calculating.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"What_Is_the_PCB_Aspect_Ratio_Formula_and_How_Do_You_Apply_It_to_Different_Via_Types\"><\/span>What Is the PCB Aspect Ratio Formula, and How Do You Apply It to Different Via Types?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>PCB Aspect Ratio = plated hole depth \u00f7 reference diameter.<\/strong><\/p>\n<ul>\n<li><strong>Mechanical holes:<\/strong> Use the nominal drill-tool diameter unless the fabricator explicitly defines the limit by finished-hole diameter.<\/li>\n<li><strong>Laser microvias:<\/strong> Use capture-to-target depth and the fabricator-defined diameter measurement point because the hole is tapered.<\/li>\n<\/ul>\n<ul>\n<li><strong>Through-hole example:<\/strong> A 1.60 mm board drilled with a 0.25 mm tool gives 1.60 \u00f7 0.25 = <strong>6.4:1<\/strong>.<\/li>\n<li><strong>Buried mechanical-via example:<\/strong> A 0.80 mm drilled sub-lamination with a 0.20 mm tool gives 0.80 \u00f7 0.20 = <strong>4:1<\/strong>. Use the drilled sub-lamination thickness, not the final board thickness.<\/li>\n<li><strong>Laser-microvia example:<\/strong> A 0.075 mm capture-to-target depth divided by a supplier-defined 0.10 mm diameter gives <strong>0.75:1<\/strong>. This is below the IPC-T-50M microvia maximum of 1:1, but the actual diameter convention and production limit still require fabrication approval.<\/li>\n<\/ul>\n<p class=\"article-image\" style=\"text-align:center;margin:1.5rem auto;\"><img src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/07\/pcb-aspect-ratio-formula.jpg\" alt=\"PCB via aspect ratio dimensions showing plated hole depth and hole diameter\" width=\"600\" height=\"400\" style=\"display:block;width:100%;max-width:600px;height:auto;margin:0 auto;\" class=\"aligncenter size-full\" loading=\"lazy\" decoding=\"async\"><\/p>\n<p><strong>Compare each result with the supplier limit for that drill process and stackup.<\/strong><\/p>\n<h2><span class=\"ez-toc-section\" id=\"Should_You_Use_Drill_Size_or_Finished_Hole_Size_in_the_Calculation\"><\/span>Should You Use Drill Size or Finished Hole Size in the Calculation?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Use the diameter specified in the fabricator\u2019s aspect-ratio convention.<\/strong> Drill size and finished-hole size are not interchangeable because barrel copper reduces the opening.<\/p>\n<ul>\n<li><strong>Mechanical vias:<\/strong> Use nominal drill-tool diameter when the supplier\u2019s capability is defined before plating.<\/li>\n<li><strong>Finished component holes:<\/strong> Control the finished opening for lead or press-fit fit, but calculate ratio with that value only if the supplier explicitly requires it.<\/li>\n<li><strong>Laser microvias:<\/strong> Confirm whether the stated diameter is measured at the capture side, target side or after plating.<\/li>\n<\/ul>\n<p>For component holes, start with the required finished opening and obtain the supplier\u2019s drill allowance. For signal vias, start with an available drill tool and verify the finished range. <strong>Show both dimensions in the drill chart and label the ratio reference.<\/strong><\/p>\n<h2><span class=\"ez-toc-section\" id=\"How_Do_You_Calculate_the_Minimum_Via_Hole_Size_for_a_Given_Board_Thickness\"><\/span>How Do You Calculate the Minimum Via Hole Size for a Given Board Thickness?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Divide drilled depth by the maximum approved ratio to obtain the theoretical minimum reference diameter.<\/strong> Then select an available drill that also meets finished-hole size, plating allowance and tolerance.<\/p>\n<p><strong>Theoretical minimum reference diameter = drilled depth \u00f7 maximum approved aspect ratio<\/strong><\/p>\n<p>For a 1.60 mm board limited to 8:1, the theoretical drill is 1.60 \u00f7 8 = <strong>0.20 mm<\/strong>. This is not a 0.20 mm finished hole because plating reduces the opening. The BestPCBS capability workbook lists 0.20 mm as the standard minimum finished hole, so the production drill must include plating and process allowance. A 0.25 mm drill gives 6.4:1; confirm its finished range with the fabricator.<\/p>\n<p>For a 0.30 mm partial-depth mechanical via, use 0.30 mm\u2014not total board thickness. For a laser microvia, use supplier-defined depth and diameter. Check the selected tool against the <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/06\/pcb-drill-sizes\/\">PCB drill size guide<\/a> and supplier DFM.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"What_Are_the_Typical_PCB_Aspect_Ratio_Limits_for_Different_Via_Types\"><\/span>What Are the Typical PCB Aspect Ratio Limits for Different Via Types?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Aspect-ratio limits depend on drill method and plated depth.<\/strong> Use these values for screening and obtain supplier approval for the final stackup.<\/p>\n<figure class=\"wp-block-table\" style=\"max-width:100%;overflow-x:auto;\">\n<table>\n<tbody>\n<tr>\n<td><strong>Via type<\/strong><\/td>\n<td><strong>Depth used<\/strong><\/td>\n<td><strong>Practical screening point<\/strong><\/td>\n<td><strong>Required check<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Plated through hole<\/td>\n<td>Finished board thickness<\/td>\n<td>6:1 to 8:1 is a common conservative starting range<\/td>\n<td>Confirm drill convention, plating and board-thickness tolerance<\/td>\n<\/tr>\n<tr>\n<td>Mechanical blind or buried via<\/td>\n<td>Actual connected layer span<\/td>\n<td>Supplier-specific; keep the span as short as the design permits<\/td>\n<td>Confirm sequential lamination and drill access<\/td>\n<\/tr>\n<tr>\n<td>Laser microvia<\/td>\n<td>Dielectric depth between adjacent layers<\/td>\n<td>1:1 or lower; lower ratios provide more process margin<\/td>\n<td>Confirm target pad, capture pad, stacking and fill requirements<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<p><a href=\"https:\/\/www.bestpcbs.com\/\">EBest Circuit<\/a> lists maximum through-hole <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-aspect-ratio\/\">PCB Aspect Ratio<\/a> values of <strong>8:1 standard and 10:1 advanced<\/strong>, with minimum finished holes of 0.20 mm and 0.15 mm respectively. The 10:1 option requires project review.<\/p>\n<p><strong>Treat the maximum as a rejection threshold, not a design target.<\/strong> Near-limit designs require a tolerance and plating review plus confirmation that a larger standard drill cannot provide safer margin. Never apply a through-hole limit to blind, buried, stacked or laser-drilled structures.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"How_Do_Board_Thickness_Layer_Count_and_Stackup_Affect_Via_Size\"><\/span>How Do Board Thickness, Layer Count and Stackup Affect Via Size?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Board thickness directly raises a through-hole ratio; layer count matters only when it changes thickness, registration or the via span.<\/strong> A 0.20 mm drill gives 6:1 in a 1.20 mm board but 10:1 in a 2.00 mm board.<\/p>\n<ul>\n<li><strong>Through vias:<\/strong> Use finished board thickness and enlarge the drill if added thickness exceeds the approved ratio.<\/li>\n<li><strong>Blind vias:<\/strong> Recalculate whenever the stop layer moves.<\/li>\n<li><strong>Buried vias:<\/strong> Use the drilled sub-lamination thickness, not the final board.<\/li>\n<li><strong>Microvias:<\/strong> Check each buildup dielectric and its capture\/target pad geometry separately.<\/li>\n<\/ul>\n<p><strong>Freeze the stackup before final padstack approval.<\/strong> Recalculate after changes to finished thickness, dielectric spacing, copper weight or start\/stop layers, then recheck pads, antipads and routing clearance.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"How_Do_Pad_Diameter_Annular_Ring_and_Hole_Tolerance_Affect_Final_Via_Size\"><\/span>How Do Pad Diameter, Annular Ring and Hole Tolerance Affect Final Via Size?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>A via passes only when enough copper remains around the worst-case hole after diameter and registration tolerances.<\/strong><\/p>\n<p><strong>Nominal annular ring = (pad diameter \u2212 hole diameter) \u00f7 2<\/strong><\/p>\n<p>A 0.60 mm pad around a 0.30 mm hole gives a nominal 0.15 mm ring. Maximum hole size and drill shift reduce the remaining copper, so apply the fabricator\u2019s acceptance method instead of subtracting assumed tolerances.<\/p>\n<ul>\n<li><strong>Hole enlargement:<\/strong> Increase the pad until the worst-case remaining annular ring meets the fabrication requirement.<\/li>\n<li><strong>Clearance:<\/strong> Recheck antipads, planes and routing space after changing the padstack.<\/li>\n<li><strong>Layer review:<\/strong> Verify capture pads on every connected layer and the rule for nonfunctional-pad removal.<\/li>\n<li><strong>Component holes:<\/strong> Keep press-fit and leaded-hole tolerances separate from ordinary signal vias.<\/li>\n<\/ul>\n<h2><span class=\"ez-toc-section\" id=\"How_Do_Copper_Plating_and_Reliability_Requirements_Affect_Via_Size_Selection\"><\/span>How Do Copper Plating and Reliability Requirements Affect Via Size Selection?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Reliability requirements may require a larger hole than the mathematical minimum because the barrel center is the hardest area to plate uniformly.<\/strong> Thin center-wall copper concentrates strain during assembly and thermal cycling.<\/p>\n<p class=\"article-image\" style=\"text-align:center;margin:1.5rem auto;\"><img src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/07\/pcb-via-microsection-inspection.jpg\" alt=\"PCB plated through-hole microsection inspection for copper thickness and barrel quality\" width=\"600\" height=\"400\" style=\"display:block;width:100%;max-width:600px;height:auto;margin:0 auto;\" class=\"aligncenter size-full\" loading=\"lazy\" decoding=\"async\"><\/p>\n<ul>\n<li><strong>Copper requirement:<\/strong> Define measurable finished barrel copper and the applicable acceptance class.<\/li>\n<li><strong>Risk factors:<\/strong> Add margin for thick boards, small drills, heavy copper and repeated thermal excursions.<\/li>\n<li><strong>Evidence:<\/strong> Specify coupon sampling, microsection locations, electrical test and required thermal stress.<\/li>\n<li><strong>Material system:<\/strong> Consider laminate z-axis expansion, resin system and assembly temperature with the ratio.<\/li>\n<\/ul>\n<p><strong>A microsection proves only the sampled location.<\/strong> Use it to inspect barrel-center copper, voids and interconnection quality, then combine it with the sampling plan, electrical testing and required thermal qualification. Requalify after a material, thickness or via-geometry change.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"When_Should_You_Choose_Through-Hole_Blind_Buried_or_Microvias\"><\/span>When Should You Choose Through-Hole, Blind, Buried or Microvias?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Use the least complex via that meets the required layer connection, routing density and signal-integrity target.<\/strong> Start with through holes; add blind, buried or microvias only when they solve a specific constraint.<\/p>\n<ul>\n<li><strong>Through hole:<\/strong> Preferred when its pad and antipad fit, inner routing remains open and the unused barrel does not create an unacceptable high-speed stub. Ratio depth is the full board thickness.<\/li>\n<li><strong>Blind via:<\/strong> Connects an outer layer to selected inner layers, preserving deeper routing channels. Confirm controlled depth, mechanical drill access and sequential-lamination impact.<\/li>\n<li><strong>Buried via:<\/strong> Connects only internal layers without using outer-layer space. Calculate from the drilled sub-lamination and justify the added lamination and inspection steps.<\/li>\n<li><strong>Laser microvia:<\/strong> Best for adjacent-layer, fine-pitch HDI escape where a mechanical pad will not fit. Define capture\/target pads, staggered or stacked construction, fill and cap requirements.<\/li>\n<\/ul>\n<p><strong>Before release, check pad\/antipad fit, stub length, layer access, lamination cycles, fill\/cap needs and inspection cost.<\/strong> Confirm the structure against the <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-via-types\/\">PCB via types guide<\/a> and supplier DFM before routing is frozen.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"How_Can_You_Check_PCB_Aspect_Ratio_and_Via_Size_During_DFM_Review\"><\/span>How Can You Check PCB Aspect Ratio and Via Size During DFM Review?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>DFM must calculate the PCB Aspect Ratio for every unique via family\u2014not only the smallest hole\u2014and record a Pass, Revise or Supplier Review disposition.<\/strong><\/p>\n<ol>\n<li><strong>Freeze inputs:<\/strong> Use matching revisions of stackup, Gerber\/ODB++, NC drill files, fabrication drawing and drill chart; stop if thickness, layer numbers or hole values conflict.<\/li>\n<li><strong>Group via families:<\/strong> Separate by drill method, start\/stop layers, tool diameter, finished-hole requirement, plating status and tolerance.<\/li>\n<li><strong>Confirm conventions:<\/strong> Record drill and finished diameters separately and define the laser-microvia measurement point.<\/li>\n<li><strong>Calculate both cases:<\/strong> Nominal ratio uses nominal depth\/diameter; conservative ratio uses maximum depth\/minimum reference diameter when supplier tolerances are available.<\/li>\n<li><strong>Check padstack:<\/strong> Verify remaining annular ring, capture\/target pads, antipads, copper spacing and solder-mask treatment after any hole change.<\/li>\n<li><strong>Check process:<\/strong> Identify sequential lamination, fill, copper cap, backdrill, plating, coupons and thermal-stress requirements.<\/li>\n<li><strong>Close disposition:<\/strong> Pass only when ratio, geometry and process all pass; otherwise revise the design or retain written supplier approval.<\/li>\n<\/ol>\n<p>Example: 1.60 mm depth \u00f7 0.25 mm drill = <strong>6.4:1 nominal<\/strong>. If supplier-defined limits are 1.68 mm maximum depth and 0.24 mm minimum diameter, the conservative value is <strong>7.0:1<\/strong>. Record both values, the applicable limit and disposition; recalculate after any stackup or drill change.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Which_Via_Sizing_Mistakes_Increase_Cost_or_Cause_Fabrication_Defects\"><\/span>Which Via Sizing Mistakes Increase Cost or Cause Fabrication Defects?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Incomplete drill definitions and calculations made without tolerance margin cause avoidable tooling, lamination and redesign costs.<\/strong><\/p>\n<figure class=\"wp-block-table\" style=\"max-width:100%;overflow-x:auto;\">\n<table>\n<tbody>\n<tr>\n<td><strong>Mistake<\/strong><\/td>\n<td><strong>Likely consequence<\/strong><\/td>\n<td><strong>Practical correction<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Using finished hole in one file and drill tool in another<\/td>\n<td>Conflicting ratio, tolerance and quote assumptions<\/td>\n<td>Show both values and identify the calculation convention<\/td>\n<\/tr>\n<tr>\n<td>Calculating blind vias from total board thickness<\/td>\n<td>Incorrect rejection or an unnecessarily large via<\/td>\n<td>Use the actual start-to-stop layer depth<\/td>\n<\/tr>\n<tr>\n<td>Selecting the mathematical minimum without margin<\/td>\n<td>Lower yield and tighter process control<\/td>\n<td>Choose a larger standard drill where routing permits<\/td>\n<\/tr>\n<tr>\n<td>Enlarging the hole but not the pad<\/td>\n<td>Reduced annular ring or breakout<\/td>\n<td>Recalculate pad, clearance and registration margin together<\/td>\n<\/tr>\n<tr>\n<td>Stacking microvias without supplier approval<\/td>\n<td>Extra process steps and reliability risk<\/td>\n<td>Confirm stacking, filling and qualification before layout release<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<p><strong>Correct the geometry before requesting tighter tolerances.<\/strong> Compare a larger drill, shorter span, larger pad and simpler via structure. Blind\/buried vias add lamination cost; stacked microvias may add filling, planarization, copper capping and qualification.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"What_Via_Specifications_and_PCB_Files_Should_You_Send_for_Manufacturing_Review\"><\/span>What Via Specifications and PCB Files Should You Send for Manufacturing Review?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Send matching-revision fabrication data, drill data, stackup and acceptance requirements.<\/strong><\/p>\n<ul>\n<li><strong>Fabrication data:<\/strong> Gerber or ODB++ files with matching revision identifiers.<\/li>\n<li><strong>Drill data:<\/strong> NC drill files, drill map and a chart separating tool size, finished size, plated status and tolerance.<\/li>\n<li><strong>Stackup:<\/strong> Finished thickness, materials, copper weights and the depth of every blind or buried span.<\/li>\n<li><strong>Via construction:<\/strong> Start\/stop layers, stacked or staggered arrangement, fill, cap, tent and backdrill requirements.<\/li>\n<li><strong>Acceptance:<\/strong> Product class, plating requirement, impedance, coupon, microsection and electrical-test needs.<\/li>\n<li><strong>Commercial context:<\/strong> Prototype and production quantities, forecast, delivery target and any approved alternative.<\/li>\n<\/ul>\n<p><strong>Add one calculation row per via family:<\/strong> ID, drill method, start\/stop layers, depth, nominal tool or microvia diameter, finished-hole requirement\/tolerance, pad diameter, fill\/cap\/tent or backdrill requirement, calculated ratio and capability limit. Label every value as nominal, minimum, maximum or finished.<\/p>\n<p>If DFM changes a drill or layer span, regenerate the affected files. Obtain written approval for accepted via families and exceptions before production release.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"FAQs_About_PCB_Aspect_Ratio\"><\/span>FAQs About PCB Aspect Ratio<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Q1: Does backdrilling change the original plated-through-hole aspect ratio?<\/strong><\/p>\n<p>A1: <strong>Backdrilling removes an unused barrel section after the through hole has been drilled and plated, so it does not change the original plating challenge.<\/strong> Specify backdrill depth, residual stub and clearance separately.<\/p>\n<p><strong>Q2: Does controlled impedance set the allowable aspect ratio?<\/strong><\/p>\n<p>A2: No. <strong>Controlled impedance governs transmission-line geometry, while the allowable ratio is a hole-manufacturing limit.<\/strong> Via diameter, pad, antipad and stub length can affect impedance and must be modeled separately.<\/p>\n<p><strong>Q3: Do non-plated holes have a PCB via aspect ratio?<\/strong><\/p>\n<p>A3: A depth-to-diameter ratio can be calculated, but <strong>the plating-related via limit does not apply in the same way to an NPTH.<\/strong> Mechanical drilling capability, positional tolerance and tool access still need review.<\/p>\n<p><strong>Q4: How is aspect ratio handled for plated slots?<\/strong><\/p>\n<p>A4: <strong>Use the plated depth and the slot&#8217;s controlling narrow dimension, then confirm the supplier&#8217;s routing and plating rule.<\/strong> End radius, slot width, tolerance and copper coverage also affect approval.<\/p>\n<p><strong>Q5: Does via filling change the calculated ratio?<\/strong><\/p>\n<p>A5: No. <strong>Filling occurs after the hole is formed and plated, so it does not change the original depth-to-diameter calculation.<\/strong> It does add material, process and planarization requirements that need separate DFM checks.<\/p>\n<p><strong>Q6: Should press-fit component holes use the same diameter strategy as signal vias?<\/strong><\/p>\n<p>A6: No. <strong>Press-fit holes are sized around the component pin and finished-hole tolerance, not routing density.<\/strong> Confirm the compliant-pin specification, plating build and insertion-force requirements before selecting the drill.<\/p>\n<p><strong>Q7: Does a lower ratio always improve electrical performance?<\/strong><\/p>\n<p>A7: Not necessarily. <strong>A lower ratio generally improves plating access, but electrical behavior depends on via length, diameter, pad and antipad geometry, stub length and return path.<\/strong> Evaluate high-speed performance separately.<\/p>\n<p><strong>Q8: Can aspect ratio alone predict conductive anodic filament risk?<\/strong><\/p>\n<p>A8: No. <strong>CAF risk also depends on material system, spacing, moisture, voltage, drilling damage and processing cleanliness.<\/strong> Treat it as a separate material and reliability assessment.<\/p>\n<p><strong>Q9: Does via tenting affect PCB Aspect Ratio?<\/strong><\/p>\n<p>A9: No. <strong>Solder-mask tenting covers the via opening but does not change the drilled depth or diameter.<\/strong> Tenting may affect assembly protection, outgassing and inspection, so specify it independently.<\/p>\n<p><strong>Q10: Can aspect ratio determine how much current a via carries?<\/strong><\/p>\n<p>A10: No. <strong>Current capacity depends mainly on finished barrel copper, hole geometry, temperature rise and the connected copper features.<\/strong> Aspect ratio helps assess manufacturability but cannot replace an electrical and thermal calculation.<\/p>\n<p><strong>Need a project-specific via check?<\/strong> Send your Gerber or ODB++ package, NC drill files, controlled stackup, target quantity and via table to <a href=\"mailto:sales@bestpcbs.com\">sales@bestpcbs.com<\/a>. EBest Circuit can review the proposed PCB Aspect Ratio, hole convention, annular ring and via structure before quotation.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Learn how to calculate PCB Aspect Ratio, select a practical via size, check drilled versus finished hole diameter, and prepare reliable PCB fabrication data.<\/p>\n","protected":false},"author":33247,"featured_media":32136,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_uf_show_specific_survey":0,"_uf_disable_surveys":false,"footnotes":""},"categories":[175,174,4380],"tags":[7148,7147,7145,7146],"class_list":["post-32139","post","type-post","status-publish","format-standard","hentry","category-best-pcb","category-bestpcb","category-pcb-manufacturing","tag-aspect-ratio-in-pcb-manufacturing","tag-pcb-aspect-ratio-example","tag-pcb-aspect-ratio-formula","tag-standard-pcb-aspect-ratio"],"acf":[],"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/posts\/32139","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/users\/33247"}],"replies":[{"embeddable":true,"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/comments?post=32139"}],"version-history":[{"count":2,"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/posts\/32139\/revisions"}],"predecessor-version":[{"id":32142,"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/posts\/32139\/revisions\/32142"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/media\/32136"}],"wp:attachment":[{"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/media?parent=32139"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/categories?post=32139"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/tags?post=32139"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}