{"id":31957,"date":"2026-07-22T18:39:41","date_gmt":"2026-07-22T10:39:41","guid":{"rendered":"https:\/\/www.bestpcbs.com\/blog\/?p=31957"},"modified":"2026-07-22T18:39:43","modified_gmt":"2026-07-22T10:39:43","slug":"pcb-traces","status":"publish","type":"post","link":"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-traces\/","title":{"rendered":"PCB Traces: Types, Design Rules, Width, Current &#038; Repair"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_84 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-traces\/#What_Are_Traces_on_a_PCB\" >What Are Traces on a PCB?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-traces\/#PCB_Trace_Material_and_Copper_Thickness\" >PCB Trace Material and Copper Thickness<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-traces\/#Types_of_PCB_Traces\" >Types of PCB Traces<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-traces\/#How_Are_PCB_Traces_Made\" >How Are PCB Traces Made?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-traces\/#What_Are_the_Differences_Between_PCB_Traces_and_Vias\" >What Are the Differences Between PCB Traces and Vias?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-traces\/#How_to_Read_PCB_Traces\" >How to Read PCB Traces?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-traces\/#PCB_Trace_Design_Rules\" >PCB Trace Design Rules<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-traces\/#How_Wide_Should_PCB_Traces_Be\" >How Wide Should PCB Traces Be?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-traces\/#How_to_Calculate_Current_Capacity_of_PCB_Traces\" >How to Calculate Current Capacity of PCB Traces?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-traces\/#Why_Are_PCB_Traces_45_Degrees\" >Why Are PCB Traces 45 Degrees?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-11\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-traces\/#How_to_Repair_PCB_Traces\" >How to Repair PCB Traces?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-12\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-traces\/#FAQ_About_PCB_Traces\" >FAQ About PCB Traces<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-13\" href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-traces\/#How_Can_EBest_Circuit_Support_Your_PCB_Trace_Requirements\" >How Can EBest Circuit Support Your PCB Trace Requirements?<\/a><\/li><\/ul><\/nav><\/div>\n<div class=\"yzp-no-index\"><\/div><p><a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/07\/pcb-traces\/\">pcb traces<\/a> are the copper paths that connect component pads, vias, connectors and test points. A useful trace design must satisfy <strong>fabrication limits, electrical clearance, current capacity and signal requirements<\/strong>.<\/p>\n<p>This guide shows how to recognize a trace, select practical design rules and check a damaged route. It also includes <strong>our complete FR4 line width and spacing table<\/strong> for different copper weights.<\/p>\n<figure style=\"max-width:600px;margin:24px auto;text-align:center;\">\n    <img fetchpriority=\"high\" decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/07\/pcb-traces.jpg\" alt=\"PCB Traces shown as copper paths connecting pads and vias on a multilayer circuit board\" width=\"1200\" height=\"800\" loading=\"eager\" style=\"width:100%;max-width:600px;max-height:400px;height:auto;object-fit:contain;\"><br \/>\n  <\/figure>\n<section>\n<h2><span class=\"ez-toc-section\" id=\"What_Are_Traces_on_a_PCB\"><\/span>What Are Traces on a PCB?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>A PCB trace is a patterned copper conductor that carries a signal or supply current between two electrical nodes. On an outer layer, the trace usually appears as a narrow path beneath the solder mask. Its exposed ends become pads for soldering, probing or connection.<\/p>\n<p>Four dimensions define the physical conductor:<\/p>\n<ul>\n<li><strong>Trace width<\/strong> is the horizontal width of one copper path.<\/li>\n<li><strong>Trace spacing<\/strong> is the copper-to-copper gap between neighboring features.<\/li>\n<li><strong>Copper thickness<\/strong> is the vertical thickness of the conductor.<\/li>\n<li><strong>Trace length<\/strong> is the routed distance between its endpoints.<\/li>\n<\/ul>\n<p>Width and thickness determine the copper cross-section. Length then affects resistance, voltage drop and signal delay. This is why two traces that look similar may perform differently.<\/p>\n<\/section>\n<section>\n<h2><span class=\"ez-toc-section\" id=\"PCB_Trace_Material_and_Copper_Thickness\"><\/span>PCB Trace Material and Copper Thickness<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>PCB trace material is normally electrodeposited or rolled copper. The following table converts the most common nominal copper weights into thickness.<\/p>\n<div class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Copper Weight<\/strong><\/td>\n<td><strong>Nominal Thickness<\/strong><\/td>\n<\/tr>\n<tr>\n<td>0.5 oz<\/td>\n<td>Approximately 17 \u00b5m<\/td>\n<\/tr>\n<tr>\n<td>1 oz<\/td>\n<td>Approximately 35 \u00b5m<\/td>\n<\/tr>\n<tr>\n<td>2 oz<\/td>\n<td>Approximately 70 \u00b5m<\/td>\n<\/tr>\n<tr>\n<td>3 oz<\/td>\n<td>Approximately 105 \u00b5m<\/td>\n<\/tr>\n<\/tbody>\n<\/table><\/div>\n<p>These figures describe nominal foil thickness, not a guaranteed finished measurement at every point. Outer-layer plating adds copper, while etching changes the sidewalls and finished width. The fabrication drawing should therefore state the required finished copper when that value controls current or impedance.<\/p>\n<p>For FR4 boards, our standard range is <strong>0.5\u20135 oz for inner copper<\/strong> and <strong>1\u20135 oz for outer copper<\/strong>. Special processes extend both inner and outer copper to <strong>20 oz<\/strong>. Heavier copper needs wider spacing because deeper etching makes fine conductors harder to hold.<\/p>\n<\/section>\n<section>\n<h2><span class=\"ez-toc-section\" id=\"Types_of_PCB_Traces\"><\/span>Types of PCB Traces<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Types of PCB traces are separated by electrical function, because each function creates a different design priority. The same minimum fabrication rule should not be used blindly for every net.<\/p>\n<div class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Trace Type<\/strong><\/td>\n<td><strong>Design Priority<\/strong><\/td>\n<td><strong>Primary Check<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Ordinary signal trace<\/td>\n<td>Reliable connection and practical routing<\/td>\n<td>Width, spacing and continuity<\/td>\n<\/tr>\n<tr>\n<td>Power trace<\/td>\n<td>Low resistance and controlled heating<\/td>\n<td>Current, voltage drop and neck-down width<\/td>\n<\/tr>\n<tr>\n<td>Differential pair<\/td>\n<td>Matched propagation and coupling<\/td>\n<td>Pair width, gap and length mismatch<\/td>\n<\/tr>\n<tr>\n<td>Controlled-impedance trace<\/td>\n<td>Target transmission impedance<\/td>\n<td>Stackup, width and reference plane<\/td>\n<\/tr>\n<tr>\n<td>RF trace<\/td>\n<td>Low discontinuity and predictable return current<\/td>\n<td>Geometry, transitions and ground reference<\/td>\n<\/tr>\n<\/tbody>\n<\/table><\/div>\n<p>A route can belong to more than one group. A high-speed differential pair is also a controlled-impedance structure, so changing its width or pair gap after routing changes the electrical result.<\/p>\n<figure style=\"max-width:600px;margin:24px auto;text-align:center;\">\n      <img decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/07\/types-of-pcb-traces.jpg\" alt=\"Types of PCB Traces including signal, power, differential pair and controlled-impedance routes\" width=\"1200\" height=\"800\" loading=\"lazy\" style=\"width:100%;max-width:600px;max-height:400px;height:auto;object-fit:contain;\"><br \/>\n    <\/figure>\n<\/section>\n<section>\n<h2><span class=\"ez-toc-section\" id=\"How_Are_PCB_Traces_Made\"><\/span>How Are PCB Traces Made?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>PCB traces are made by transferring the circuit image to copper-clad laminate and etching away the unwanted copper. The finished geometry comes from the artwork, copper thickness and process compensation used by the fabricator.<\/p>\n<ol>\n<li><strong>Clean and coat the copper.<\/strong> A photosensitive resist is applied to the copper surface.<\/li>\n<li><strong>Image the circuit.<\/strong> Film exposure or laser direct imaging defines the tracks, pads and clearances.<\/li>\n<li><strong>Develop and etch.<\/strong> The process protects wanted copper and removes the open areas.<\/li>\n<li><strong>Inspect the pattern.<\/strong> AOI compares the etched conductors with the production data and finds opens, shorts or damaged features.<\/li>\n<li><strong>Build and test the board.<\/strong> Inner layers are laminated, outer layers are processed, and electrical testing verifies continuity and isolation.<\/li>\n<\/ol>\n<p>Etching does not produce perfectly vertical copper walls. Thick copper needs more lateral etch compensation, which explains why the minimum line and space increase as copper weight rises.<\/p>\n<\/section>\n<section>\n<h2><span class=\"ez-toc-section\" id=\"What_Are_the_Differences_Between_PCB_Traces_and_Vias\"><\/span>What Are the Differences Between PCB Traces and Vias?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>PCB traces carry a connection across one copper layer, while vias carry it vertically between layers. A trace is an etched horizontal conductor; a via is a plated hole with pads on the layers it connects.<\/p>\n<p>The two features work together when a net changes layers. We support <strong>0.10 mm laser blind or buried vias<\/strong>. Our minimum finished mechanical hole is <strong>0.20 mm for standard processing<\/strong> and <strong>0.15 mm for special processing<\/strong>. The maximum through-hole aspect ratio is <strong>8:1 standard<\/strong> and <strong>10:1 special<\/strong>.<\/p>\n<p>One small via should not become the narrowest point in a high-current path. Use enough via copper for the required current and place return vias near high-speed layer transitions. A signal via without a nearby return path forces return current to take a longer route, increasing loop area and discontinuity.<\/p>\n<\/section>\n<section>\n<h2><span class=\"ez-toc-section\" id=\"How_to_Read_PCB_Traces\"><\/span>How to Read PCB Traces?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>To read PCB traces, begin at a known pad and follow the same copper path until it reaches another pad, a via or a plane. Work on an unpowered board and use the schematic or PCB files whenever they are available.<\/p>\n<ol>\n<li>Identify the component reference and pin number.<\/li>\n<li>Follow the visible route under good lighting or magnification.<\/li>\n<li>Mark every via where the route may change layers.<\/li>\n<li>Use continuity mode to confirm suspected endpoints.<\/li>\n<li>Compare the result with the schematic net instead of relying only on appearance.<\/li>\n<\/ol>\n<p>Ground pours and internal planes can make many points appear connected. Zero-ohm resistors can also look like ordinary components while acting as routing links. Recording each confirmed point prevents repeated probing and accidental pad damage.<\/p>\n<\/section>\n<section>\n<h2><span class=\"ez-toc-section\" id=\"PCB_Trace_Design_Rules\"><\/span>PCB Trace Design Rules<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>PCB trace design rules should convert the stackup and fabrication capability into constraints that the layout software can check. A useful rule set separates ordinary signals, power nets, controlled-impedance routes and high-voltage circuits.<\/p>\n<p>Set these values before detailed routing:<\/p>\n<ul>\n<li>Minimum trace width and copper spacing for each layer and copper weight.<\/li>\n<li>Electrical clearance based on working voltage and the applicable safety requirement.<\/li>\n<li>Via diameter, finished hole, annular ring and allowed via structures.<\/li>\n<li>Differential-pair width, gap and permitted length mismatch.<\/li>\n<li>Controlled-impedance geometry from the confirmed production stackup.<\/li>\n<li>Wider neck-down limits for pads, connectors and high-current transitions.<\/li>\n<\/ul>\n<p>A <a href=\"https:\/\/www.bestpcbs.com\/blog\/2026\/04\/what-is-design-rule-check-drc-in-pcb-types-of-deisgn-rule-checking\/\"><strong>PCB design rule check<\/strong><\/a> finds violations of the entered constraints. It cannot correct a wrong rule value, so DRC should follow stackup and capability confirmation rather than replace it.<\/p>\n<\/section>\n<section>\n<h2><span class=\"ez-toc-section\" id=\"How_Wide_Should_PCB_Traces_Be\"><\/span>How Wide Should PCB Traces Be?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>PCB trace width should stay at or above the line\/space value for the selected copper weight, then increase where current, voltage drop or impedance requires it. A <strong>4\/4 mil<\/strong> capability means a minimum 4 mil line beside a minimum 4 mil copper gap.<\/p>\n<p>The table below shows <strong>our complete FR4 line width and spacing data<\/strong>. Standard values are the preferred production limits. Special values require stackup and engineering review before release.<\/p>\n<div class=\"wp-block-table\">\n<table>\n<tbody>\n<tr>\n<td><strong>Layer<\/strong><\/td>\n<td><strong>Copper Weight<\/strong><\/td>\n<td><strong>Standard Line\/Space<\/strong><\/td>\n<td><strong>Special Line\/Space<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Inner<\/td>\n<td>0.5 oz<\/td>\n<td>4\/4 mil<\/td>\n<td>3\/3 mil<\/td>\n<\/tr>\n<tr>\n<td>Inner<\/td>\n<td>1 oz<\/td>\n<td>4\/4 mil<\/td>\n<td>3\/3 mil<\/td>\n<\/tr>\n<tr>\n<td>Inner<\/td>\n<td>2 oz<\/td>\n<td>6\/6 mil<\/td>\n<td>5\/5 mil<\/td>\n<\/tr>\n<tr>\n<td>Inner<\/td>\n<td>3 oz<\/td>\n<td>10\/12 mil<\/td>\n<td>8\/8 mil<\/td>\n<\/tr>\n<tr>\n<td>Inner<\/td>\n<td>4 oz<\/td>\n<td>12\/16 mil<\/td>\n<td>10\/10 mil<\/td>\n<\/tr>\n<tr>\n<td>Inner<\/td>\n<td>5 oz<\/td>\n<td>16\/20 mil<\/td>\n<td>10\/14 mil<\/td>\n<\/tr>\n<tr>\n<td>Inner<\/td>\n<td>6 oz<\/td>\n<td>22\/26 mil<\/td>\n<td>14\/16 mil<\/td>\n<\/tr>\n<tr>\n<td>Inner<\/td>\n<td>10 oz<\/td>\n<td>36\/40 mil<\/td>\n<td>28\/34 mil<\/td>\n<\/tr>\n<tr>\n<td>Inner<\/td>\n<td>20 oz<\/td>\n<td>74\/90 mil<\/td>\n<td>60\/80 mil<\/td>\n<\/tr>\n<tr>\n<td>Outer<\/td>\n<td>1 oz<\/td>\n<td>4\/4 mil<\/td>\n<td>3\/3 mil<\/td>\n<\/tr>\n<tr>\n<td>Outer<\/td>\n<td>1.5 oz<\/td>\n<td>6\/6 mil<\/td>\n<td>4\/4 mil<\/td>\n<\/tr>\n<tr>\n<td>Outer<\/td>\n<td>2 oz<\/td>\n<td>8\/8 mil<\/td>\n<td>6\/6 mil<\/td>\n<\/tr>\n<tr>\n<td>Outer<\/td>\n<td>3 oz<\/td>\n<td>12\/12 mil<\/td>\n<td>9\/9 mil<\/td>\n<\/tr>\n<tr>\n<td>Outer<\/td>\n<td>4 oz<\/td>\n<td>16\/16 mil<\/td>\n<td>12\/12 mil<\/td>\n<\/tr>\n<tr>\n<td>Outer<\/td>\n<td>5 oz<\/td>\n<td>20\/20 mil<\/td>\n<td>15\/15 mil<\/td>\n<\/tr>\n<tr>\n<td>Outer<\/td>\n<td>6 oz<\/td>\n<td>26\/26 mil<\/td>\n<td>20\/20 mil<\/td>\n<\/tr>\n<tr>\n<td>Outer<\/td>\n<td>10 oz<\/td>\n<td>40\/40 mil<\/td>\n<td>32\/32 mil<\/td>\n<\/tr>\n<tr>\n<td>Outer<\/td>\n<td>20 oz<\/td>\n<td>90\/90 mil<\/td>\n<td>70\/70 mil<\/td>\n<\/tr>\n<\/tbody>\n<\/table><\/div>\n<p>Do not choose 3\/3 mil merely because it appears in the special column. Wider spacing improves process margin, especially on heavy copper. Use the smallest value only where routing density makes it necessary.<\/p>\n<figure style=\"max-width:600px;margin:24px auto;text-align:center;\">\n      <img decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/07\/pcb-trace-width-current.jpg\" alt=\"PCB trace width, spacing and copper thickness used to size a current-carrying path\" width=\"1200\" height=\"800\" loading=\"lazy\" style=\"width:100%;max-width:600px;max-height:400px;height:auto;object-fit:contain;\"><br \/>\n    <\/figure>\n<\/section>\n<section>\n<h2><span class=\"ez-toc-section\" id=\"How_to_Calculate_Current_Capacity_of_PCB_Traces\"><\/span>How to Calculate Current Capacity of PCB Traces?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>The current capacity of PCB traces is set by allowable temperature rise, not by a single current-per-mil rule. Use the actual copper thickness, layer position and available cooling when selecting the width.<\/p>\n<p>Start with <a href=\"https:\/\/www.ipc.org\/TOC\/IPC-2152.pdf\">IPC-2152<\/a> conductor-sizing data, then check resistance with <strong>R = \u03c1L\/(w \u00d7 t)<\/strong>. For example, an ideal 100 mm long, 10 mil wide trace in 35 \u00b5m copper is about <strong>0.19 \u03a9<\/strong> at room temperature. At 1 A, that creates about <strong>0.19 V drop and 0.19 W of heat<\/strong> before temperature and process effects are considered.<\/p>\n<p>A complete sizing check follows this order:<\/p>\n<ol>\n<li>Define continuous current, peak current and duty cycle.<\/li>\n<li>Select the allowed trace temperature rise.<\/li>\n<li>Choose width from the correct internal or external conductor condition.<\/li>\n<li>Calculate voltage drop along the complete path.<\/li>\n<li>Verify the prototype at the narrowest and hottest locations.<\/li>\n<\/ol>\n<p>High current PCB traces should use the shortest practical route and enough copper cross-section to control both heat and voltage drop. Increasing width is usually the first step; heavier copper or parallel layers may be needed when board space is limited.<\/p>\n<p>Inspect the entire current path rather than its widest area. The effective bottleneck may be:<\/p>\n<ul>\n<li>A narrow connection entering a component pad.<\/li>\n<li>A thermal relief with thin spokes.<\/li>\n<li>A single via between large copper pours.<\/li>\n<li>A connector pin or fuse footprint with limited copper.<\/li>\n<\/ul>\n<p>The relationship between <a href=\"https:\/\/www.bestpcbs.com\/blog\/2023\/09\/do-you-know-the-relationship-between-copper-thickness-and-circuit-width-spacing\/\">copper thickness and circuit width<\/a> also changes manufacturability. Confirm heavy-copper spacing before final routing, not after the layout is crowded.<\/p>\n<\/section>\n<section>\n<h2><span class=\"ez-toc-section\" id=\"Why_Are_PCB_Traces_45_Degrees\"><\/span>Why Are PCB Traces 45 Degrees?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>PCB traces commonly use <strong>45-degree bends<\/strong> because they produce compact routes without the sharp inside corner of a square turn. They are easy to route consistently and work well for most ordinary digital and analog layouts.<\/p>\n<figure style=\"max-width:600px;margin:24px auto;text-align:center;\">\n      <img decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/07\/pcb-traces-45-degree-callout.jpg\" alt=\"45-degree PCB trace bend identified with a magnified inset, angle arc, yellow circle and red arrow\" width=\"1200\" height=\"800\" loading=\"lazy\" style=\"width:100%;max-width:600px;max-height:400px;height:auto;object-fit:contain;\"><br \/>\n    <\/figure>\n<p><strong>A 90-degree bend does not automatically cause an EMI failure.<\/strong> High-speed performance depends more on impedance continuity and the return path than on the visual angle alone. RF routes may use arcs or mitered bends after calculation, while low-speed traces rarely need that extra geometry.<\/p>\n<\/section>\n<section>\n<h2><span class=\"ez-toc-section\" id=\"How_to_Repair_PCB_Traces\"><\/span>How to Repair PCB Traces?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>To repair PCB traces, remove the failed copper from the load path and bridge the break between two sound conductor points. The board must remain <strong>unpowered until continuity and isolation checks are complete<\/strong>.<\/p>\n<ol>\n<li>Find the original fault before repairing the visible damage.<\/li>\n<li>Remove loose or carbonized material and clean the area.<\/li>\n<li>Expose a short section of clean copper on both sides of the break.<\/li>\n<li>Tin the copper and install a conductor sized for the circuit current.<\/li>\n<li>Anchor the conductor so vibration cannot pull on the repaired pads.<\/li>\n<li>Measure continuity to the endpoints and isolation from adjacent nets.<\/li>\n<\/ol>\n<p>Stop the repair when damage enters a plated hole, internal layer or controlled-impedance route that cannot be verified. Burned laminate must also be removed or professionally evaluated because carbonized material can remain electrically conductive.<\/p>\n<figure style=\"max-width:600px;margin:24px auto;text-align:center;\">\n      <img decoding=\"async\" src=\"https:\/\/www.bestpcbs.com\/blog\/wp-content\/uploads\/2026\/07\/pcb-trace-repair.jpg\" alt=\"PCB trace repair showing damaged copper exposed, bridged, anchored and tested\" width=\"1200\" height=\"800\" loading=\"lazy\" style=\"width:100%;max-width:600px;max-height:400px;height:auto;object-fit:contain;\"><br \/>\n    <\/figure>\n<\/section>\n<section>\n<h2><span class=\"ez-toc-section\" id=\"FAQ_About_PCB_Traces\"><\/span>FAQ About PCB Traces<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<h3>Are PCB traces copper or gold?<\/h3>\n<p>PCB traces are copper. ENIG or another finish may cover exposed pads, but the thin surface finish protects the underlying copper rather than replacing it.<\/p>\n<h3>Can PCB traces cross?<\/h3>\n<p>Two unrelated traces cannot cross on the same copper layer. One route must change layers through vias, use a jumper or take a different path.<\/p>\n<h3>What is the difference between a PCB trace and a track?<\/h3>\n<p>Trace and track normally describe the same copper conductor. The preferred word depends on the region, company or PCB design software.<\/p>\n<h3>Can a PCB trace run under a component?<\/h3>\n<p>Yes, if the trace maintains the required clearance and does not interfere with pads or exposed metal. Sensitive analog and RF layouts may need additional restrictions.<\/p>\n<h3>What happens when a PCB trace is too narrow?<\/h3>\n<p>A narrow power trace has more resistance, voltage drop and heating. A narrow controlled-impedance trace also changes impedance, so the result depends on the net function.<\/p>\n<h3>How do you measure PCB trace width?<\/h3>\n<p>Read the nominal width from the PCB data and inspect the finished conductor with calibrated optical equipment. Manufacturing acceptance must use the agreed tolerance and inspection method.<\/p>\n<h3>What causes a PCB trace to burn?<\/h3>\n<p>Overcurrent, a short circuit or a high-resistance connection can overheat a trace. The fault must be corrected before replacing the damaged conductor.<\/p>\n<h3>Can a repaired trace carry the original current?<\/h3>\n<p>Only when the repair restores enough conductor cross-section and secure attachment. A continuity reading alone does not prove that the repair can carry the original load.<\/p>\n<\/section>\n<section>\n<h2><span class=\"ez-toc-section\" id=\"How_Can_EBest_Circuit_Support_Your_PCB_Trace_Requirements\"><\/span>How Can EBest Circuit Support Your PCB Trace Requirements?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>At EBest Circuit, <strong>we review FR4 trace geometry<\/strong> against the selected copper weight, layer structure, via requirements and production process. We keep standard and special limits separate so each project is evaluated against the correct manufacturing route.<\/p>\n<p>Send your <strong>Gerber or ODB++ files<\/strong>, stackup, finished copper requirements, current information and impedance targets to <a href=\"mailto:sales@bestpcbs.com\">sales@bestpcbs.com<\/a>. Our engineering team will review the data and provide manufacturing feedback with the quotation.<\/p>\n<\/section>\n","protected":false},"excerpt":{"rendered":"<p>Learn how PCB traces are made, read, sized and repaired, with practical design rules and EBest Circuit line width and spacing capabilities.<\/p>\n","protected":false},"author":623,"featured_media":31952,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_uf_show_specific_survey":0,"_uf_disable_surveys":false,"footnotes":""},"categories":[174],"tags":[7078,7080,7079,7076,7077],"class_list":["post-31957","post","type-post","status-publish","format-standard","hentry","category-bestpcb","tag-how-are-pcb-traces-made","tag-how-to-repair-pcb-traces","tag-how-wide-should-pcb-traces-be","tag-pcb-traces","tag-pcb-traces-and-vias"],"acf":[],"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/posts\/31957","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/users\/623"}],"replies":[{"embeddable":true,"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/comments?post=31957"}],"version-history":[{"count":1,"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/posts\/31957\/revisions"}],"predecessor-version":[{"id":32010,"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/posts\/31957\/revisions\/32010"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/media\/31952"}],"wp:attachment":[{"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/media?parent=31957"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/categories?post=31957"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.bestpcbs.com\/blog\/wp-json\/wp\/v2\/tags?post=31957"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}