# Microvia Reliability: Read the Reflow Resistance Trace _Published: 2026-11-10_ Table of Contents Toggle - microvia reliability - stacked vs staggered microvias - pcb daisy chain - pcb reflow profile - microvia failure - pcb microsection analysis - interconnect stress test pcb - pcb thermal cycling test - FAQ - Sources - Project Review Don’t release an HDI lot on the strength of a cold continuity check alone when the purchase requirements call for reflow-monitored resistance. First verify that the coupon reproduces the critical via structure. Then compare its resistance trace with the agreed reference and temperature profile. A chain can read normally after cooling even if it opened during heating. ![Mounted PCB cross-section with copper interconnections and dielectric layers](https://www.bestpcbs.com/blog/wp-content/uploads/2026/11/stacked-vs-staggered-microvias.jpg)Illustrative rendering of a cross-section specimen. Use the actual stack drawing and coupon record to identify via geometry. ## microvia reliability Microvias connect adjacent PCB layers in dense layouts. During soldering, the board expands and contracts, stressing these connections. A room-temperature continuity result answers whether the path conducts at that moment. It does not reveal an interruption that occurs only at elevated temperature. Ask for the evidence that matches the anticipated assembly exposure. ## stacked vs staggered microvias A stacked design places one microvia above another. A staggered design offsets them and joins the paths on a shared layer. When the board uses both, identify which geometry each coupon actually represents. A result from a staggered chain should not be used to approve an unrepresented stacked interface. For routing and construction trade-offs, see the [BestPCBs comparison guide](https://www.bestpcbs.com/blog/2026/09/stacked-vs-staggered-microvias-reliability-hdi-dfm/). **Board feature** **Check on the coupon** Stacked microvias Same layer spans and stacked interface Staggered microvias Correct layer spans and offset pattern Mixed connections Coverage of each structure required for release ## pcb daisy chain A daisy chain connects many via structures in series so that a change anywhere in the path can appear in the resistance record. Ask for the chain ID, layer pairs, structure count and panel-to-coupon relationship. The resulting trace describes the chain, not the resistance or failure location of an individual via. A chain that includes other structures may require fault isolation. ![Bare test coupon and measurement leads on an electronics lab bench](https://www.bestpcbs.com/blog/wp-content/uploads/2026/11/microvia-reliability.jpg)Illustrative rendering of a coupon setup, not a test log or a pass result. ## pcb reflow profile Compare traces only under the approved profile and measurement convention. Record the test method and revision, profile, cycle count, temperature measurement location and reference resistance. For a performance-based evaluation under IPC-TM-650 2.6.27, use the reference and acceptance criteria in the applicable revision and procurement agreement. Do not silently substitute a cold baseline for a specified hot reference. **Report field** **Why it matters** Profile and cycle Matches the specified exposure Resistance in Ω or mΩ Identifies the measured chain and reference Change in % Shows the result at the specified comparison point Temperature and time Locates the event within the cycle ## microvia failure Consider an illustrative chain with a specified hot reference of 0.500 Ω. A comparable point in a later cycle reads 0.530 Ω. The relative rise is (0.530 − 0.500) ÷ 0.500 = 6%. If the project limit were 5%, the reading would exceed it. A normal cold reading afterward does not cancel the event. These values are a worked example, not a test report or a universal limit. Check whether the event is synchronized with temperature and whether other channels show a simultaneous fixture disturbance. Preserve the original trace and reference coupon. When instrumentation remains a plausible cause, use the documented investigation or retest procedure instead of deleting the event or releasing on the final reading alone. ## pcb microsection analysis Use the electrical record to choose where to section. A section can show a physical discontinuity at a sampled interface, but a clean section elsewhere cannot rule out a hot-only failure in the chain. Ask the lab to correlate the section location with the failed net, stack and panel rather than accepting an unlabeled image. ## interconnect stress test pcb Convection reflow simulation reproduces an agreed assembly heat exposure. DC current-induced thermal cycling is a different test method with a different heating mechanism and protocol. Don’t accept one in place of the other simply because both include resistance readings. Match the report to the contracted exposure, specimen and evaluation method. ## pcb thermal cycling test Specify separately any cycling needed to qualify the board for service. A reflow simulation result alone does not establish lifetime under operational temperature changes. For lot release, verify the approved coupon map, profile, complete trace and disposition of any anomalies. If the controlling geometry or hot record is missing, mark the evidence incomplete rather than treating the omission as a pass. ## FAQ ### Is the final resistance value enough? No when the requirement covers behavior during the cycle. Inspect the agreed measurement interval and preserve any anomalous excursion. ### Can an unmarked coupon represent every panel? Not without documented traceability and an agreed sampling plan. Link its identity to the appropriate panel, lot and build. ### Does a resistance excursion prove a microvia crack? No. It locates a suspect time and chain. Check the test setup and use targeted failure analysis before assigning a cause. ### Can I compare two chains with different numbers of vias directly? Not by raw resistance alone. Geometry and chain length affect the value. Use the prescribed baseline and compare equivalent structures where possible. ### Does a passed stacked coupon qualify a deeper stack? Not automatically. Additional interfaces and different layers can change the behavior. Confirm that the evidence represents the intended construction. ### Does the oven setpoint equal coupon temperature? No. Confirm the recorded measurement convention and coupon temperature rather than assuming the displayed setting is the specimen profile. ### Can I approve the lot if the report only says pass? Only if that is sufficient under the agreement. When the purchase requires traces, conditions or specimen details, request the missing evidence before release. ### What should I retain for a repeat order? Keep the approved stack, coupon ID and drawing, reference convention, test profile, original records and disposition together with the production revision. ## Sources [IPC-TM-650 2.6.27B: convection reflow assembly simulation](https://www.ipc.org/sites/default/files/test_methods_docs/2.6.27b.pdf); [IPC-TM-650 2.6.26A: DC current-induced thermal cycling](https://www.ipc.org/sites/default/files/test_methods_docs/2-6_2-6-26a.pdf). ## Project Review For a Best Technology fabrication discussion, send the critical via stack, intended assembly exposure and coupon acceptance requirements to [sales@bestpcbs.com](mailto:sales@bestpcbs.com).