# Ethernet PCB Routing Guide: From PHY to RJ45 _Published: 2026-11-11_ Table of Contents Toggle - ethernet pcb routing - ethernet phy pcb design layout checklist - ethernet differential pair impedance - ethernet differential pair length matching - ethernet magnetics layout - rj45 pcb layout - rmii pcb layout guidelines - ethernet pcb routing guidelines - FAQ - References Start Ethernet PCB routing by dividing the interface into two parts: the digital link from the MAC to the PHY, and the cable-facing differential pairs from the PHY toward the RJ45. Get the PHY vendor’s layout guide and the fabricator’s stackup before drawing traces. Route the cable pairs as balanced transmission lines, keep their return paths intact where the design calls for a reference plane, and preserve the isolation boundary specified by the connector and system design. ![Evaluation PCB with an RJ45 connector and nearby Ethernet PHY region](https://www.bestpcbs.com/blog/wp-content/uploads/2026/11/ethernet-pcb-routing.jpg)Illustrative Ethernet board. Use the selected parts and their drawings to verify the actual placement and pinout. ## ethernet pcb routing Assign each net to its electrical interface first. The media access controller (MAC) handles Ethernet frames; the physical-layer transceiver (PHY) converts data into the signals used by the medium. The medium-dependent interface (MDI) is the PHY’s cable-facing side. It is not the MAC interface and does not use the same length-matching rules. Use a hypothetical industrial controller with a 1000BASE-T port as a running example. Its connector sits at the enclosure edge, while a switch-mode regulator competes for nearby space. Moving the PHY close to the connector is useful only if the move also leaves a clean, balanced path and preserves the isolation and protection layout. ## ethernet phy pcb design layout checklist Convert the vendor’s electrical requirements into separate CAD checks before routing. Use the exact PHY and magnetics documentation. For example, Texas Instruments’ SNLA387 uses 100 Ω differential routing for MDI traces; it is not a universal width, spacing, or skew limit. **Design item** **Set from** **Check before release** MDI impedance, Ω PHY guide and stackup Width, gap, layer Intra-pair skew Selected PHY guide Delay and transitions Digital timing MAC and PHY timing Clock and data delays Isolation keepout Parts and system spec Planes and copper ## ethernet differential pair impedance Set differential impedance using the trace width and gap together with copper thickness, dielectric thickness and properties, and the reference layer. Moving an apparently identical pair to a different layer changes that geometry. Ask the fabricator for a matched stackup and obtain approval before substituting material or dielectric thickness. Use an appropriate controlled-impedance coupon where specified; a coupon pass checks its test structure, not every discontinuity on the port. ## ethernet differential pair length matching Check the two conductors of each pair first. Follow the PHY guide for any separate pair-to-pair requirements; do not impose one total-length target on unrelated nets. For illustration, if a stackup gives an assumed effective delay of 6 ps/mm, a 3 mm mismatch corresponds to 18 ps before accounting for different via structures or layers. That is not a pass limit. Compare the actual extracted delay and path geometry against the selected device’s requirements. Fix an asymmetric breakout or transition before adding a long meander. A trace can have the right CAD length and still encounter a different reference plane or more vias than its partner. A small symmetric change is often easier to verify than a large correction near the connector. ## ethernet magnetics layout Choose discrete magnetics or an integrated magnetic jack before fixing the PHY position. Both can work; the decision depends on the approved circuit, footprint, signal path, and isolation needs. **Option** **Useful when** **Verify** Discrete magnetics Placement flexibility matters Extra route and keepout Integrated jack Edge area is limited Pinout and shield Integrated vs discrete does not change the need to read center-tap and termination guidance. Confirm the exact transformer ratio, approved pin mapping, and isolation requirements. Do not infer compatibility from identical connector footprints. ![Discrete Ethernet magnetics package next to a shielded RJ45 jack](https://www.bestpcbs.com/blog/wp-content/uploads/2026/11/ethernet-magnetics-layout.jpg)Illustrative discrete-magnetics layout. Check the space for copper keepouts and protection before committing to placement. ## rj45 pcb layout Treat the connector area as a system boundary. Place the connector to suit the enclosure, and follow the reference design for the specified separation between circuit ground and chassis or shield. Do not carry an ordinary ground pour across a required isolation keepout to make an otherwise shorter route. Plan the ESD discharge path and protection placement with the connector and PHY documentation; a short route on a drawing can still return transient current through the wrong area. ## rmii pcb layout guidelines RMII is a digital MAC-to-PHY interface, not a method for routing the cable pairs. For a 10/100 design using RMII, identify the clock source, then review the clock and associated signals against both device documents. Do not apply the MDI differential rule to RMII signals. The gigabit example normally needs a different MAC interface, such as RGMII when supported. Check its timing and configured clock delays separately; changing PHY mode changes which design rules apply. ## ethernet pcb routing guidelines Release the port only after you can show that the layout meets the selected part requirements and the board works under the intended conditions. In the controller example, first route the MDI channel away from the regulator’s noisy node. If layer changes are necessary, keep pair transitions balanced and provide the return path required by the reference stackup, without bridging the connector’s isolation boundary. 1. Cross-check schematic and footprint against the PHY, transformer, and jack documents. Confirm polarity, center taps, digital interface mode, and shield connection. 2. Review the released artwork and fabricator stackup for impedance, pair transitions, plane continuity, and keepouts. Resolve any deviations before order release. 3. On the first article, confirm power, clock, reset and link negotiation at the intended modes. Transfer sustained traffic, check error counters, and repeat with the intended cable, supply conditions and enclosure. A link LED alone does not establish margin. 4. Where required, run the specified physical-layer and EMC tests. If errors correlate with converter loading, review coupling and return paths before changing pair length. ## FAQ ### Are vias prohibited in Ethernet differential pairs? No universal rule prohibits them. Follow the PHY guidance, minimize unnecessary transitions, use comparable transitions on both conductors, and preserve the return path as required. Inspect the actual transition, not just the via count. ### Do all Ethernet MDI routes use two pairs? No. Conventional 100BASE-TX uses two pairs, while 1000BASE-T uses four. Confirm the PHY mode and connector mapping rather than copying a two-pair layout into a gigabit design. ### Can I swap pair polarity or pair positions? Do not assume so. Some devices can compensate for selected swaps, but support varies with device, interface, and mode. Check the exact PHY documentation and the magnetics pinout. ### Can I omit magnetics between two devices on the same board? Only if the selected devices and system requirements support the chosen topology. Follow a device-specific transformerless design note, and do not assume a board-to-board topology is suitable for a cable port. ### Can power and data share the same connector? Power over Ethernet does this with a compatible circuit and magnetics. It changes the connector, thermal and protection requirements. Do not repurpose an ordinary design without reviewing the power path and its applicable requirements. ### Do I need a four-layer PCB? Layer count alone is not a qualification test. Verify the target impedance, routing density, ground references and isolation boundaries in the proposed stackup. Use the selected device guide to decide whether the layout is credible. ### Is this guide for 10G or single-pair Ethernet? No. The examples cover common copper 10/100/1000 ports, not single-pair, 10G or serial backplane interfaces. Use the specifications and layout documents for the intended PHY and medium. ### What should I send for a stackup review? Provide the current layer count, impedance targets, routing layers, copper thickness, and board outline. Include the relevant PHY and connector part numbers and separate any additional timing constraints from fabrication tolerances. See the related [microstrip design guide](https://www.bestpcbs.com/blog/2026/11/microstrip-pcb/). ## References - Texas Instruments SNLA387: Ethernet PHY PCB Design Layout Checklist - Microchip AN2054: Gigabit Ethernet Guide - Microchip AN186: Ethernet Physical Layer Layout Guidelines For a board fabrication review, send the proposed stackup, differential impedance requirements, and current fabrication revision to Best Technology at [sales@bestpcbs.com](mailto:sales@bestpcbs.com).