# 22-Layer HDI PCB Design & Manufacturing: Stackup, Vias & Impedance _Published: 2026-11-12_ Table of Contents Toggle - What Is a 22-Layer HDI PCB, and Where Is It Used? - What Does a 22-Layer HDI PCB Stackup Look Like? - How Do 1+20+1 HDI Structures Support Complex Layer Interconnections? - How Are Microvias, Buried Vias, and Via-in-Pad Designed for 22-Layer HDI PCBs? - What Are the Critical Design Requirements for a 22-Layer HDI PCB? - How Can Signal Integrity and Controlled Impedance Be Maintained in 22-Layer HDI PCBs? - Which PCB Materials Are Suitable for High-Speed 22-Layer HDI Designs? - What Are the Main Challenges and Solutions in 22-Layer HDI PCB Manufacturing? - How Are 22-Layer HDI PCBs Fabricated and Quality Tested? - What Should You Consider When Prototyping a Complex 22-Layer HDI PCB? - What Is the Lead Time for 22-Layer HDI PCB Prototyping and Production? - What Factors Affect 22-Layer HDI PCB Manufacturing Costs? - Why Choose EBest Circuit for 22-Layer HDI PCB Manufacturing? - FAQs About 22-Layer HDI PCB Design & Manufacturing An [22-layer HDI PCB](https://www.bestpcbs.com/blog/2026/11/22-layer-hdi-pcb/) must accommodate dense BGA routing, high-speed signals, complex buried vias, and multiple power planes within strict manufacturing limits. When a design requires **0.10 mm microvias, deep buried vias, ±10% impedance tolerance, and a fixed board thickness**, can these requirements be achieved without changing the original layout? Possibly, but not on assumption alone. The proposed stackup, via spans, material constructions, and finished trace geometry must be checked together before an unchanged layout can be approved for fabrication. [EBest Circuit](https://www.bestpcbs.com/) provides **multilayer PCB manufacturing, HDI fabrication, and DFM review** for complex electronic projects. We help customers evaluate stackup construction, interconnection reliability, material compatibility, and manufacturing feasibility before prototyping and production. ![22-Layer HDI PCB, https://www.bestpcbs.com/blog/2026/11/22-layer-hdi-pcb/](https://www.bestpcbs.com/blog/wp-content/uploads/2026/11/22-layer-hdi-pcb-1.jpg) ## What Is a 22-Layer HDI PCB, and Where Is It Used? An [22-layer HDI PCB](https://www.bestpcbs.com/blog/2026/11/22-layer-hdi-pcb/) contains 22 conductive copper layers with high-density interconnections such as laser microvias, blind vias, buried vias, and via-in-pad structures. It provides additional routing capacity for high-pin-count components while reducing the space occupied by conventional through-hole connections. Typical applications include: - High-speed computing and FPGA boards: High-pin-count BGAs, DDR memory, SerDes interfaces, and multiple power domains. - Networking and telecommunications: Switches, routers, and communication equipment requiring controlled impedance and low-loss transmission. - Industrial VME systems: Processor cards with fixed mechanical dimensions, backplane connectors, and high-density routing. - Medical instrumentation: High-channel-count signal acquisition, imaging, and processing equipment. - Aerospace electronics: Compact control and communication hardware with project-specific reliability requirements. **Not every 22-layer PCB requires HDI construction.** Conventional multilayer fabrication may be sufficient when through-holes provide adequate routing space. HDI becomes more appropriate when BGA fanout, routing density, or signal transitions cannot be accommodated efficiently using conventional vias. ## What Does a 22-Layer HDI PCB Stackup Look Like? A 22-layer [HDI PCB](https://www.bestpcbs.com/products/HDI-board.htm) stackup distributes high-speed signal layers, ground planes, and power planes across 22 copper layers. Critical signal layers should be positioned next to suitable reference planes to support controlled impedance and continuous return-current paths. ![22-Layer HDI PCB, https://www.bestpcbs.com/blog/2026/11/22-layer-hdi-pcb/](https://www.bestpcbs.com/blog/wp-content/uploads/2026/11/22-layer-hdi-pcb-stackup.jpg) The following is an example of a symmetrical functional layer arrangement. **Layer Pair** **Layer Function** L1 / L22 Outer signal and BGA breakout L2 / L21 Ground reference L3 / L20 High-speed signal L4 / L19 Ground reference L5 / L18 Internal signal L6 / L17 Power distribution L7 / L16 Ground reference L8 / L15 Internal signal L9 / L14 Ground reference L10 / L13 High-speed signal L11 / L12 Central ground reference L3 and L20 can carry controlled-impedance stripline signals, while L10 and L13 provide additional high-speed routing channels. The remaining signal layers accommodate BGA fanout and internal connections. A production-ready stackup also requires: - Core and prepreg materials: Actual material constructions and dielectric properties. - Dielectric thickness: Individual spacing between copper layers. - Copper thickness: Finished copper weights for signal and power layers. - Impedance calculations: Trace geometry and reference-plane relationships for each controlled layer. - Lamination balance: Suitable copper distribution and mechanical stability. For a **2.25 mm nominal finished thickness**, the complete copper and dielectric construction must fit the approved mechanical requirements. Dielectric spacing cannot be adjusted independently because it also affects impedance and drilling geometry. ## How Do 1+20+1 HDI Structures Support Complex Layer Interconnections? A **22-layer 1+20+1 HDI PCB** consists of a 20-layer central structure with one HDI buildup layer on each side. Outer microvias provide compact surface connections, while buried vias and through-holes connect the required internal layers. The main interconnections include: - L1–L2 laser microvias: Connect top-side BGA pads and traces to the adjacent layer. - L21–L22 laser microvias: Provide corresponding bottom-side connections. - Internal buried vias: Connect selected layers without reaching the finished outer surfaces. - L1–L22 plated through-holes: Provide full-depth connections where required. When a signal microvia terminates on a ground-reference layer, its capture pad must be isolated from the surrounding ground copper and connected to the intended signal network. **1+20+1 versus 2+18+2 HDI construction** - 1+20+1: Suitable when one buildup level on each side provides sufficient BGA breakout and internal routing access. - 2+18+2: Provides additional buildup connections for denser routing but requires more sequential lamination and microvia processing. The appropriate construction depends on BGA escape routing, required layer transitions, and interconnect reliability. Additional buildup levels should address a specific routing limitation. ## How Are Microvias, Buried Vias, and Via-in-Pad Designed for 22-Layer HDI PCBs? **22-layer HDI PCB via design** must balance routing density, drilling depth, copper plating, and interconnect reliability. ![22-Layer HDI PCB, https://www.bestpcbs.com/blog/2026/11/22-layer-hdi-pcb/](https://www.bestpcbs.com/blog/wp-content/uploads/2026/11/22-layer-hdi-pcb-microvia.jpg) - Laser microvias: A 0.10 mm laser microvia provides a compact connection between adjacent buildup layers. Its feasibility depends on dielectric thickness, capture-pad dimensions, drilling geometry, and metallization. For example, a 0.10 mm laser-entry diameter with a 0.075 mm dielectric depth gives a nominal depth-to-diameter ratio of 0.75:1. - BGA via-in-pad: Filled and capped microvias allow routing beneath fine-pitch BGA pads. Copper filling, planarization, and capping must produce a flat, solderable surface. Voids or uneven capping can affect solder-joint quality. - Mechanical buried vias: An L2–L21 buried via may extend through most of the central structure. At approximately 2.0 mm drilling depth, a 0.20 mm drill diameter produces a 10:1 aspect ratio, while a 0.25 mm drill produces 8:1. If these dimensions represent finished holes, the actual drill sizes and aspect ratios must be recalculated. - Plated through-holes: Through-holes provide full-depth connections but consume routing space throughout the stackup. Unused portions of high-speed signal vias can create stubs, making antipad optimization or backdrilling relevant. **Deep buried-via manufacturability depends on hole-wall preparation and copper plating continuity.** High aspect ratios make uniform copper deposition more difficult. The drilling and plating processes must therefore be evaluated against the actual hole depth, not simply the specified diameter. ## What Are the Critical Design Requirements for a 22-Layer HDI PCB? A **22-layer HDI PCB** must meet its electrical, dimensional, and fabrication requirements within one approved construction. The following represents a demanding high-speed PCB project. **Design Parameter** **Example Specification** PCB layers 22 Board dimensions 228.35 × 160 mm Finished thickness 2.25 mm ±10% HDI construction 1+20+1 Laser microvias 0.10 mm, L1–L2 / L21–L22 Mechanical buried vias 0.20 / 0.25 mm, L2–L21 Plated through-holes 0.25 mm Minimum trace / spacing 85 / 100 µm BGA pitch 0.8 / 1.0 mm Inner signal copper 17 µm Selected power-plane copper 35 µm Outer copper 17 µm base, approximately 32 µm finished Controlled impedance 40/50Ω single-ended; 80/100Ω differential, ±10% High-speed interfaces SerDes up to 6.25 Gb/s; DDR3 Surface finish ENIG These are example project requirements, not guaranteed manufacturing capabilities. Three constraints require particular attention: - Fixed thickness: The approved 2.25 mm nominal thickness must accommodate all copper and dielectric layers. A ±10% finished-thickness tolerance does not authorize an unapproved change to the nominal stackup. - Fine-line geometry: An 85 µm trace must be evaluated against its finished copper thickness. Internal and external layers may require different etching compensation. - Impedance tolerance: A 40Ω ±10% requirement permits only ±4Ω deviation, which is tighter than a generic ±5Ω tolerance and requires specific capability confirmation. Industrial boards may also contain hundreds of press-fit connector holes. For example, a VME board requiring **105 holes at 0.60 mm and 320 holes at 1.00 mm** needs connector-specific finished-hole tolerances, plating specifications, and board-thickness compatibility. ENIG used on BGA solder pads does not automatically qualify the finish inside every press-fit hole. ## How Can Signal Integrity and Controlled Impedance Be Maintained in 22-Layer HDI PCBs? **Controlled impedance in a 22-layer HDI PCB** depends on finished trace geometry, dielectric spacing, copper thickness, material properties, and reference-plane continuity. For high-speed interfaces such as SerDes and DDR3, the main requirements are: - Finished conductor dimensions: Calculate impedance using etched trace geometry, copper thickness, and differential-pair spacing rather than nominal CAD dimensions alone. - Continuous reference planes: Keep critical signals over suitable references and provide appropriate return-current paths during layer transitions. - Controlled via transitions: Review capture pads, antipads, via barrels, and unused stubs that can introduce reflections. - Transmission-line loss: Evaluate material Df, copper roughness, channel length, and connector transitions against the required insertion-loss budget. - Manufacturing verification: Use representative impedance coupons to measure controlled-impedance structures under agreed test conditions. For a **100Ω differential pair with ±10% tolerance**, the acceptable measured range is 90–110Ω. At **6.25 Gb/s NRZ signaling**, the Nyquist frequency is approximately 3.125 GHz. Higher-frequency components also contribute to channel performance, making dielectric loss and via transitions important. DDR3 interfaces additionally require suitable clock and data-strobe routing, timing margins, and termination. **Meeting impedance tolerance does not guarantee complete signal integrity.** Coupon testing verifies selected fabricated transmission lines, while full-channel performance requires electrical simulation or system-level validation. ## Which PCB Materials Are Suitable for High-Speed 22-Layer HDI Designs? **High-speed 22-layer HDI PCBs** require laminates with suitable dielectric properties, thermal performance, available thicknesses, and compatibility with the specified HDI construction. Common material options include: - Isola I-Tera MT40 — Very-low-loss laminate Suitable for demanding high-speed digital applications. A published 0.051 mm core construction has **Dk 3.30 and Df 0.0026 at 10 GHz**. Other constructions have different values, so the selected core and prepreg specifications must be used for impedance calculations. - Panasonic MEGTRON 6 — Ultra-low-loss laminate Used in high-speed networking, communication, and computing systems. Panasonic lists **Dk 3.34 and Df 0.0037 at 13 GHz** for its R-5775(N) construction. Other variants have different dielectric properties and available constructions. - Shengyi S7439 — Low-loss high-speed laminate Suitable for servers, switches, networking equipment, and backplanes. Shengyi lists **Dk 3.80 and Df 0.0068 at 10 GHz** using the specified IPC test method. Material selection depends on the required channel-loss budget and stackup. - ITEQ IT-968G — Very-low-loss, high-Tg laminate Used in high-speed networking and server applications. For a specified 55% resin-content construction, ITEQ lists **Dk 3.59 and Df 0.0050 at 10 GHz**. Other resin contents produce different dielectric values. - TUC TU-862HF — High-Tg, halogen-free laminate Suitable for multilayer applications requiring thermal stability and halogen-free construction. Published data for a specified 50% resin-content construction includes **Dk 4.4 and Df 0.010 at 1 GHz**. These figures use different test conditions from the higher-frequency data above and should not be compared directly. TU-862HF is not an automatic electrical replacement for I-Tera MT40 or MEGTRON 6. **Can materials be substituted without changing the original layout?** Substitution is possible only when the replacement satisfies the approved electrical and mechanical requirements. 1. Recalculate the stackup: Select available core and prepreg constructions that maintain the specified board thickness. 2. Recalculate impedance: Verify every controlled layer using the replacement material’s dielectric properties. 3. Check signal loss: Confirm that the substitute satisfies the required high-speed channel-loss budget. 4. Verify manufacturing compatibility: Evaluate lamination, thermal expansion, dimensional stability, and HDI processing. 5. Confirm permitted compensation: Determine whether allowable conductor adjustments can meet impedance requirements without changing the approved routing. For urgent prototypes, in-stock laminate materials may reduce sourcing delays. However, **similar nominal Dk values do not guarantee equivalent impedance, insertion loss, or manufacturing behavior**. Material substitutions affecting the approved construction require customer confirmation. ## What Are the Main Challenges and Solutions in 22-Layer HDI PCB Manufacturing? **22-layer HDI PCB manufacturing** requires accurate layer registration, reliable interconnections, fine-line control, and dimensional stability. The primary challenges and solutions are: - Multilayer registration errors **Challenge:** Material movement during lamination can shift internal copper features and reduce alignment between buried vias and capture pads. **Solution:** Apply material-specific dimensional compensation, controlled lamination conditions, and registration inspection before subsequent processing. - Deep buried-via plating defects **Challenge:** High-aspect-ratio holes may develop nonuniform barrel copper or plating discontinuities. **Solution:** Use drilling, desmear, and plating processes suitable for the actual hole depth. Verify barrel copper continuity through microsection inspection. - Microvia interface failures **Challenge:** Poor target-pad preparation or insufficient metallization can create weak connections that may fail after thermal exposure. **Solution:** Control laser drilling, pad preparation, copper deposition, filling, and capping. Apply structural and thermal reliability verification when required. - Fine-line and impedance variation **Challenge:** Etching variation or uneven finished copper thickness can alter conductor geometry and impedance. **Solution:** Apply copper-dependent etching compensation, measure finished trace dimensions, and verify impedance with representative coupons. - Board warpage and thickness variation **Challenge:** Unbalanced copper distribution and dielectric construction can cause deformation during lamination. **Solution:** Balance the stackup where practical, control lamination conditions, and inspect finished dimensions. - Press-fit connector-hole defects **Challenge:** Incorrect hole dimensions or plating may damage connections during installation. **Solution:** Follow the connector manufacturer’s finished-hole and plating requirements, supported by dimensional inspection. ## How Are 22-Layer HDI PCBs Fabricated and Quality Tested? **22-layer HDI PCB fabrication** involves inner-layer processing, buried-via construction, central lamination, outer HDI buildup, and final verification. ![22-Layer HDI PCB, https://www.bestpcbs.com/blog/2026/11/22-layer-hdi-pcb/](https://www.bestpcbs.com/blog/wp-content/uploads/2026/11/22-layer-hdi-pcb-testing.jpg) For a typical 1+20+1 structure, the manufacturing stages are: 1. Inner-layer fabrication: Image, etch, and inspect internal copper patterns using AOI. 2. Buried-via processing: Drill, desmear, metallize, and plate internal connections before subsequent lamination makes them inaccessible. 3. Central-structure lamination: Align and laminate the 20-layer central structure using the approved materials. 4. HDI buildup: Add outer dielectric and copper layers, laser-drill microvias, and complete metallization, filling, and capping where specified. 5. Final PCB processing: Complete applicable through-hole plating, outer-layer circuits, solder mask, ENIG, and profiling. **Quality verification includes:** - Electrical testing: Detects opens and shorts in the completed circuitry. - Microsection inspection: Examines buried-via copper, microvia interfaces, layer registration, and filling quality. - Impedance testing: Measures specified transmission-line structures using representative coupons. - Dimensional inspection: Confirms finished thickness, board outline, and critical connector-hole dimensions. - Thermal reliability testing: Evaluates interconnect behavior under agreed thermal-stress conditions when required. Inner-layer AOI is performed during fabrication to detect conductor defects before lamination. The applicable **IPC-6012 performance class** and project-specific requirements determine the acceptance criteria. Inspection records and required reports should be agreed upon before manufacturing. ## What Should You Consider When Prototyping a Complex 22-Layer HDI PCB? **22-layer HDI PCB prototyping** should verify a construction that can be repeated during production, not merely demonstrate that a small number of boards can be fabricated. Even a **3–4-piece prototype order** may require extensive engineering preparation when the design contains deep buried vias, filled microvias, and strict mechanical requirements. Before prototype release, confirm: - Stackup: Approved materials, dielectric thicknesses, copper weights, and layer assignments. - Via construction: Hole sizes, layer connections, and filling or capping requirements. - Impedance: Controlled layers, target values, tolerances, and permitted manufacturing compensation. - Mechanical specifications: Board dimensions, connector positions, finished-hole sizes, and critical tolerances. - Acceptance criteria: Required electrical, impedance, structural, and reliability verification. Any necessary material substitution or manufacturing adjustment should be approved before fabrication. Maintaining the intended production construction during prototyping reduces the risk of further qualification or redesign. ## What Is the Lead Time for 22-Layer HDI PCB Prototyping and Production? The **lead time for a 22-layer HDI PCB** depends on material availability, manufacturing complexity, engineering approval, and testing requirements. The main scheduling factors are: - Materials: Availability of specified laminate and prepreg constructions. - HDI buildup: Sequential lamination, laser drilling, microvia filling, and capping. - Buried vias: Specialized drilling and plating requirements for deep mechanical holes. - Engineering approval: Resolution of stackup, impedance, or mechanical conflicts. - Testing: Required impedance measurements, microsections, and reliability verification. For urgent prototypes, complete fabrication data and approved material alternatives can reduce avoidable delays. **Prototype quantity alone does not determine lead time.** A four-piece order may require the same critical processing stages as a larger production batch. Delivery should be confirmed after reviewing the approved construction, materials, and production capacity. ## What Factors Affect 22-Layer HDI PCB Manufacturing Costs? The cost of a **22-layer HDI PCB** depends on materials, buildup structure, via complexity, fabrication tolerances, inspection, and order quantity. The main cost drivers include: - HDI buildup: Additional lamination and laser-drilling operations. - Via construction: Deep buried holes and filled or capped microvias. - Materials: Low-loss laminates and specialized dielectric constructions. - Fine-line fabrication: Tight conductor dimensions and reduced manufacturing margins. - Quality verification: Additional impedance testing, microsections, and reliability checks. - Order quantity: Engineering and setup costs spread across fewer prototype boards. **Cost optimization options include:** - Use 1+20+1 instead of a higher-order buildup when routing permits. - Avoid filled vias where they are not needed for electrical or assembly requirements. - Review noncritical tolerances that unnecessarily restrict manufacturing. - Consider approved materials already available for production. - Maintain a consistent construction between prototypes and later batches. Any adjustment must preserve the required electrical performance, mechanical fit, and interconnect reliability. ## Why Choose EBest Circuit for 22-Layer HDI PCB Manufacturing? For a complex **22-layer HDI PCB**, you need clear answers about manufacturing feasibility, material availability, quality verification, and delivery before placing an order. EBest Circuit provides multilayer PCB fabrication, HDI manufacturing support, DFM review, and PCB assembly services. We can help you: - Identify manufacturing conflicts before production: Submit your fabrication files for a free DFM check covering via depth, copper thickness, dielectric construction, and mechanical tolerances. - Evaluate complex HDI requirements: Our capability information includes special multilayer constructions up to 32 layers and laser blind vias down to 0.10 mm. We assess the complete proposed structure rather than relying only on individual process limits. - Review material alternatives: If the specified laminate is unavailable, we can evaluate candidate materials against the approved impedance, thickness, and manufacturing requirements. - Clarify quality verification: Define the required electrical tests, impedance measurements, microsections, and dimensional inspection records before production. - Support prototype-to-production continuity: Maintain the approved manufacturing revision, material specifications, and critical construction requirements for subsequent orders. - Combine PCB fabrication and assembly: We also provide SMT assembly, component sourcing, and specified testing for customers requiring complete PCBAs. For demanding **22-layer 1+20+1 HDI PCB projects**, our engineering team can review the fabrication package and confirm the feasible manufacturing approach, quotation, and lead time. ## FAQs About 22-Layer HDI PCB Design & Manufacturing **Q1: Can an NDA be signed before sharing confidential PCB files?** **A1:** Yes. Customers can request a non-disclosure agreement before submitting confidential design information. The terms and file-handling conditions should be agreed upon before technical data is exchanged. **Q2: Is IPC Class 3 required for every 22-layer HDI PCB?** **A2:** No. The acceptance class depends on the product’s intended use and contractual reliability requirements. A 22-layer construction does not automatically require Class 3. **Q3: Can individual prototypes be serialized for traceability?** **A3:** Serial-number marking can be specified in the fabrication requirements. The marking location, format, and required traceability records should be confirmed before manufacturing. **Q4: What happens if Gerber files and drill drawings contain different revisions?** **A4:** Fabrication should not begin until the discrepancy is resolved. One approved revision must control the artwork, drilling data, stackup, and fabrication notes. **Q5: Can customer-supplied laminate materials be used?** **A5:** Customer-supplied materials may be evaluated for identification, condition, traceability, dimensions, and process compatibility. Acceptance must be confirmed before fabrication. **Q6: Can different PCB designs be combined into one manufacturing panel?** **A6:** Mixed-design panelization may be possible when the boards have compatible materials, thicknesses, copper constructions, and processing requirements. Different HDI structures may prevent combined production. **Q7: Can special packaging be requested for finished HDI PCBs?** **A7:** Yes. Customers can specify individual board protection, moisture-control packaging, labeling, and other handling requirements appropriate to the product and shipping conditions. **Q8: Can a certificate of conformity be supplied with the PCB order?** **A8:** A certificate of conformity can be requested as part of the agreed delivery documentation. It should identify the relevant order, product revision, and applicable acceptance requirements. **Q9: Which surface finish should be specified for a 22-layer HDI PCB?** **A9:** The finish should be selected for the component termination, assembly process, storage period, flatness needs, and reliability requirements. Confirm the permitted finish and thickness in the fabrication notes before quotation. **Q10: Can a 22-layer HDI PCB include edge plating or castellated features?** **A10:** These features may be feasible, but their geometry, copper coverage, board-edge clearance, panelization, and inspection requirements must be reviewed with the complete stackup and outline data. Are you developing a **22-layer HDI PCB** with dense BGA routing, deep buried vias, controlled impedance, or fixed mechanical dimensions? EBest Circuit can review your design requirements and assess manufacturing options for prototypes and production. Send your Gerber or ODB++ files, stackup, drill specifications, material requirements, **quantity, required delivery date, and delivery location** to **sales@bestpcbs.com**. Request a **free DFM check** and a quotation for your custom 22-layer HDI PCB project.